sh: Optimized cache handling for SH-4/SH-4A caches.

This reworks some of the SH-4 cache handling code to more easily
accomodate newer-style caches (particularly for the > direct-mapped
case), as well as optimizing some of the old code.

Signed-off-by: Richard Curnow <richard.curnow@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

1 files changed, 11 insertions, 0 deletions

diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 42427b79697b..1208da8fe5db 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -113,6 +113,11 @@ int __init detect_cpu_and_cache_system(void)
                 break;
         }
 
+#ifdef CONFIG_SH_DIRECT_MAPPED
+        cpu_data->icache.ways = 1;
+        cpu_data->dcache.ways = 1;
+#endif
+
         /*
          * On anything that's not a direct-mapped cache, look to the CVR
          * for I/D-cache specifics.
@@ -125,6 +130,9 @@ int __init detect_cpu_and_cache_system(void)
                         (cpu_data->icache.way_incr - (1 << 5));
         }
 
+        cpu_data->icache.way_size = cpu_data->icache.sets *
+                                    cpu_data->icache.linesz;
+
         if (cpu_data->dcache.ways > 1) {
                 size = sizes[(cvr >> 16) & 0xf];
                 cpu_data->dcache.way_incr       = (size >> 1);
@@ -133,6 +141,9 @@ int __init detect_cpu_and_cache_system(void)
                         (cpu_data->dcache.way_incr - (1 << 5));
         }
 
+        cpu_data->dcache.way_size = cpu_data->dcache.sets *
+                                    cpu_data->dcache.linesz;
+
         return 0;
 }