diff options
author | Magnus Damm <damm@igel.co.jp> | 2007-08-16 11:45:35 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2007-09-20 22:57:50 -0400 |
commit | 5c37e025352b993d8726b0207ff2270b2f2bc7d6 (patch) | |
tree | 87463d1c79600c37d3df06cbdbdf14bdc6de5094 /arch/sh/kernel/cpu/sh4 | |
parent | 46420e49c9fd76defecfb3f048ab20c5a72dfd0a (diff) |
sh: intc - mark data structures as __initdata
With the intc core improved it is now possible to put the intc data
structures in the initdata section.
Version two of this patch puts the __initdata inside DECLARE_INTC_DESC()
and removes the __initdata included in the board specific r2d code.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4')
-rw-r--r-- | arch/sh/kernel/cpu/sh4/setup-sh7750.c | 26 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4/setup-sh7760.c | 12 |
2 files changed, 19 insertions, 19 deletions
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c index 062c3c1b2431..523f68a9ce0e 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c | |||
@@ -104,7 +104,7 @@ enum { | |||
104 | DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, | 104 | DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, |
105 | }; | 105 | }; |
106 | 106 | ||
107 | static struct intc_vect vectors[] = { | 107 | static struct intc_vect vectors[] __initdata = { |
108 | INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), | 108 | INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), |
109 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), | 109 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
110 | INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), | 110 | INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), |
@@ -118,7 +118,7 @@ static struct intc_vect vectors[] = { | |||
118 | INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), | 118 | INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), |
119 | }; | 119 | }; |
120 | 120 | ||
121 | static struct intc_group groups[] = { | 121 | static struct intc_group groups[] __initdata = { |
122 | INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), | 122 | INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), |
123 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), | 123 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), |
124 | INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), | 124 | INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), |
@@ -126,13 +126,13 @@ static struct intc_group groups[] = { | |||
126 | INTC_GROUP(REF, REF_RCMI, REF_ROVI), | 126 | INTC_GROUP(REF, REF_RCMI, REF_ROVI), |
127 | }; | 127 | }; |
128 | 128 | ||
129 | static struct intc_prio priorities[] = { | 129 | static struct intc_prio priorities[] __initdata = { |
130 | INTC_PRIO(SCIF, 3), | 130 | INTC_PRIO(SCIF, 3), |
131 | INTC_PRIO(SCI1, 3), | 131 | INTC_PRIO(SCI1, 3), |
132 | INTC_PRIO(DMAC, 7), | 132 | INTC_PRIO(DMAC, 7), |
133 | }; | 133 | }; |
134 | 134 | ||
135 | static struct intc_prio_reg prio_registers[] = { | 135 | static struct intc_prio_reg prio_registers[] __initdata = { |
136 | { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, | 136 | { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, |
137 | { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, | 137 | { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, |
138 | { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, | 138 | { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, |
@@ -150,13 +150,13 @@ static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups, | |||
150 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | 150 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ |
151 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | 151 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ |
152 | defined(CONFIG_CPU_SUBTYPE_SH7091) | 152 | defined(CONFIG_CPU_SUBTYPE_SH7091) |
153 | static struct intc_vect vectors_dma4[] = { | 153 | static struct intc_vect vectors_dma4[] __initdata = { |
154 | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), | 154 | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), |
155 | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), | 155 | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), |
156 | INTC_VECT(DMAC_DMAE, 0x6c0), | 156 | INTC_VECT(DMAC_DMAE, 0x6c0), |
157 | }; | 157 | }; |
158 | 158 | ||
159 | static struct intc_group groups_dma4[] = { | 159 | static struct intc_group groups_dma4[] __initdata = { |
160 | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, | 160 | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, |
161 | DMAC_DMTE3, DMAC_DMAE), | 161 | DMAC_DMTE3, DMAC_DMAE), |
162 | }; | 162 | }; |
@@ -168,7 +168,7 @@ static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4", | |||
168 | 168 | ||
169 | /* SH7750R and SH7751R both have 8-channel DMA controllers */ | 169 | /* SH7750R and SH7751R both have 8-channel DMA controllers */ |
170 | #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R) | 170 | #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R) |
171 | static struct intc_vect vectors_dma8[] = { | 171 | static struct intc_vect vectors_dma8[] __initdata = { |
172 | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), | 172 | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), |
173 | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), | 173 | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), |
174 | INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), | 174 | INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), |
@@ -176,7 +176,7 @@ static struct intc_vect vectors_dma8[] = { | |||
176 | INTC_VECT(DMAC_DMAE, 0x6c0), | 176 | INTC_VECT(DMAC_DMAE, 0x6c0), |
177 | }; | 177 | }; |
178 | 178 | ||
179 | static struct intc_group groups_dma8[] = { | 179 | static struct intc_group groups_dma8[] __initdata = { |
180 | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, | 180 | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, |
181 | DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, | 181 | DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, |
182 | DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), | 182 | DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), |
@@ -191,11 +191,11 @@ static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8", | |||
191 | #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | 191 | #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ |
192 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | 192 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ |
193 | defined(CONFIG_CPU_SUBTYPE_SH7751R) | 193 | defined(CONFIG_CPU_SUBTYPE_SH7751R) |
194 | static struct intc_vect vectors_tmu34[] = { | 194 | static struct intc_vect vectors_tmu34[] __initdata = { |
195 | INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), | 195 | INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), |
196 | }; | 196 | }; |
197 | 197 | ||
198 | static struct intc_mask_reg mask_registers[] = { | 198 | static struct intc_mask_reg mask_registers[] __initdata = { |
199 | { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ | 199 | { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ |
200 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 200 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
201 | 0, 0, 0, 0, 0, 0, TMU4, TMU3, | 201 | 0, 0, 0, 0, 0, 0, TMU4, TMU3, |
@@ -210,7 +210,7 @@ static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34", | |||
210 | #endif | 210 | #endif |
211 | 211 | ||
212 | /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ | 212 | /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ |
213 | static struct intc_vect vectors_irlm[] = { | 213 | static struct intc_vect vectors_irlm[] __initdata = { |
214 | INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), | 214 | INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), |
215 | INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), | 215 | INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), |
216 | }; | 216 | }; |
@@ -220,14 +220,14 @@ static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL, | |||
220 | 220 | ||
221 | /* SH7751 and SH7751R both have PCI */ | 221 | /* SH7751 and SH7751R both have PCI */ |
222 | #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R) | 222 | #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R) |
223 | static struct intc_vect vectors_pci[] = { | 223 | static struct intc_vect vectors_pci[] __initdata = { |
224 | INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), | 224 | INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), |
225 | INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), | 225 | INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), |
226 | INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), | 226 | INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), |
227 | INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), | 227 | INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), |
228 | }; | 228 | }; |
229 | 229 | ||
230 | static struct intc_group groups_pci[] = { | 230 | static struct intc_group groups_pci[] __initdata = { |
231 | INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, | 231 | INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
232 | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), | 232 | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), |
233 | }; | 233 | }; |
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c index 6b4e48cbe7ff..7a898cb1d940 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c | |||
@@ -43,7 +43,7 @@ enum { | |||
43 | DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF, | 43 | DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF, |
44 | }; | 44 | }; |
45 | 45 | ||
46 | static struct intc_vect vectors[] = { | 46 | static struct intc_vect vectors[] __initdata = { |
47 | INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), | 47 | INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), |
48 | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), | 48 | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), |
49 | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), | 49 | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), |
@@ -78,7 +78,7 @@ static struct intc_vect vectors[] = { | |||
78 | INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), | 78 | INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), |
79 | }; | 79 | }; |
80 | 80 | ||
81 | static struct intc_group groups[] = { | 81 | static struct intc_group groups[] __initdata = { |
82 | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, | 82 | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, |
83 | DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, | 83 | DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, |
84 | DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), | 84 | DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), |
@@ -92,7 +92,7 @@ static struct intc_group groups[] = { | |||
92 | INTC_GROUP(REF, REF_RCMI, REF_ROVI), | 92 | INTC_GROUP(REF, REF_RCMI, REF_ROVI), |
93 | }; | 93 | }; |
94 | 94 | ||
95 | static struct intc_prio priorities[] = { | 95 | static struct intc_prio priorities[] __initdata = { |
96 | INTC_PRIO(SCIF0, 3), | 96 | INTC_PRIO(SCIF0, 3), |
97 | INTC_PRIO(SCIF1, 3), | 97 | INTC_PRIO(SCIF1, 3), |
98 | INTC_PRIO(SCIF2, 3), | 98 | INTC_PRIO(SCIF2, 3), |
@@ -101,7 +101,7 @@ static struct intc_prio priorities[] = { | |||
101 | INTC_PRIO(DMABRG, 13), | 101 | INTC_PRIO(DMABRG, 13), |
102 | }; | 102 | }; |
103 | 103 | ||
104 | static struct intc_mask_reg mask_registers[] = { | 104 | static struct intc_mask_reg mask_registers[] __initdata = { |
105 | { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ | 105 | { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ |
106 | { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21, | 106 | { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21, |
107 | SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC, | 107 | SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC, |
@@ -117,7 +117,7 @@ static struct intc_mask_reg mask_registers[] = { | |||
117 | 0, MFI, 0, 0, 0, 0, ADC, CMT, } }, | 117 | 0, MFI, 0, 0, 0, 0, ADC, CMT, } }, |
118 | }; | 118 | }; |
119 | 119 | ||
120 | static struct intc_prio_reg prio_registers[] = { | 120 | static struct intc_prio_reg prio_registers[] __initdata = { |
121 | { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, | 121 | { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, |
122 | { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, | 122 | { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, |
123 | { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } }, | 123 | { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } }, |
@@ -134,7 +134,7 @@ static struct intc_prio_reg prio_registers[] = { | |||
134 | static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups, | 134 | static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups, |
135 | priorities, mask_registers, prio_registers, NULL); | 135 | priorities, mask_registers, prio_registers, NULL); |
136 | 136 | ||
137 | static struct intc_vect vectors_irq[] = { | 137 | static struct intc_vect vectors_irq[] __initdata = { |
138 | INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), | 138 | INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), |
139 | INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), | 139 | INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), |
140 | }; | 140 | }; |