diff options
| author | Magnus Damm <damm@igel.co.jp> | 2007-08-12 02:22:02 -0400 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2007-09-20 22:57:49 -0400 |
| commit | 6ef5fb2cfcedaab4a43493c8f2305a67c0ce1af6 (patch) | |
| tree | ba5b4c0a19a1d81047d49488b6fe3e3b02e824cf /arch/sh/kernel/cpu/sh4/setup-sh7760.c | |
| parent | d6aee69ca11550f3ca325ceaa020ea74e173478f (diff) | |
sh: intc - add a clear register to struct intc_prio_reg
We need a secondary register member in struct intc_prio_reg to support
dual priority registers used by ipi on x3.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4/setup-sh7760.c')
| -rw-r--r-- | arch/sh/kernel/cpu/sh4/setup-sh7760.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c index 6a6686d71fbc..6b4e48cbe7ff 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c | |||
| @@ -118,17 +118,17 @@ static struct intc_mask_reg mask_registers[] = { | |||
| 118 | }; | 118 | }; |
| 119 | 119 | ||
| 120 | static struct intc_prio_reg prio_registers[] = { | 120 | static struct intc_prio_reg prio_registers[] = { |
| 121 | { 0xffd00004, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, | 121 | { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, |
| 122 | { 0xffd00008, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, | 122 | { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, |
| 123 | { 0xffd0000c, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } }, | 123 | { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } }, |
| 124 | { 0xffd00010, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, | 124 | { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, |
| 125 | { 0xfe080000, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, | 125 | { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, |
| 126 | { 0xfe080004, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1, | 126 | { 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1, |
| 127 | HAC0, HAC1, I2C0, I2C1 } }, | 127 | HAC0, HAC1, I2C0, I2C1 } }, |
| 128 | { 0xfe080008, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0, | 128 | { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0, |
| 129 | SCIF1, SCIF2, SIM, HSPI } }, | 129 | SCIF1, SCIF2, SIM, HSPI } }, |
| 130 | { 0xfe08000c, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0, | 130 | { 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0, |
| 131 | MFI, 0, ADC, CMT } }, | 131 | MFI, 0, ADC, CMT } }, |
| 132 | }; | 132 | }; |
| 133 | 133 | ||
| 134 | static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups, | 134 | static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups, |