diff options
author | Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | 2007-12-25 21:45:06 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2008-01-27 23:19:02 -0500 |
commit | 31a49c4bf8f964b7a9897baa889916d71b51d9c1 (patch) | |
tree | e6c900dfbdf51d97d4c189a712a8c4e1aa059cf4 /arch/sh/kernel/cpu/sh3 | |
parent | 52e8b118ecd17185ce514cd3f955094c1d8f4288 (diff) |
sh: Add support for SH7721 CPU subtype.
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh3')
-rw-r--r-- | arch/sh/kernel/cpu/sh3/Makefile | 1 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh3/probe.c | 3 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh3/setup-sh7720.c | 11 |
3 files changed, 13 insertions, 2 deletions
diff --git a/arch/sh/kernel/cpu/sh3/Makefile b/arch/sh/kernel/cpu/sh3/Makefile index 646eb6933614..1afd05e62d1c 100644 --- a/arch/sh/kernel/cpu/sh3/Makefile +++ b/arch/sh/kernel/cpu/sh3/Makefile | |||
@@ -13,6 +13,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setup-sh770x.o | |||
13 | obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o | 13 | obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o |
14 | obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o | 14 | obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o |
15 | obj-$(CONFIG_CPU_SUBTYPE_SH7720) += setup-sh7720.o | 15 | obj-$(CONFIG_CPU_SUBTYPE_SH7720) += setup-sh7720.o |
16 | obj-$(CONFIG_CPU_SUBTYPE_SH7721) += setup-sh7720.o | ||
16 | 17 | ||
17 | # Primary on-chip clocks (common) | 18 | # Primary on-chip clocks (common) |
18 | clock-$(CONFIG_CPU_SH3) := clock-sh3.o | 19 | clock-$(CONFIG_CPU_SH3) := clock-sh3.o |
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c index 22070e43e34d..fcc80bb7bee7 100644 --- a/arch/sh/kernel/cpu/sh3/probe.c +++ b/arch/sh/kernel/cpu/sh3/probe.c | |||
@@ -84,6 +84,9 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void) | |||
84 | #if defined(CONFIG_CPU_SUBTYPE_SH7720) | 84 | #if defined(CONFIG_CPU_SUBTYPE_SH7720) |
85 | boot_cpu_data.type = CPU_SH7720; | 85 | boot_cpu_data.type = CPU_SH7720; |
86 | #endif | 86 | #endif |
87 | #if defined(CONFIG_CPU_SUBTYPE_SH7721) | ||
88 | boot_cpu_data.type = CPU_SH7721; | ||
89 | #endif | ||
87 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) | 90 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) |
88 | boot_cpu_data.type = CPU_SH7705; | 91 | boot_cpu_data.type = CPU_SH7705; |
89 | 92 | ||
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c index a0929b8a95ae..00facd028a08 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c | |||
@@ -127,8 +127,11 @@ static struct intc_vect vectors[] __initdata = { | |||
127 | INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1_DEI0, 0x800), | 127 | INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1_DEI0, 0x800), |
128 | INTC_VECT(DMAC1_DEI1, 0x820), INTC_VECT(DMAC1_DEI2, 0x840), | 128 | INTC_VECT(DMAC1_DEI1, 0x820), INTC_VECT(DMAC1_DEI2, 0x840), |
129 | INTC_VECT(DMAC1_DEI3, 0x860), INTC_VECT(LCDC, 0x900), | 129 | INTC_VECT(DMAC1_DEI3, 0x860), INTC_VECT(LCDC, 0x900), |
130 | INTC_VECT(SSL, 0x980), INTC_VECT(USBFI0, 0xa20), | 130 | #if defined(CONFIG_CPU_SUBTYPE_SH7720) |
131 | INTC_VECT(USBFI1, 0xa40), INTC_VECT(USBHI, 0xa60), | 131 | INTC_VECT(SSL, 0x980), |
132 | #endif | ||
133 | INTC_VECT(USBFI0, 0xa20), INTC_VECT(USBFI1, 0xa40), | ||
134 | INTC_VECT(USBHI, 0xa60), | ||
132 | INTC_VECT(DMAC2_DEI4, 0xb80), INTC_VECT(DMAC2_DEI5, 0xba0), | 135 | INTC_VECT(DMAC2_DEI4, 0xb80), INTC_VECT(DMAC2_DEI5, 0xba0), |
133 | INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00), | 136 | INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00), |
134 | INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80), | 137 | INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80), |
@@ -168,7 +171,11 @@ static struct intc_prio_reg prio_registers[] __initdata = { | |||
168 | { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, | 171 | { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, |
169 | { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, | 172 | { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, |
170 | { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } }, | 173 | { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } }, |
174 | #if defined(CONFIG_CPU_SUBTYPE_SH7720) | ||
171 | { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } }, | 175 | { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } }, |
176 | #else | ||
177 | { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, 0 } }, | ||
178 | #endif | ||
172 | { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } }, | 179 | { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } }, |
173 | { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } }, | 180 | { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } }, |
174 | { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } }, | 181 | { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } }, |