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authorPaul Mundt <lethal@linux-sh.org>2007-09-27 05:18:39 -0400
committerPaul Mundt <lethal@linux-sh.org>2007-09-27 05:18:39 -0400
commitcb7af21f7d370edb3a6a6d3e15cb17c8fd61591e (patch)
tree9042e4b322593adc3864b28a8c0899d7af7a52da /arch/sh/kernel/cpu/sh3
parentc3af39758ce49b79570ab5ff2f64e0ea5fd82c9b (diff)
sh: Use boot_cpu_data for CPU probe.
This moves off of smp_processor_id() and only sets the probe information for the boot CPU directly. This will be copied out for the secondaries, so there's no reason to do this each time. This also allows for some header tidying. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh3')
-rw-r--r--arch/sh/kernel/cpu/sh3/probe.c47
1 files changed, 23 insertions, 24 deletions
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index 1a66cf636a9d..bf579e061e09 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -50,47 +50,47 @@ int __init detect_cpu_and_cache_system(void)
50 50
51 back_to_P1(); 51 back_to_P1();
52 52
53 current_cpu_data.dcache.ways = 4; 53 boot_cpu_data.dcache.ways = 4;
54 current_cpu_data.dcache.entry_shift = 4; 54 boot_cpu_data.dcache.entry_shift = 4;
55 current_cpu_data.dcache.linesz = L1_CACHE_BYTES; 55 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
56 current_cpu_data.dcache.flags = 0; 56 boot_cpu_data.dcache.flags = 0;
57 57
58 /* 58 /*
59 * 7709A/7729 has 16K cache (256-entry), while 7702 has only 59 * 7709A/7729 has 16K cache (256-entry), while 7702 has only
60 * 2K(direct) 7702 is not supported (yet) 60 * 2K(direct) 7702 is not supported (yet)
61 */ 61 */
62 if (data0 == data1 && data2 == data3) { /* Shadow */ 62 if (data0 == data1 && data2 == data3) { /* Shadow */
63 current_cpu_data.dcache.way_incr = (1 << 11); 63 boot_cpu_data.dcache.way_incr = (1 << 11);
64 current_cpu_data.dcache.entry_mask = 0x7f0; 64 boot_cpu_data.dcache.entry_mask = 0x7f0;
65 current_cpu_data.dcache.sets = 128; 65 boot_cpu_data.dcache.sets = 128;
66 current_cpu_data.type = CPU_SH7708; 66 boot_cpu_data.type = CPU_SH7708;
67 67
68 current_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC; 68 boot_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC;
69 } else { /* 7709A or 7729 */ 69 } else { /* 7709A or 7729 */
70 current_cpu_data.dcache.way_incr = (1 << 12); 70 boot_cpu_data.dcache.way_incr = (1 << 12);
71 current_cpu_data.dcache.entry_mask = 0xff0; 71 boot_cpu_data.dcache.entry_mask = 0xff0;
72 current_cpu_data.dcache.sets = 256; 72 boot_cpu_data.dcache.sets = 256;
73 current_cpu_data.type = CPU_SH7729; 73 boot_cpu_data.type = CPU_SH7729;
74 74
75#if defined(CONFIG_CPU_SUBTYPE_SH7706) 75#if defined(CONFIG_CPU_SUBTYPE_SH7706)
76 current_cpu_data.type = CPU_SH7706; 76 boot_cpu_data.type = CPU_SH7706;
77#endif 77#endif
78#if defined(CONFIG_CPU_SUBTYPE_SH7710) 78#if defined(CONFIG_CPU_SUBTYPE_SH7710)
79 current_cpu_data.type = CPU_SH7710; 79 boot_cpu_data.type = CPU_SH7710;
80#endif 80#endif
81#if defined(CONFIG_CPU_SUBTYPE_SH7712) 81#if defined(CONFIG_CPU_SUBTYPE_SH7712)
82 current_cpu_data.type = CPU_SH7712; 82 boot_cpu_data.type = CPU_SH7712;
83#endif 83#endif
84#if defined(CONFIG_CPU_SUBTYPE_SH7720) 84#if defined(CONFIG_CPU_SUBTYPE_SH7720)
85 current_cpu_data.type = CPU_SH7720; 85 boot_cpu_data.type = CPU_SH7720;
86#endif 86#endif
87#if defined(CONFIG_CPU_SUBTYPE_SH7705) 87#if defined(CONFIG_CPU_SUBTYPE_SH7705)
88 current_cpu_data.type = CPU_SH7705; 88 boot_cpu_data.type = CPU_SH7705;
89 89
90#if defined(CONFIG_SH7705_CACHE_32KB) 90#if defined(CONFIG_SH7705_CACHE_32KB)
91 current_cpu_data.dcache.way_incr = (1 << 13); 91 boot_cpu_data.dcache.way_incr = (1 << 13);
92 current_cpu_data.dcache.entry_mask = 0x1ff0; 92 boot_cpu_data.dcache.entry_mask = 0x1ff0;
93 current_cpu_data.dcache.sets = 512; 93 boot_cpu_data.dcache.sets = 512;
94 ctrl_outl(CCR_CACHE_32KB, CCR3); 94 ctrl_outl(CCR_CACHE_32KB, CCR3);
95#else 95#else
96 ctrl_outl(CCR_CACHE_16KB, CCR3); 96 ctrl_outl(CCR_CACHE_16KB, CCR3);
@@ -101,9 +101,8 @@ int __init detect_cpu_and_cache_system(void)
101 /* 101 /*
102 * SH-3 doesn't have separate caches 102 * SH-3 doesn't have separate caches
103 */ 103 */
104 current_cpu_data.dcache.flags |= SH_CACHE_COMBINED; 104 boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
105 current_cpu_data.icache = current_cpu_data.dcache; 105 boot_cpu_data.icache = boot_cpu_data.dcache;
106 106
107 return 0; 107 return 0;
108} 108}
109