diff options
| author | Magnus Damm <damm@igel.co.jp> | 2007-08-12 02:22:02 -0400 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2007-09-20 22:57:49 -0400 |
| commit | 6ef5fb2cfcedaab4a43493c8f2305a67c0ce1af6 (patch) | |
| tree | ba5b4c0a19a1d81047d49488b6fe3e3b02e824cf /arch/sh/kernel/cpu/sh3/setup-sh7710.c | |
| parent | d6aee69ca11550f3ca325ceaa020ea74e173478f (diff) | |
sh: intc - add a clear register to struct intc_prio_reg
We need a secondary register member in struct intc_prio_reg to support
dual priority registers used by ipi on x3.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh3/setup-sh7710.c')
| -rw-r--r-- | arch/sh/kernel/cpu/sh3/setup-sh7710.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c index eb55ac9dbf71..5aa77710e42b 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c | |||
| @@ -86,18 +86,18 @@ static struct intc_prio priorities[] = { | |||
| 86 | }; | 86 | }; |
| 87 | 87 | ||
| 88 | static struct intc_prio_reg prio_registers[] = { | 88 | static struct intc_prio_reg prio_registers[] = { |
| 89 | { 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, | 89 | { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, |
| 90 | { 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, | 90 | { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, |
| 91 | { 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, | 91 | { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, |
| 92 | { 0xa4000018, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, | 92 | { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, |
| 93 | { 0xa400001a, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } }, | 93 | { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } }, |
| 94 | { 0xa4080000, 16, 4, /* IPRF */ { 0, DMAC2 } }, | 94 | { 0xa4080000, 0, 16, 4, /* IPRF */ { 0, DMAC2 } }, |
| 95 | #ifdef CONFIG_CPU_SUBTYPE_SH7710 | 95 | #ifdef CONFIG_CPU_SUBTYPE_SH7710 |
| 96 | { 0xa4080000, 16, 4, /* IPRF */ { IPSEC } }, | 96 | { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC } }, |
| 97 | #endif | 97 | #endif |
| 98 | { 0xa4080002, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } }, | 98 | { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } }, |
| 99 | { 0xa4080004, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } }, | 99 | { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } }, |
| 100 | { 0xa4080006, 16, 4, /* IPRI */ { 0, 0, SIOF1 } }, | 100 | { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } }, |
| 101 | }; | 101 | }; |
| 102 | 102 | ||
| 103 | static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups, | 103 | static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups, |