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authorMagnus Damm <damm@igel.co.jp>2007-08-12 02:22:02 -0400
committerPaul Mundt <lethal@linux-sh.org>2007-09-20 22:57:49 -0400
commit6ef5fb2cfcedaab4a43493c8f2305a67c0ce1af6 (patch)
treeba5b4c0a19a1d81047d49488b6fe3e3b02e824cf /arch/sh/kernel/cpu/sh3/setup-sh770x.c
parentd6aee69ca11550f3ca325ceaa020ea74e173478f (diff)
sh: intc - add a clear register to struct intc_prio_reg
We need a secondary register member in struct intc_prio_reg to support dual priority registers used by ipi on x3. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh3/setup-sh770x.c')
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index eef505b43f0c..2980c44ffb2f 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -89,22 +89,22 @@ static struct intc_prio priorities[] = {
89}; 89};
90 90
91static struct intc_prio_reg prio_registers[] = { 91static struct intc_prio_reg prio_registers[] = {
92 { 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 92 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
93 { 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } }, 93 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
94#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 94#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
95 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 95 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
96 defined(CONFIG_CPU_SUBTYPE_SH7709) 96 defined(CONFIG_CPU_SUBTYPE_SH7709)
97 { 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 97 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
98 { 0xa4000018, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, 98 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
99 { 0xa400001a, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } }, 99 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
100#endif 100#endif
101#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 101#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
102 defined(CONFIG_CPU_SUBTYPE_SH7709) 102 defined(CONFIG_CPU_SUBTYPE_SH7709)
103 { 0xa4000018, 16, 4, /* IPRD */ { PINT07, PINT815, } }, 103 { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
104 { 0xa400001a, 16, 4, /* IPRE */ { 0, SCIF0 } }, 104 { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
105#endif 105#endif
106#if defined(CONFIG_CPU_SUBTYPE_SH7707) 106#if defined(CONFIG_CPU_SUBTYPE_SH7707)
107 { 0xa400001c, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } }, 107 { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
108#endif 108#endif
109}; 109};
110 110