Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (37 commits)
  SH: catch negative denormal_subf1() retval in denormal_add()
  sh: Fix DMAC base address for SH7709S
  sh: update smc91x platform data for se7206.
  sh: Stub in cpu_to_node() and friends for NUMA build.
  sh: intc register modify fix
  sh: no high level trigger on some sh3 cpus
  sh: clean up sh7710 and sh7720 intc tables
  sh: add interrupt ack code to sh3
  sh: unify external irq pin code for sh3
  sh-sci: avoid writing to nonexistent registers
  sh-sci: sh7722 lacks scsptr registers
  sh-sci: improve sh7722 support
  sh: reset hardware from early printk
  sh: drain and wait for early printk
  sh: use sci_out() for early printk
  sh: add memory resources to /proc/iomem
  sh: add kernel bss resource
  sh: fix sh7705 interrupt vector typo
  sh: update smc91x platform data for se7722
  sh: update smc91x platform data for MigoR
  ...

1 files changed, 71 insertions, 0 deletions

diff --git a/arch/sh/kernel/cpu/sh3/setup-sh3.c b/arch/sh/kernel/cpu/sh3/setup-sh3.c
new file mode 100644
index 000000000000..c98846857855
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/setup-sh3.c
@@ -0,0 +1,71 @@
+/*
+ * Shared SH3 Setup code
+ *
+ *  Copyright (C) 2008  Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+/* All SH3 devices are equipped with IRQ0->5 (except sh7708) */
+
+enum {
+        UNUSED = 0,
+
+        /* interrupt sources */
+        IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
+};
+
+static struct intc_vect vectors_irq0123[] __initdata = {
+        INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
+        INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
+};
+
+static struct intc_vect vectors_irq45[] __initdata = {
+        INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+        { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
+        { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
+};
+
+static struct intc_mask_reg ack_registers[] __initdata = {
+        { 0xa4000004, 0, 8, /* IRR0 */
+          { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
+};
+
+static struct intc_sense_reg sense_registers[] __initdata = {
+        { 0xa4000010, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
+};
+
+static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh3-irq0123",
+                             vectors_irq0123, NULL, NULL,
+                             prio_registers, sense_registers, ack_registers);
+
+static DECLARE_INTC_DESC_ACK(intc_desc_irq45, "sh3-irq45",
+                             vectors_irq45, NULL, NULL,
+                             prio_registers, sense_registers, ack_registers);
+
+#define INTC_ICR1               0xa4000010UL
+#define INTC_ICR1_IRQLVL        (1<<14)
+
+void __init plat_irq_setup_pins(int mode)
+{
+        if (mode == IRQ_MODE_IRQ) {
+                ctrl_outw(ctrl_inw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1);
+                register_intc_controller(&intc_desc_irq0123);
+                return;
+        }
+        BUG();
+}
+
+void __init plat_irq_setup_sh3(void)
+{
+        register_intc_controller(&intc_desc_irq45);
+}