diff options
author | Paul Mundt <lethal@linux-sh.org> | 2009-06-24 05:23:52 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2009-06-24 05:23:52 -0400 |
commit | 26c92f3728d738aaa7e4859d5581323cd68096dd (patch) | |
tree | b7cc2f49a6ffe6a6b88d19b33547a370ae314de6 /arch/sh/kernel/cpu/sh2a | |
parent | 00b9de9c249f51f09c19aa41cbbb3e3eb4eea807 (diff) |
serial: sh-sci: Move SCBRR calculation algo in to platform data.
This permits each port to select its own SCBRR calculation algorithm,
rather than having it all ifdef'ed in the header. There are presently
only 5 different variations that all parts fall under.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh2a')
-rw-r--r-- | arch/sh/kernel/cpu/sh2a/setup-mxg.c | 1 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh2a/setup-sh7201.c | 8 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh2a/setup-sh7203.c | 4 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh2a/setup-sh7206.c | 4 |
4 files changed, 17 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c index 7ec658ce14f8..b2c3bcc01190 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c +++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c | |||
@@ -212,6 +212,7 @@ static struct plat_sci_port sci_platform_data[] = { | |||
212 | .mapbase = 0xff804000, | 212 | .mapbase = 0xff804000, |
213 | .flags = UPF_BOOT_AUTOCONF, | 213 | .flags = UPF_BOOT_AUTOCONF, |
214 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 214 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
215 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
215 | .type = PORT_SCIF, | 216 | .type = PORT_SCIF, |
216 | .irqs = { 220, 220, 220, 220 }, | 217 | .irqs = { 220, 220, 220, 220 }, |
217 | }, { | 218 | }, { |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c index 2a2ac222f9c7..8d44917ce50b 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c | |||
@@ -182,48 +182,56 @@ static struct plat_sci_port sci_platform_data[] = { | |||
182 | .mapbase = 0xfffe8000, | 182 | .mapbase = 0xfffe8000, |
183 | .flags = UPF_BOOT_AUTOCONF, | 183 | .flags = UPF_BOOT_AUTOCONF, |
184 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 184 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
185 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
185 | .type = PORT_SCIF, | 186 | .type = PORT_SCIF, |
186 | .irqs = { 180, 180, 180, 180 } | 187 | .irqs = { 180, 180, 180, 180 } |
187 | }, { | 188 | }, { |
188 | .mapbase = 0xfffe8800, | 189 | .mapbase = 0xfffe8800, |
189 | .flags = UPF_BOOT_AUTOCONF, | 190 | .flags = UPF_BOOT_AUTOCONF, |
190 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 191 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
192 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
191 | .type = PORT_SCIF, | 193 | .type = PORT_SCIF, |
192 | .irqs = { 184, 184, 184, 184 } | 194 | .irqs = { 184, 184, 184, 184 } |
193 | }, { | 195 | }, { |
194 | .mapbase = 0xfffe9000, | 196 | .mapbase = 0xfffe9000, |
195 | .flags = UPF_BOOT_AUTOCONF, | 197 | .flags = UPF_BOOT_AUTOCONF, |
196 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 198 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
199 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
197 | .type = PORT_SCIF, | 200 | .type = PORT_SCIF, |
198 | .irqs = { 188, 188, 188, 188 } | 201 | .irqs = { 188, 188, 188, 188 } |
199 | }, { | 202 | }, { |
200 | .mapbase = 0xfffe9800, | 203 | .mapbase = 0xfffe9800, |
201 | .flags = UPF_BOOT_AUTOCONF, | 204 | .flags = UPF_BOOT_AUTOCONF, |
202 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 205 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
206 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
203 | .type = PORT_SCIF, | 207 | .type = PORT_SCIF, |
204 | .irqs = { 192, 192, 192, 192 } | 208 | .irqs = { 192, 192, 192, 192 } |
205 | }, { | 209 | }, { |
206 | .mapbase = 0xfffea000, | 210 | .mapbase = 0xfffea000, |
207 | .flags = UPF_BOOT_AUTOCONF, | 211 | .flags = UPF_BOOT_AUTOCONF, |
208 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 212 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
213 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
209 | .type = PORT_SCIF, | 214 | .type = PORT_SCIF, |
210 | .irqs = { 196, 196, 196, 196 } | 215 | .irqs = { 196, 196, 196, 196 } |
211 | }, { | 216 | }, { |
212 | .mapbase = 0xfffea800, | 217 | .mapbase = 0xfffea800, |
213 | .flags = UPF_BOOT_AUTOCONF, | 218 | .flags = UPF_BOOT_AUTOCONF, |
214 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 219 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
220 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
215 | .type = PORT_SCIF, | 221 | .type = PORT_SCIF, |
216 | .irqs = { 200, 200, 200, 200 } | 222 | .irqs = { 200, 200, 200, 200 } |
217 | }, { | 223 | }, { |
218 | .mapbase = 0xfffeb000, | 224 | .mapbase = 0xfffeb000, |
219 | .flags = UPF_BOOT_AUTOCONF, | 225 | .flags = UPF_BOOT_AUTOCONF, |
220 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 226 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
227 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
221 | .type = PORT_SCIF, | 228 | .type = PORT_SCIF, |
222 | .irqs = { 204, 204, 204, 204 } | 229 | .irqs = { 204, 204, 204, 204 } |
223 | }, { | 230 | }, { |
224 | .mapbase = 0xfffeb800, | 231 | .mapbase = 0xfffeb800, |
225 | .flags = UPF_BOOT_AUTOCONF, | 232 | .flags = UPF_BOOT_AUTOCONF, |
226 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 233 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
234 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
227 | .type = PORT_SCIF, | 235 | .type = PORT_SCIF, |
228 | .irqs = { 208, 208, 208, 208 } | 236 | .irqs = { 208, 208, 208, 208 } |
229 | }, { | 237 | }, { |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c index 2c9f3ababfd7..a78d2a219f3b 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c | |||
@@ -178,24 +178,28 @@ static struct plat_sci_port sci_platform_data[] = { | |||
178 | .mapbase = 0xfffe8000, | 178 | .mapbase = 0xfffe8000, |
179 | .flags = UPF_BOOT_AUTOCONF, | 179 | .flags = UPF_BOOT_AUTOCONF, |
180 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 180 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
181 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
181 | .type = PORT_SCIF, | 182 | .type = PORT_SCIF, |
182 | .irqs = { 192, 192, 192, 192 }, | 183 | .irqs = { 192, 192, 192, 192 }, |
183 | }, { | 184 | }, { |
184 | .mapbase = 0xfffe8800, | 185 | .mapbase = 0xfffe8800, |
185 | .flags = UPF_BOOT_AUTOCONF, | 186 | .flags = UPF_BOOT_AUTOCONF, |
186 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 187 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
188 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
187 | .type = PORT_SCIF, | 189 | .type = PORT_SCIF, |
188 | .irqs = { 196, 196, 196, 196 }, | 190 | .irqs = { 196, 196, 196, 196 }, |
189 | }, { | 191 | }, { |
190 | .mapbase = 0xfffe9000, | 192 | .mapbase = 0xfffe9000, |
191 | .flags = UPF_BOOT_AUTOCONF, | 193 | .flags = UPF_BOOT_AUTOCONF, |
192 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 194 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
195 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
193 | .type = PORT_SCIF, | 196 | .type = PORT_SCIF, |
194 | .irqs = { 200, 200, 200, 200 }, | 197 | .irqs = { 200, 200, 200, 200 }, |
195 | }, { | 198 | }, { |
196 | .mapbase = 0xfffe9800, | 199 | .mapbase = 0xfffe9800, |
197 | .flags = UPF_BOOT_AUTOCONF, | 200 | .flags = UPF_BOOT_AUTOCONF, |
198 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 201 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
202 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
199 | .type = PORT_SCIF, | 203 | .type = PORT_SCIF, |
200 | .irqs = { 204, 204, 204, 204 }, | 204 | .irqs = { 204, 204, 204, 204 }, |
201 | }, { | 205 | }, { |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c index 5a47987f3902..68b93ed44cc2 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c | |||
@@ -138,24 +138,28 @@ static struct plat_sci_port sci_platform_data[] = { | |||
138 | .mapbase = 0xfffe8000, | 138 | .mapbase = 0xfffe8000, |
139 | .flags = UPF_BOOT_AUTOCONF, | 139 | .flags = UPF_BOOT_AUTOCONF, |
140 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 140 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
141 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
141 | .type = PORT_SCIF, | 142 | .type = PORT_SCIF, |
142 | .irqs = { 240, 240, 240, 240 }, | 143 | .irqs = { 240, 240, 240, 240 }, |
143 | }, { | 144 | }, { |
144 | .mapbase = 0xfffe8800, | 145 | .mapbase = 0xfffe8800, |
145 | .flags = UPF_BOOT_AUTOCONF, | 146 | .flags = UPF_BOOT_AUTOCONF, |
146 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 147 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
148 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
147 | .type = PORT_SCIF, | 149 | .type = PORT_SCIF, |
148 | .irqs = { 244, 244, 244, 244 }, | 150 | .irqs = { 244, 244, 244, 244 }, |
149 | }, { | 151 | }, { |
150 | .mapbase = 0xfffe9000, | 152 | .mapbase = 0xfffe9000, |
151 | .flags = UPF_BOOT_AUTOCONF, | 153 | .flags = UPF_BOOT_AUTOCONF, |
152 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 154 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
155 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
153 | .type = PORT_SCIF, | 156 | .type = PORT_SCIF, |
154 | .irqs = { 248, 248, 248, 248 }, | 157 | .irqs = { 248, 248, 248, 248 }, |
155 | }, { | 158 | }, { |
156 | .mapbase = 0xfffe9800, | 159 | .mapbase = 0xfffe9800, |
157 | .flags = UPF_BOOT_AUTOCONF, | 160 | .flags = UPF_BOOT_AUTOCONF, |
158 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 161 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
162 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
159 | .type = PORT_SCIF, | 163 | .type = PORT_SCIF, |
160 | .irqs = { 252, 252, 252, 252 }, | 164 | .irqs = { 252, 252, 252, 252 }, |
161 | }, { | 165 | }, { |