diff options
author | Paul Mundt <lethal@linux-sh.org> | 2006-12-24 20:19:56 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2007-02-12 20:54:45 -0500 |
commit | 11c1965687b0a472add948d4240dfe65a2fcb298 (patch) | |
tree | 69a71a34591bbdc6339dbe72de36819479f96198 /arch/sh/kernel/cpu/sh2a | |
parent | aec5e0e1c179fac4bbca4007a3f0d3107275a73c (diff) |
sh: Fixup cpu_data references for the non-boot CPUs.
There are a lot of bogus cpu_data-> references that only end up working
for the boot CPU, convert these to current_cpu_data to fixup SMP.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh2a')
-rw-r--r-- | arch/sh/kernel/cpu/sh2a/probe.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c index 87c6c0542089..426f6db01fc6 100644 --- a/arch/sh/kernel/cpu/sh2a/probe.c +++ b/arch/sh/kernel/cpu/sh2a/probe.c | |||
@@ -17,14 +17,14 @@ | |||
17 | int __init detect_cpu_and_cache_system(void) | 17 | int __init detect_cpu_and_cache_system(void) |
18 | { | 18 | { |
19 | /* Just SH7206 for now .. */ | 19 | /* Just SH7206 for now .. */ |
20 | cpu_data->type = CPU_SH7206; | 20 | current_cpu_data.type = CPU_SH7206; |
21 | 21 | ||
22 | cpu_data->dcache.ways = 4; | 22 | current_cpu_data.dcache.ways = 4; |
23 | cpu_data->dcache.way_incr = (1 << 11); | 23 | current_cpu_data.dcache.way_incr = (1 << 11); |
24 | cpu_data->dcache.sets = 128; | 24 | current_cpu_data.dcache.sets = 128; |
25 | cpu_data->dcache.entry_shift = 4; | 25 | current_cpu_data.dcache.entry_shift = 4; |
26 | cpu_data->dcache.linesz = L1_CACHE_BYTES; | 26 | current_cpu_data.dcache.linesz = L1_CACHE_BYTES; |
27 | cpu_data->dcache.flags = 0; | 27 | current_cpu_data.dcache.flags = 0; |
28 | 28 | ||
29 | /* | 29 | /* |
30 | * The icache is the same as the dcache as far as this setup is | 30 | * The icache is the same as the dcache as far as this setup is |
@@ -32,7 +32,7 @@ int __init detect_cpu_and_cache_system(void) | |||
32 | * lacks the U bit that the dcache has, none of this has any bearing | 32 | * lacks the U bit that the dcache has, none of this has any bearing |
33 | * on the cache info. | 33 | * on the cache info. |
34 | */ | 34 | */ |
35 | cpu_data->icache = cpu_data->dcache; | 35 | current_cpu_data.icache = current_cpu_data.dcache; |
36 | 36 | ||
37 | return 0; | 37 | return 0; |
38 | } | 38 | } |