Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (124 commits)
  sh: allow building for both r2d boards in same binary.
  sh: fix r2d board detection
  sh: Discard .exit.text/.exit.data at runtime.
  sh: Fix up some section alignments in linker script.
  sh: Fix SH-4 DMAC CHCR masking.
  sh: Rip out left-over nommu cond syscall cruft.
  sh: Make kgdb i-cache flushing less inept.
  sh: kgdb section mismatches and tidying.
  sh: cleanup struct irqaction initializers.
  sh: early_printk tidying.
  video: pvr2fb: Add TV (RGB) support to Dreamcast PVR driver.
  sh: Conditionalize gUSA support.
  sh: Follow gUSA preempt changes in __switch_to().
  sh: Tidy up gUSA preempt handling.
  sh: __copy_user() optimizations for small copies.
  sh: clkfwk: Support multi-level clock propagation.
  sh: Fix URAM start address on SH7785.
  sh: Use boot_cpu_data for CPU probe.
  sh: Support extended mode TLB on SH-X3.
  sh: Bump MAX_ACTIVE_REGIONS for SH7785.
  ...

1 files changed, 9 insertions, 10 deletions

diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index abbf17427e52..5916d9096b99 100644
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -10,26 +10,25 @@
  * for more details.
  */
 #include <linux/init.h>
-#include <linux/smp.h>
 #include <asm/processor.h>
 #include <asm/cache.h>
 
 int __init detect_cpu_and_cache_system(void)
 {
 #if defined(CONFIG_CPU_SUBTYPE_SH7619)
-        current_cpu_data.type                   = CPU_SH7619;
-        current_cpu_data.dcache.ways            = 4;
-        current_cpu_data.dcache.way_incr        = (1<<12);
-        current_cpu_data.dcache.sets            = 256;
-        current_cpu_data.dcache.entry_shift     = 4;
-        current_cpu_data.dcache.linesz          = L1_CACHE_BYTES;
-        current_cpu_data.dcache.flags           = 0;
+        boot_cpu_data.type                      = CPU_SH7619;
+        boot_cpu_data.dcache.ways               = 4;
+        boot_cpu_data.dcache.way_incr   = (1<<12);
+        boot_cpu_data.dcache.sets               = 256;
+        boot_cpu_data.dcache.entry_shift        = 4;
+        boot_cpu_data.dcache.linesz             = L1_CACHE_BYTES;
+        boot_cpu_data.dcache.flags              = 0;
 #endif
         /*
          * SH-2 doesn't have separate caches
          */
-        current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
-        current_cpu_data.icache = current_cpu_data.dcache;
+        boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
+        boot_cpu_data.icache = boot_cpu_data.dcache;
 
         return 0;
 }