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authorPaul Mundt <lethal@linux-sh.org>2006-01-17 01:14:14 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-01-17 02:15:28 -0500
commitbf3a00f88c926635932c91afd90b4a0907dfbe78 (patch)
tree179a56c061461a0f3d25cd0171ba8ce90e5e7ed5 /arch/sh/kernel/cpu/irq
parent9d44190eae97ad4c9ce30f1084e1b0dabd646df5 (diff)
[PATCH] sh: IRQ handler updates
This moves the various IRQ controller drivers into a new subdirectory, and also extends the INTC2 IRQ handler to also deal with SH7760 and SH7780 interrupts, rather than just ST-40. The old CONFIG_SH_GENERIC has also been removed from the IRQ definitions, as new ports are expected to be based off of CONFIG_SH_UNKNOWN. Since there are plenty of incompatible machvecs, CONFIG_SH_GENERIC doesn't make sense anymore. Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/sh/kernel/cpu/irq')
-rw-r--r--arch/sh/kernel/cpu/irq/Makefile7
-rw-r--r--arch/sh/kernel/cpu/irq/imask.c110
-rw-r--r--arch/sh/kernel/cpu/irq/intc2.c284
-rw-r--r--arch/sh/kernel/cpu/irq/ipr.c206
-rw-r--r--arch/sh/kernel/cpu/irq/pint.c169
5 files changed, 776 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/irq/Makefile b/arch/sh/kernel/cpu/irq/Makefile
new file mode 100644
index 000000000000..e3cccea15e1d
--- /dev/null
+++ b/arch/sh/kernel/cpu/irq/Makefile
@@ -0,0 +1,7 @@
1#
2# Makefile for the Linux/SuperH CPU-specifc IRQ handlers.
3#
4obj-y += ipr.o imask.o
5
6obj-$(CONFIG_CPU_HAS_PINT_IRQ) += pint.o
7obj-$(CONFIG_CPU_HAS_INTC2_IRQ) += intc2.o
diff --git a/arch/sh/kernel/cpu/irq/imask.c b/arch/sh/kernel/cpu/irq/imask.c
new file mode 100644
index 000000000000..baed9a550d39
--- /dev/null
+++ b/arch/sh/kernel/cpu/irq/imask.c
@@ -0,0 +1,110 @@
1/*
2 * arch/sh/kernel/cpu/irq/imask.c
3 *
4 * Copyright (C) 1999, 2000 Niibe Yutaka
5 *
6 * Simple interrupt handling using IMASK of SR register.
7 *
8 */
9/* NOTE: Will not work on level 15 */
10#include <linux/ptrace.h>
11#include <linux/errno.h>
12#include <linux/kernel_stat.h>
13#include <linux/signal.h>
14#include <linux/sched.h>
15#include <linux/interrupt.h>
16#include <linux/init.h>
17#include <linux/bitops.h>
18#include <linux/spinlock.h>
19#include <linux/cache.h>
20#include <linux/irq.h>
21#include <asm/system.h>
22#include <asm/irq.h>
23
24/* Bitmap of IRQ masked */
25static unsigned long imask_mask = 0x7fff;
26static int interrupt_priority = 0;
27
28static void enable_imask_irq(unsigned int irq);
29static void disable_imask_irq(unsigned int irq);
30static void shutdown_imask_irq(unsigned int irq);
31static void mask_and_ack_imask(unsigned int);
32static void end_imask_irq(unsigned int irq);
33
34#define IMASK_PRIORITY 15
35
36static unsigned int startup_imask_irq(unsigned int irq)
37{
38 /* Nothing to do */
39 return 0; /* never anything pending */
40}
41
42static struct hw_interrupt_type imask_irq_type = {
43 .typename = "SR.IMASK",
44 .startup = startup_imask_irq,
45 .shutdown = shutdown_imask_irq,
46 .enable = enable_imask_irq,
47 .disable = disable_imask_irq,
48 .ack = mask_and_ack_imask,
49 .end = end_imask_irq
50};
51
52void static inline set_interrupt_registers(int ip)
53{
54 unsigned long __dummy;
55
56 asm volatile("ldc %2, r6_bank\n\t"
57 "stc sr, %0\n\t"
58 "and #0xf0, %0\n\t"
59 "shlr2 %0\n\t"
60 "cmp/eq #0x3c, %0\n\t"
61 "bt/s 1f ! CLI-ed\n\t"
62 " stc sr, %0\n\t"
63 "and %1, %0\n\t"
64 "or %2, %0\n\t"
65 "ldc %0, sr\n"
66 "1:"
67 : "=&z" (__dummy)
68 : "r" (~0xf0), "r" (ip << 4)
69 : "t");
70}
71
72static void disable_imask_irq(unsigned int irq)
73{
74 clear_bit(irq, &imask_mask);
75 if (interrupt_priority < IMASK_PRIORITY - irq)
76 interrupt_priority = IMASK_PRIORITY - irq;
77
78 set_interrupt_registers(interrupt_priority);
79}
80
81static void enable_imask_irq(unsigned int irq)
82{
83 set_bit(irq, &imask_mask);
84 interrupt_priority = IMASK_PRIORITY - ffz(imask_mask);
85
86 set_interrupt_registers(interrupt_priority);
87}
88
89static void mask_and_ack_imask(unsigned int irq)
90{
91 disable_imask_irq(irq);
92}
93
94static void end_imask_irq(unsigned int irq)
95{
96 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
97 enable_imask_irq(irq);
98}
99
100static void shutdown_imask_irq(unsigned int irq)
101{
102 /* Nothing to do */
103}
104
105void make_imask_irq(unsigned int irq)
106{
107 disable_irq_nosync(irq);
108 irq_desc[irq].handler = &imask_irq_type;
109 enable_irq(irq);
110}
diff --git a/arch/sh/kernel/cpu/irq/intc2.c b/arch/sh/kernel/cpu/irq/intc2.c
new file mode 100644
index 000000000000..06e8afab32e4
--- /dev/null
+++ b/arch/sh/kernel/cpu/irq/intc2.c
@@ -0,0 +1,284 @@
1/*
2 * Interrupt handling for INTC2-based IRQ.
3 *
4 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
5 * Copyright (C) 2005, 2006 Paul Mundt (lethal@linux-sh.org)
6 *
7 * May be copied or modified under the terms of the GNU General Public
8 * License. See linux/COPYING for more information.
9 *
10 * These are the "new Hitachi style" interrupts, as present on the
11 * Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/irq.h>
17#include <asm/system.h>
18#include <asm/io.h>
19#include <asm/machvec.h>
20
21struct intc2_data {
22 unsigned char msk_offset;
23 unsigned char msk_shift;
24
25 int (*clear_irq) (int);
26};
27
28static struct intc2_data intc2_data[NR_INTC2_IRQS];
29
30static void enable_intc2_irq(unsigned int irq);
31static void disable_intc2_irq(unsigned int irq);
32
33/* shutdown is same as "disable" */
34#define shutdown_intc2_irq disable_intc2_irq
35
36static void mask_and_ack_intc2(unsigned int);
37static void end_intc2_irq(unsigned int irq);
38
39static unsigned int startup_intc2_irq(unsigned int irq)
40{
41 enable_intc2_irq(irq);
42 return 0; /* never anything pending */
43}
44
45static struct hw_interrupt_type intc2_irq_type = {
46 .typename = "INTC2-IRQ",
47 .startup = startup_intc2_irq,
48 .shutdown = shutdown_intc2_irq,
49 .enable = enable_intc2_irq,
50 .disable = disable_intc2_irq,
51 .ack = mask_and_ack_intc2,
52 .end = end_intc2_irq
53};
54
55static void disable_intc2_irq(unsigned int irq)
56{
57 int irq_offset = irq - INTC2_FIRST_IRQ;
58 int msk_shift, msk_offset;
59
60 /* Sanity check */
61 if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))
62 return;
63
64 msk_shift = intc2_data[irq_offset].msk_shift;
65 msk_offset = intc2_data[irq_offset].msk_offset;
66
67 ctrl_outl(1 << msk_shift,
68 INTC2_BASE + INTC2_INTMSK_OFFSET + msk_offset);
69}
70
71static void enable_intc2_irq(unsigned int irq)
72{
73 int irq_offset = irq - INTC2_FIRST_IRQ;
74 int msk_shift, msk_offset;
75
76 /* Sanity check */
77 if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))
78 return;
79
80 msk_shift = intc2_data[irq_offset].msk_shift;
81 msk_offset = intc2_data[irq_offset].msk_offset;
82
83 ctrl_outl(1 << msk_shift,
84 INTC2_BASE + INTC2_INTMSKCLR_OFFSET + msk_offset);
85}
86
87static void mask_and_ack_intc2(unsigned int irq)
88{
89 disable_intc2_irq(irq);
90}
91
92static void end_intc2_irq(unsigned int irq)
93{
94 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
95 enable_intc2_irq(irq);
96
97 if (unlikely(intc2_data[irq - INTC2_FIRST_IRQ].clear_irq))
98 intc2_data[irq - INTC2_FIRST_IRQ].clear_irq(irq);
99}
100
101/*
102 * Setup an INTC2 style interrupt.
103 * NOTE: Unlike IPR interrupts, parameters are not shifted by this code,
104 * allowing the use of the numbers straight out of the datasheet.
105 * For example:
106 * PIO1 which is INTPRI00[19,16] and INTMSK00[13]
107 * would be: ^ ^ ^ ^
108 * | | | |
109 * make_intc2_irq(84, 0, 16, 0, 13);
110 */
111void make_intc2_irq(unsigned int irq,
112 unsigned int ipr_offset, unsigned int ipr_shift,
113 unsigned int msk_offset, unsigned int msk_shift,
114 unsigned int priority)
115{
116 int irq_offset = irq - INTC2_FIRST_IRQ;
117 unsigned int flags;
118 unsigned long ipr;
119
120 if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))
121 return;
122
123 disable_irq_nosync(irq);
124
125 /* Fill the data we need */
126 intc2_data[irq_offset].msk_offset = msk_offset;
127 intc2_data[irq_offset].msk_shift = msk_shift;
128 intc2_data[irq_offset].clear_irq = NULL;
129
130 /* Set the priority level */
131 local_irq_save(flags);
132
133 ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET + ipr_offset);
134 ipr &= ~(0xf << ipr_shift);
135 ipr |= priority << ipr_shift;
136 ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET + ipr_offset);
137
138 local_irq_restore(flags);
139
140 irq_desc[irq].handler = &intc2_irq_type;
141
142 disable_intc2_irq(irq);
143}
144
145static struct intc2_init {
146 unsigned short irq;
147 unsigned char ipr_offset, ipr_shift;
148 unsigned char msk_offset, msk_shift;
149 unsigned char priority;
150} intc2_init_data[] __initdata = {
151#if defined(CONFIG_CPU_SUBTYPE_ST40)
152 {64, 0, 0, 0, 0, 13}, /* PCI serr */
153 {65, 0, 4, 0, 1, 13}, /* PCI err */
154 {66, 0, 4, 0, 2, 13}, /* PCI ad */
155 {67, 0, 4, 0, 3, 13}, /* PCI pwd down */
156 {72, 0, 8, 0, 5, 13}, /* DMAC INT0 */
157 {73, 0, 8, 0, 6, 13}, /* DMAC INT1 */
158 {74, 0, 8, 0, 7, 13}, /* DMAC INT2 */
159 {75, 0, 8, 0, 8, 13}, /* DMAC INT3 */
160 {76, 0, 8, 0, 9, 13}, /* DMAC INT4 */
161 {78, 0, 8, 0, 11, 13}, /* DMAC ERR */
162 {80, 0, 12, 0, 12, 13}, /* PIO0 */
163 {84, 0, 16, 0, 13, 13}, /* PIO1 */
164 {88, 0, 20, 0, 14, 13}, /* PIO2 */
165 {112, 4, 0, 4, 0, 13}, /* Mailbox */
166 #ifdef CONFIG_CPU_SUBTYPE_ST40GX1
167 {116, 4, 4, 4, 4, 13}, /* SSC0 */
168 {120, 4, 8, 4, 8, 13}, /* IR Blaster */
169 {124, 4, 12, 4, 12, 13}, /* USB host */
170 {128, 4, 16, 4, 16, 13}, /* Video processor BLITTER */
171 {132, 4, 20, 4, 20, 13}, /* UART0 */
172 {134, 4, 20, 4, 22, 13}, /* UART2 */
173 {136, 4, 24, 4, 24, 13}, /* IO_PIO0 */
174 {140, 4, 28, 4, 28, 13}, /* EMPI */
175 {144, 8, 0, 8, 0, 13}, /* MAFE */
176 {148, 8, 4, 8, 4, 13}, /* PWM */
177 {152, 8, 8, 8, 8, 13}, /* SSC1 */
178 {156, 8, 12, 8, 12, 13}, /* IO_PIO1 */
179 {160, 8, 16, 8, 16, 13}, /* USB target */
180 {164, 8, 20, 8, 20, 13}, /* UART1 */
181 {168, 8, 24, 8, 24, 13}, /* Teletext */
182 {172, 8, 28, 8, 28, 13}, /* VideoSync VTG */
183 {173, 8, 28, 8, 29, 13}, /* VideoSync DVP0 */
184 {174, 8, 28, 8, 30, 13}, /* VideoSync DVP1 */
185#endif
186#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
187/*
188 * SH7760 INTC2-Style interrupts, vectors IRQ48-111 INTEVT 0x800-0xFE0
189 */
190 /* INTPRIO0 | INTMSK0 */
191 {48, 0, 28, 0, 31, 3}, /* IRQ 4 */
192 {49, 0, 24, 0, 30, 3}, /* IRQ 3 */
193 {50, 0, 20, 0, 29, 3}, /* IRQ 2 */
194 {51, 0, 16, 0, 28, 3}, /* IRQ 1 */
195 /* 52-55 (INTEVT 0x880-0x8E0) unused/reserved */
196 /* INTPRIO4 | INTMSK0 */
197 {56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */
198 {57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */
199 {58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */
200 {59, 4, 16, 0, 22, 3}, /* I2S_CHAN1 */
201 {60, 4, 12, 0, 21, 3}, /* AC97_CHAN0 */
202 {61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */
203 {62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */
204 {63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */
205 /* INTPRIO8 | INTMSK0 */
206 {52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */
207 {53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */
208 {54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */
209 {55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */
210 {64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */
211 {65, 8, 24, 0, 16, 3}, /* LCDC */
212 /* 66, 67 unused */
213 {68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */
214 {69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */
215 {70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */
216 /* 71 unused */
217 {72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */
218 {73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */
219 {74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */
220 {75, 8, 12, 0, 4, 3}, /* SCIF1_TXI_IRQ */
221 {76, 8, 8, 0, 3, 3}, /* SCIF2_ERI_IRQ */
222 {77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */
223 {78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */
224 {79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */
225 /* | INTMSK4 */
226 {80, 8, 4, 4, 23, 3}, /* SIM_ERI */
227 {81, 8, 4, 4, 22, 3}, /* SIM_RXI */
228 {82, 8, 4, 4, 21, 3}, /* SIM_TXI */
229 {83, 8, 4, 4, 20, 3}, /* SIM_TEI */
230 {84, 8, 0, 4, 19, 3}, /* HSPII */
231 /* INTPRIOC | INTMSK4 */
232 /* 85-87 unused/reserved */
233 {88, 12, 20, 4, 18, 3}, /* MMCI0 */
234 {89, 12, 20, 4, 17, 3}, /* MMCI1 */
235 {90, 12, 20, 4, 16, 3}, /* MMCI2 */
236 {91, 12, 20, 4, 15, 3}, /* MMCI3 */
237 {92, 12, 12, 4, 6, 3}, /* MFI (unsure, bug? in my 7760 manual*/
238 /* 93-107 reserved/undocumented */
239 {108,12, 4, 4, 1, 3}, /* ADC */
240 {109,12, 0, 4, 0, 3}, /* CMTI */
241 /* 110-111 reserved/unused */
242#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
243 { TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2},
244#ifdef CONFIG_SH_RTC
245 { RTC_IRQ, 4, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
246#endif
247 { SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
248 { SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
249 { SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
250 { SCIF0_TXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
251
252 { SCIF1_ERI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
253 { SCIF1_RXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
254 { SCIF1_BRI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
255 { SCIF1_TXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
256
257 { PCIC0_IRQ, 0x10, 8, 0, INTC_PCIC0_MSK, PCIC0_PRIORITY },
258 { PCIC1_IRQ, 0x10, 0, 0, INTC_PCIC1_MSK, PCIC1_PRIORITY },
259 { PCIC2_IRQ, 0x14, 24, 0, INTC_PCIC2_MSK, PCIC2_PRIORITY },
260 { PCIC3_IRQ, 0x14, 16, 0, INTC_PCIC3_MSK, PCIC3_PRIORITY },
261 { PCIC4_IRQ, 0x14, 8, 0, INTC_PCIC4_MSK, PCIC4_PRIORITY },
262#endif
263};
264
265void __init init_IRQ_intc2(void)
266{
267 int i;
268
269 for (i = 0; i < ARRAY_SIZE(intc2_init_data); i++) {
270 struct intc2_init *p = intc2_init_data + i;
271 make_intc2_irq(p->irq, p->ipr_offset, p->ipr_shift,
272 p-> msk_offset, p->msk_shift, p->priority);
273 }
274}
275
276/* Adds a termination callback to the interrupt */
277void intc2_add_clear_irq(int irq, int (*fn)(int))
278{
279 if (unlikely(irq < INTC2_FIRST_IRQ))
280 return;
281
282 intc2_data[irq - INTC2_FIRST_IRQ].clear_irq = fn;
283}
284
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
new file mode 100644
index 000000000000..fdbd718ae5c6
--- /dev/null
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -0,0 +1,206 @@
1/*
2 * arch/sh/kernel/cpu/irq/ipr.c
3 *
4 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
5 * Copyright (C) 2000 Kazumoto Kojima
6 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
7 *
8 * Interrupt handling for IPR-based IRQ.
9 *
10 * Supported system:
11 * On-chip supporting modules (TMU, RTC, etc.).
12 * On-chip supporting modules for SH7709/SH7709A/SH7729/SH7300.
13 * Hitachi SolutionEngine external I/O:
14 * MS7709SE01, MS7709ASE01, and MS7750SE01
15 *
16 */
17
18#include <linux/config.h>
19#include <linux/init.h>
20#include <linux/irq.h>
21#include <linux/module.h>
22
23#include <asm/system.h>
24#include <asm/io.h>
25#include <asm/machvec.h>
26
27struct ipr_data {
28 unsigned int addr; /* Address of Interrupt Priority Register */
29 int shift; /* Shifts of the 16-bit data */
30 int priority; /* The priority */
31};
32static struct ipr_data ipr_data[NR_IRQS];
33
34static void enable_ipr_irq(unsigned int irq);
35static void disable_ipr_irq(unsigned int irq);
36
37/* shutdown is same as "disable" */
38#define shutdown_ipr_irq disable_ipr_irq
39
40static void mask_and_ack_ipr(unsigned int);
41static void end_ipr_irq(unsigned int irq);
42
43static unsigned int startup_ipr_irq(unsigned int irq)
44{
45 enable_ipr_irq(irq);
46 return 0; /* never anything pending */
47}
48
49static struct hw_interrupt_type ipr_irq_type = {
50 .typename = "IPR-IRQ",
51 .startup = startup_ipr_irq,
52 .shutdown = shutdown_ipr_irq,
53 .enable = enable_ipr_irq,
54 .disable = disable_ipr_irq,
55 .ack = mask_and_ack_ipr,
56 .end = end_ipr_irq
57};
58
59static void disable_ipr_irq(unsigned int irq)
60{
61 unsigned long val, flags;
62 unsigned int addr = ipr_data[irq].addr;
63 unsigned short mask = 0xffff ^ (0x0f << ipr_data[irq].shift);
64
65 /* Set the priority in IPR to 0 */
66 local_irq_save(flags);
67 val = ctrl_inw(addr);
68 val &= mask;
69 ctrl_outw(val, addr);
70 local_irq_restore(flags);
71}
72
73static void enable_ipr_irq(unsigned int irq)
74{
75 unsigned long val, flags;
76 unsigned int addr = ipr_data[irq].addr;
77 int priority = ipr_data[irq].priority;
78 unsigned short value = (priority << ipr_data[irq].shift);
79
80 /* Set priority in IPR back to original value */
81 local_irq_save(flags);
82 val = ctrl_inw(addr);
83 val |= value;
84 ctrl_outw(val, addr);
85 local_irq_restore(flags);
86}
87
88static void mask_and_ack_ipr(unsigned int irq)
89{
90 disable_ipr_irq(irq);
91
92#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
93 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
94 /* This is needed when we use edge triggered setting */
95 /* XXX: Is it really needed? */
96 if (IRQ0_IRQ <= irq && irq <= IRQ5_IRQ) {
97 /* Clear external interrupt request */
98 int a = ctrl_inb(INTC_IRR0);
99 a &= ~(1 << (irq - IRQ0_IRQ));
100 ctrl_outb(a, INTC_IRR0);
101 }
102#endif
103}
104
105static void end_ipr_irq(unsigned int irq)
106{
107 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
108 enable_ipr_irq(irq);
109}
110
111void make_ipr_irq(unsigned int irq, unsigned int addr, int pos,
112 int priority, int maskpos)
113{
114 disable_irq_nosync(irq);
115 ipr_data[irq].addr = addr;
116 ipr_data[irq].shift = pos*4; /* POSition (0-3) x 4 means shift */
117 ipr_data[irq].priority = priority;
118
119 irq_desc[irq].handler = &ipr_irq_type;
120 disable_ipr_irq(irq);
121}
122
123void __init init_IRQ(void)
124{
125#ifndef CONFIG_CPU_SUBTYPE_SH7780
126 make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY, 0);
127 make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY, 0);
128#if defined(CONFIG_SH_RTC)
129 make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY, 0);
130#endif
131
132#ifdef SCI_ERI_IRQ
133 make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY, 0);
134 make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY, 0);
135 make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY, 0);
136#endif
137
138#ifdef SCIF1_ERI_IRQ
139 make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0);
140 make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0);
141 make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0);
142 make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0);
143#endif
144
145#if defined(CONFIG_CPU_SUBTYPE_SH7300)
146 make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY, 0);
147 make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY, 0);
148 make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY, 0);
149 make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY, 0);
150#endif
151
152#ifdef SCIF_ERI_IRQ
153 make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0);
154 make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0);
155 make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0);
156 make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0);
157#endif
158
159#ifdef IRDA_ERI_IRQ
160 make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0);
161 make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0);
162 make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0);
163 make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0);
164#endif
165
166#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
167 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
168 /*
169 * Initialize the Interrupt Controller (INTC)
170 * registers to their power on values
171 */
172
173 /*
174 * Enable external irq (INTC IRQ mode).
175 * You should set corresponding bits of PFC to "00"
176 * to enable these interrupts.
177 */
178 make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY, 0);
179 make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY, 0);
180 make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY, 0);
181 make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY, 0);
182 make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY, 0);
183 make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY, 0);
184#endif
185#endif
186
187#ifdef CONFIG_CPU_HAS_PINT_IRQ
188 init_IRQ_pint();
189#endif
190
191#ifdef CONFIG_CPU_HAS_INTC2_IRQ
192 init_IRQ_intc2();
193#endif
194 /* Perform the machine specific initialisation */
195 if (sh_mv.mv_init_irq != NULL)
196 sh_mv.mv_init_irq();
197}
198
199#if !defined(CONFIG_CPU_HAS_PINT_IRQ)
200int ipr_irq_demux(int irq)
201{
202 return irq;
203}
204#endif
205
206EXPORT_SYMBOL(make_ipr_irq);
diff --git a/arch/sh/kernel/cpu/irq/pint.c b/arch/sh/kernel/cpu/irq/pint.c
new file mode 100644
index 000000000000..95d6024fe1ae
--- /dev/null
+++ b/arch/sh/kernel/cpu/irq/pint.c
@@ -0,0 +1,169 @@
1/*
2 * arch/sh/kernel/cpu/irq/pint.c - Interrupt handling for PINT-based IRQs.
3 *
4 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
5 * Copyright (C) 2000 Kazumoto Kojima
6 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/config.h>
14#include <linux/init.h>
15#include <linux/irq.h>
16#include <linux/module.h>
17
18#include <asm/system.h>
19#include <asm/io.h>
20#include <asm/machvec.h>
21
22static unsigned char pint_map[256];
23static unsigned long portcr_mask;
24
25static void enable_pint_irq(unsigned int irq);
26static void disable_pint_irq(unsigned int irq);
27
28/* shutdown is same as "disable" */
29#define shutdown_pint_irq disable_pint_irq
30
31static void mask_and_ack_pint(unsigned int);
32static void end_pint_irq(unsigned int irq);
33
34static unsigned int startup_pint_irq(unsigned int irq)
35{
36 enable_pint_irq(irq);
37 return 0; /* never anything pending */
38}
39
40static struct hw_interrupt_type pint_irq_type = {
41 .typename = "PINT-IRQ",
42 .startup = startup_pint_irq,
43 .shutdown = shutdown_pint_irq,
44 .enable = enable_pint_irq,
45 .disable = disable_pint_irq,
46 .ack = mask_and_ack_pint,
47 .end = end_pint_irq
48};
49
50static void disable_pint_irq(unsigned int irq)
51{
52 unsigned long val, flags;
53
54 local_irq_save(flags);
55 val = ctrl_inw(INTC_INTER);
56 val &= ~(1 << (irq - PINT_IRQ_BASE));
57 ctrl_outw(val, INTC_INTER); /* disable PINTn */
58 portcr_mask &= ~(3 << (irq - PINT_IRQ_BASE)*2);
59 local_irq_restore(flags);
60}
61
62static void enable_pint_irq(unsigned int irq)
63{
64 unsigned long val, flags;
65
66 local_irq_save(flags);
67 val = ctrl_inw(INTC_INTER);
68 val |= 1 << (irq - PINT_IRQ_BASE);
69 ctrl_outw(val, INTC_INTER); /* enable PINTn */
70 portcr_mask |= 3 << (irq - PINT_IRQ_BASE)*2;
71 local_irq_restore(flags);
72}
73
74static void mask_and_ack_pint(unsigned int irq)
75{
76 disable_pint_irq(irq);
77}
78
79static void end_pint_irq(unsigned int irq)
80{
81 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
82 enable_pint_irq(irq);
83}
84
85void make_pint_irq(unsigned int irq)
86{
87 disable_irq_nosync(irq);
88 irq_desc[irq].handler = &pint_irq_type;
89 disable_pint_irq(irq);
90}
91
92void __init init_IRQ_pint(void)
93{
94 int i;
95
96 make_ipr_irq(PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY);
97 make_ipr_irq(PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY);
98
99 enable_irq(PINT0_IRQ);
100 enable_irq(PINT8_IRQ);
101
102 for(i = 0; i < 16; i++)
103 make_pint_irq(PINT_IRQ_BASE + i);
104
105 for(i = 0; i < 256; i++) {
106 if (i & 1)
107 pint_map[i] = 0;
108 else if (i & 2)
109 pint_map[i] = 1;
110 else if (i & 4)
111 pint_map[i] = 2;
112 else if (i & 8)
113 pint_map[i] = 3;
114 else if (i & 0x10)
115 pint_map[i] = 4;
116 else if (i & 0x20)
117 pint_map[i] = 5;
118 else if (i & 0x40)
119 pint_map[i] = 6;
120 else if (i & 0x80)
121 pint_map[i] = 7;
122 }
123}
124
125int ipr_irq_demux(int irq)
126{
127 unsigned long creg, dreg, d, sav;
128
129 if (irq == PINT0_IRQ) {
130#if defined(CONFIG_CPU_SUBTYPE_SH7707)
131 creg = PORT_PACR;
132 dreg = PORT_PADR;
133#else
134 creg = PORT_PCCR;
135 dreg = PORT_PCDR;
136#endif
137 sav = ctrl_inw(creg);
138 ctrl_outw(sav | portcr_mask, creg);
139 d = (~ctrl_inb(dreg) ^ ctrl_inw(INTC_ICR2)) &
140 ctrl_inw(INTC_INTER) & 0xff;
141 ctrl_outw(sav, creg);
142
143 if (d == 0)
144 return irq;
145
146 return PINT_IRQ_BASE + pint_map[d];
147 } else if (irq == PINT8_IRQ) {
148#if defined(CONFIG_CPU_SUBTYPE_SH7707)
149 creg = PORT_PBCR;
150 dreg = PORT_PBDR;
151#else
152 creg = PORT_PFCR;
153 dreg = PORT_PFDR;
154#endif
155 sav = ctrl_inw(creg);
156 ctrl_outw(sav | (portcr_mask >> 16), creg);
157 d = (~ctrl_inb(dreg) ^ (ctrl_inw(INTC_ICR2) >> 8)) &
158 (ctrl_inw(INTC_INTER) >> 8) & 0xff;
159 ctrl_outw(sav, creg);
160
161 if (d == 0)
162 return irq;
163
164 return PINT_IRQ_BASE + 8 + pint_map[d];
165 }
166
167 return irq;
168}
169
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