diff options
author | Magnus Damm <damm@igel.co.jp> | 2007-06-14 21:41:54 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2007-06-14 21:41:54 -0400 |
commit | d619500aed2f9b841b2310bc94f8056ae9ca2a73 (patch) | |
tree | 42ca07266afbf0406d419e57dde404ad89cd316d /arch/sh/kernel/cpu/irq | |
parent | d3efbdd6c5e8c823b732df26a355ec931ccab374 (diff) |
sh: rework intc2 code
The shared intc2 code currently contains cpu-specific #ifdefs.
This is a tad unclean and it prevents us from using the shared code
to drive board-specific irqs on the se7780 board.
This patch reworks the intc2 code by moving the base addresses of
the intc2 registers into struct intc2_desc. This new structure also
contains the name of the controller in struct irq_chip. The idea
behind putting struct irq_chip in there is that we can use offsetof()
to locate the base addresses in the irq_chip callbacks.
One logic change has been made - the original shared intc2 code
enabled the interrupts by default but with this patch they are all
disabled by default.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/irq')
-rw-r--r-- | arch/sh/kernel/cpu/irq/intc2.c | 58 |
1 files changed, 27 insertions, 31 deletions
diff --git a/arch/sh/kernel/cpu/irq/intc2.c b/arch/sh/kernel/cpu/irq/intc2.c index d8e22f4ff0f0..dae02d3152e7 100644 --- a/arch/sh/kernel/cpu/irq/intc2.c +++ b/arch/sh/kernel/cpu/irq/intc2.c | |||
@@ -14,36 +14,26 @@ | |||
14 | #include <linux/interrupt.h> | 14 | #include <linux/interrupt.h> |
15 | #include <linux/io.h> | 15 | #include <linux/io.h> |
16 | 16 | ||
17 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) | 17 | static inline struct intc2_desc *get_intc2_desc(unsigned int irq) |
18 | #define INTC2_BASE 0xfe080000 | 18 | { |
19 | #define INTC2_INTMSK (INTC2_BASE + 0x40) | 19 | struct irq_chip *chip = get_irq_chip(irq); |
20 | #define INTC2_INTMSKCLR (INTC2_BASE + 0x60) | 20 | return (void *)((char *)chip - offsetof(struct intc2_desc, chip)); |
21 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | 21 | } |
22 | defined(CONFIG_CPU_SUBTYPE_SH7785) | ||
23 | #define INTC2_BASE 0xffd40000 | ||
24 | #define INTC2_INTMSK (INTC2_BASE + 0x38) | ||
25 | #define INTC2_INTMSKCLR (INTC2_BASE + 0x3c) | ||
26 | #endif | ||
27 | 22 | ||
28 | static void disable_intc2_irq(unsigned int irq) | 23 | static void disable_intc2_irq(unsigned int irq) |
29 | { | 24 | { |
30 | struct intc2_data *p = get_irq_chip_data(irq); | 25 | struct intc2_data *p = get_irq_chip_data(irq); |
31 | ctrl_outl(1 << p->msk_shift, INTC2_INTMSK + p->msk_offset); | 26 | struct intc2_desc *d = get_intc2_desc(irq); |
27 | ctrl_outl(1 << p->msk_shift, d->msk_base + p->msk_offset); | ||
32 | } | 28 | } |
33 | 29 | ||
34 | static void enable_intc2_irq(unsigned int irq) | 30 | static void enable_intc2_irq(unsigned int irq) |
35 | { | 31 | { |
36 | struct intc2_data *p = get_irq_chip_data(irq); | 32 | struct intc2_data *p = get_irq_chip_data(irq); |
37 | ctrl_outl(1 << p->msk_shift, INTC2_INTMSKCLR + p->msk_offset); | 33 | struct intc2_desc *d = get_intc2_desc(irq); |
34 | ctrl_outl(1 << p->msk_shift, d->mskclr_base + p->msk_offset); | ||
38 | } | 35 | } |
39 | 36 | ||
40 | static struct irq_chip intc2_irq_chip = { | ||
41 | .name = "INTC2", | ||
42 | .mask = disable_intc2_irq, | ||
43 | .unmask = enable_intc2_irq, | ||
44 | .mask_ack = disable_intc2_irq, | ||
45 | }; | ||
46 | |||
47 | /* | 37 | /* |
48 | * Setup an INTC2 style interrupt. | 38 | * Setup an INTC2 style interrupt. |
49 | * NOTE: Unlike IPR interrupts, parameters are not shifted by this code, | 39 | * NOTE: Unlike IPR interrupts, parameters are not shifted by this code, |
@@ -56,30 +46,36 @@ static struct irq_chip intc2_irq_chip = { | |||
56 | * | 46 | * |
57 | * in the intc2_data table. | 47 | * in the intc2_data table. |
58 | */ | 48 | */ |
59 | void make_intc2_irq(struct intc2_data *table, unsigned int nr_irqs) | 49 | void register_intc2_controller(struct intc2_desc *desc) |
60 | { | 50 | { |
61 | int i; | 51 | int i; |
62 | 52 | ||
63 | for (i = 0; i < nr_irqs; i++) { | 53 | desc->chip.mask = disable_intc2_irq; |
54 | desc->chip.unmask = enable_intc2_irq; | ||
55 | desc->chip.mask_ack = disable_intc2_irq; | ||
56 | |||
57 | for (i = 0; i < desc->nr_irqs; i++) { | ||
64 | unsigned long ipr, flags; | 58 | unsigned long ipr, flags; |
65 | struct intc2_data *p = table + i; | 59 | struct intc2_data *p = desc->intc2_data + i; |
66 | 60 | ||
67 | disable_irq_nosync(p->irq); | 61 | disable_irq_nosync(p->irq); |
68 | 62 | ||
69 | /* Set the priority level */ | 63 | if (desc->prio_base) { |
70 | local_irq_save(flags); | 64 | /* Set the priority level */ |
65 | local_irq_save(flags); | ||
71 | 66 | ||
72 | ipr = ctrl_inl(INTC2_BASE + p->ipr_offset); | 67 | ipr = ctrl_inl(desc->prio_base + p->ipr_offset); |
73 | ipr &= ~(0xf << p->ipr_shift); | 68 | ipr &= ~(0xf << p->ipr_shift); |
74 | ipr |= p->priority << p->ipr_shift; | 69 | ipr |= p->priority << p->ipr_shift; |
75 | ctrl_outl(ipr, INTC2_BASE + p->ipr_offset); | 70 | ctrl_outl(ipr, desc->prio_base + p->ipr_offset); |
76 | 71 | ||
77 | local_irq_restore(flags); | 72 | local_irq_restore(flags); |
73 | } | ||
78 | 74 | ||
79 | set_irq_chip_and_handler_name(p->irq, &intc2_irq_chip, | 75 | set_irq_chip_and_handler_name(p->irq, &desc->chip, |
80 | handle_level_irq, "level"); | 76 | handle_level_irq, "level"); |
81 | set_irq_chip_data(p->irq, p); | 77 | set_irq_chip_data(p->irq, p); |
82 | 78 | ||
83 | enable_intc2_irq(p->irq); | 79 | disable_intc2_irq(p->irq); |
84 | } | 80 | } |
85 | } | 81 | } |