diff options
author | Yoshinori Sato <ysato@users.sourceforge.jp> | 2006-11-05 01:40:13 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2006-12-05 20:45:36 -0500 |
commit | 9d4436a6fbc8c5eccdfcb8f5884e0a7b4a57f6d2 (patch) | |
tree | a8b7532fffa76ae526dea547cc87200466e00842 /arch/sh/kernel/cpu/irq/ipr.c | |
parent | e62438630ca37539c8cc1553710bbfaa3cf960a7 (diff) |
sh: Add support for SH7206 and SH7619 CPU subtypes.
This implements initial support for the SH7206 (SH-2A) and SH7619
(SH-2) MMU-less CPUs.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/irq/ipr.c')
-rw-r--r-- | arch/sh/kernel/cpu/irq/ipr.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c index a0089563cbfc..f7a2bae1df94 100644 --- a/arch/sh/kernel/cpu/irq/ipr.c +++ b/arch/sh/kernel/cpu/irq/ipr.c | |||
@@ -62,6 +62,10 @@ void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs) | |||
62 | } | 62 | } |
63 | EXPORT_SYMBOL(make_ipr_irq); | 63 | EXPORT_SYMBOL(make_ipr_irq); |
64 | 64 | ||
65 | /* | ||
66 | * XXX: Move this garbage in to the drivers, and kill off the ridiculous CPU | ||
67 | * subtype checks. | ||
68 | */ | ||
65 | static struct ipr_data sys_ipr_map[] = { | 69 | static struct ipr_data sys_ipr_map[] = { |
66 | #ifndef CONFIG_CPU_SUBTYPE_SH7780 | 70 | #ifndef CONFIG_CPU_SUBTYPE_SH7780 |
67 | { TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY }, | 71 | { TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY }, |
@@ -80,6 +84,18 @@ static struct ipr_data sys_ipr_map[] = { | |||
80 | { SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY }, | 84 | { SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY }, |
81 | { SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY }, | 85 | { SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY }, |
82 | #endif | 86 | #endif |
87 | #ifdef SCIF2_ERI_IRQ | ||
88 | { SCIF2_ERI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY }, | ||
89 | { SCIF2_RXI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY }, | ||
90 | { SCIF2_BRI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY }, | ||
91 | { SCIF2_TXI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY }, | ||
92 | #endif | ||
93 | #ifdef SCIF3_ERI_IRQ | ||
94 | { SCIF3_ERI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY }, | ||
95 | { SCIF3_RXI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY }, | ||
96 | { SCIF3_BRI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY }, | ||
97 | { SCIF3_TXI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY }, | ||
98 | #endif | ||
83 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) | 99 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) |
84 | { SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, | 100 | { SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, |
85 | { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, | 101 | { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, |