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authorPaul Mundt <lethal@linux-sh.org>2007-11-10 06:25:28 -0500
committerPaul Mundt <lethal@linux-sh.org>2008-01-27 23:18:43 -0500
commit27a511c6f37c05c5cf8fae9fe513f60d87af9158 (patch)
tree1a4832642070fb7663d59900e578e575974c51f0 /arch/sh/kernel/cpu/init.c
parentc881cbc033c80d92d1bb7a0446735561a46e1f9c (diff)
sh: Disable initial cache flush on SH-5.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/init.c')
-rw-r--r--arch/sh/kernel/cpu/init.c32
1 files changed, 18 insertions, 14 deletions
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index f37f1c031631..fd1688e6c61c 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -63,24 +63,11 @@ static void __init speculative_execution_init(void)
63/* 63/*
64 * Generic first-level cache init 64 * Generic first-level cache init
65 */ 65 */
66#ifdef CONFIG_SUPERH32
66static void __init cache_init(void) 67static void __init cache_init(void)
67{ 68{
68 unsigned long ccr, flags; 69 unsigned long ccr, flags;
69 70
70 /* First setup the rest of the I-cache info */
71 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
72 current_cpu_data.icache.linesz;
73
74 current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
75 current_cpu_data.icache.linesz;
76
77 /* And the D-cache too */
78 current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
79 current_cpu_data.dcache.linesz;
80
81 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
82 current_cpu_data.dcache.linesz;
83
84 jump_to_P2(); 71 jump_to_P2();
85 ccr = ctrl_inl(CCR); 72 ccr = ctrl_inl(CCR);
86 73
@@ -160,6 +147,9 @@ static void __init cache_init(void)
160 ctrl_outl(flags, CCR); 147 ctrl_outl(flags, CCR);
161 back_to_P1(); 148 back_to_P1();
162} 149}
150#else
151#define cache_init() do { } while (0)
152#endif
163 153
164#ifdef CONFIG_SH_DSP 154#ifdef CONFIG_SH_DSP
165static void __init release_dsp(void) 155static void __init release_dsp(void)
@@ -230,6 +220,20 @@ asmlinkage void __cpuinit sh_cpu_init(void)
230 if (current_cpu_data.type == CPU_SH_NONE) 220 if (current_cpu_data.type == CPU_SH_NONE)
231 panic("Unknown CPU"); 221 panic("Unknown CPU");
232 222
223 /* First setup the rest of the I-cache info */
224 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
225 current_cpu_data.icache.linesz;
226
227 current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
228 current_cpu_data.icache.linesz;
229
230 /* And the D-cache too */
231 current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
232 current_cpu_data.dcache.linesz;
233
234 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
235 current_cpu_data.dcache.linesz;
236
233 /* Init the cache */ 237 /* Init the cache */
234 cache_init(); 238 cache_init();
235 239