diff options
author | Ryusuke Sakato <sakato.ryusuke@renesas.com> | 2007-04-30 20:45:29 -0400 |
---|---|---|
committer | Paul Mundt <lethal@hera.kernel.org> | 2007-05-06 22:11:57 -0400 |
commit | 6865f0ea6ad91fec3ae7831c49d48b5a7db4b428 (patch) | |
tree | f5e58cf973b6c49ed04dafb7fdc035f10d3366d3 /arch/sh/kernel/cf-enabler.c | |
parent | 6b817c03489083a7457cda16b953a214dcef8d64 (diff) |
sh: Solution Engine 7722 board support.
This adds more full-featured support for the SH7722 Solution Engine.
Previously this was using the generic board, and lacked most of the
peripheral support.
Signed-off-by: Ryusuke Sakato <sakato.ryusuke@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cf-enabler.c')
-rw-r--r-- | arch/sh/kernel/cf-enabler.c | 28 |
1 files changed, 19 insertions, 9 deletions
diff --git a/arch/sh/kernel/cf-enabler.c b/arch/sh/kernel/cf-enabler.c index 3e5fa1e24df0..0758d48147a0 100644 --- a/arch/sh/kernel/cf-enabler.c +++ b/arch/sh/kernel/cf-enabler.c | |||
@@ -29,7 +29,7 @@ | |||
29 | * 0xB8001000 : Common Memory | 29 | * 0xB8001000 : Common Memory |
30 | * 0xBA000000 : I/O | 30 | * 0xBA000000 : I/O |
31 | */ | 31 | */ |
32 | #if defined(CONFIG_IDE) && defined(CONFIG_CPU_SH4) | 32 | #if defined(CONFIG_CPU_SH4) |
33 | /* SH4 can't access PCMCIA interface through P2 area. | 33 | /* SH4 can't access PCMCIA interface through P2 area. |
34 | * we must remap it with appropreate attribute bit of the page set. | 34 | * we must remap it with appropreate attribute bit of the page set. |
35 | * this part is based on Greg Banks' hd64465_ss.c implementation - Masahiro Abe */ | 35 | * this part is based on Greg Banks' hd64465_ss.c implementation - Masahiro Abe */ |
@@ -71,7 +71,7 @@ static int __init cf_init_default(void) | |||
71 | /* You must have enabled the card, and set the level interrupt | 71 | /* You must have enabled the card, and set the level interrupt |
72 | * before reaching this point. Possibly in boot ROM or boot loader. | 72 | * before reaching this point. Possibly in boot ROM or boot loader. |
73 | */ | 73 | */ |
74 | #if defined(CONFIG_IDE) && defined(CONFIG_CPU_SH4) | 74 | #if defined(CONFIG_CPU_SH4) |
75 | allocate_cf_area(); | 75 | allocate_cf_area(); |
76 | #endif | 76 | #endif |
77 | #if defined(CONFIG_SH_UNKNOWN) | 77 | #if defined(CONFIG_SH_UNKNOWN) |
@@ -84,15 +84,25 @@ static int __init cf_init_default(void) | |||
84 | 84 | ||
85 | #if defined(CONFIG_SH_SOLUTION_ENGINE) | 85 | #if defined(CONFIG_SH_SOLUTION_ENGINE) |
86 | #include <asm/se.h> | 86 | #include <asm/se.h> |
87 | #elif defined(CONFIG_SH_7722_SOLUTION_ENGINE) | ||
88 | #include <asm/se7722.h> | ||
89 | #endif | ||
87 | 90 | ||
88 | /* | 91 | /* |
89 | * SolutionEngine | 92 | * SolutionEngine Seriese |
90 | * | 93 | * |
94 | * about MS770xSE | ||
91 | * 0xB8400000 : Common Memory | 95 | * 0xB8400000 : Common Memory |
92 | * 0xB8500000 : Attribute | 96 | * 0xB8500000 : Attribute |
93 | * 0xB8600000 : I/O | 97 | * 0xB8600000 : I/O |
98 | * | ||
99 | * about MS7722SE | ||
100 | * 0xB0400000 : Common Memory | ||
101 | * 0xB0500000 : Attribute | ||
102 | * 0xB0600000 : I/O | ||
94 | */ | 103 | */ |
95 | 104 | ||
105 | #if defined(CONFIG_SH_SOLUTION_ENGINE) || defined(CONFIG_SH_7722_SOLUTION_ENGINE) | ||
96 | static int __init cf_init_se(void) | 106 | static int __init cf_init_se(void) |
97 | { | 107 | { |
98 | if ((ctrl_inw(MRSHPC_CSR) & 0x000c) != 0) | 108 | if ((ctrl_inw(MRSHPC_CSR) & 0x000c) != 0) |
@@ -109,7 +119,7 @@ static int __init cf_init_se(void) | |||
109 | * flag == COMMON/ATTRIBUTE/IO | 119 | * flag == COMMON/ATTRIBUTE/IO |
110 | */ | 120 | */ |
111 | /* common window open */ | 121 | /* common window open */ |
112 | ctrl_outw(0x8a84, MRSHPC_MW0CR1);/* window 0xb8400000 */ | 122 | ctrl_outw(0x8a84, MRSHPC_MW0CR1); |
113 | if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0) | 123 | if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0) |
114 | /* common mode & bus width 16bit SWAP = 1*/ | 124 | /* common mode & bus width 16bit SWAP = 1*/ |
115 | ctrl_outw(0x0b00, MRSHPC_MW0CR2); | 125 | ctrl_outw(0x0b00, MRSHPC_MW0CR2); |
@@ -118,7 +128,7 @@ static int __init cf_init_se(void) | |||
118 | ctrl_outw(0x0300, MRSHPC_MW0CR2); | 128 | ctrl_outw(0x0300, MRSHPC_MW0CR2); |
119 | 129 | ||
120 | /* attribute window open */ | 130 | /* attribute window open */ |
121 | ctrl_outw(0x8a85, MRSHPC_MW1CR1);/* window 0xb8500000 */ | 131 | ctrl_outw(0x8a85, MRSHPC_MW1CR1); |
122 | if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0) | 132 | if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0) |
123 | /* attribute mode & bus width 16bit SWAP = 1*/ | 133 | /* attribute mode & bus width 16bit SWAP = 1*/ |
124 | ctrl_outw(0x0a00, MRSHPC_MW1CR2); | 134 | ctrl_outw(0x0a00, MRSHPC_MW1CR2); |
@@ -127,7 +137,7 @@ static int __init cf_init_se(void) | |||
127 | ctrl_outw(0x0200, MRSHPC_MW1CR2); | 137 | ctrl_outw(0x0200, MRSHPC_MW1CR2); |
128 | 138 | ||
129 | /* I/O window open */ | 139 | /* I/O window open */ |
130 | ctrl_outw(0x8a86, MRSHPC_IOWCR1);/* I/O window 0xb8600000 */ | 140 | ctrl_outw(0x8a86, MRSHPC_IOWCR1); |
131 | ctrl_outw(0x0008, MRSHPC_CDCR); /* I/O card mode */ | 141 | ctrl_outw(0x0008, MRSHPC_CDCR); /* I/O card mode */ |
132 | if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0) | 142 | if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0) |
133 | ctrl_outw(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/ | 143 | ctrl_outw(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/ |
@@ -143,10 +153,10 @@ static int __init cf_init_se(void) | |||
143 | 153 | ||
144 | int __init cf_init(void) | 154 | int __init cf_init(void) |
145 | { | 155 | { |
146 | #if defined(CONFIG_SH_SOLUTION_ENGINE) | 156 | if( mach_is_se() || mach_is_7722se() ){ |
147 | if (MACH_SE) | ||
148 | return cf_init_se(); | 157 | return cf_init_se(); |
149 | #endif | 158 | } |
159 | |||
150 | return cf_init_default(); | 160 | return cf_init_default(); |
151 | } | 161 | } |
152 | 162 | ||