Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (28 commits)
  mm/hugetlb.c must #include <asm/io.h>
  video: Fix up hp6xx driver build regressions.
  sh: defconfig updates.
  sh: Kill off stray mach-rsk7203 reference.
  serial: sh-sci: Fix up SH7760/SH7780/SH7785 early printk regression.
  sh: Move out individual boards without mach groups.
  sh: Make sure AT_SYSINFO_EHDR is exposed to userspace in asm/auxvec.h.
  sh: Allow SH-3 and SH-5 to use common headers.
  sh: Provide common CPU headers, prune the SH-2 and SH-2A directories.
  sh/maple: clean maple bus code
  sh: More header path fixups for mach dir refactoring.
  sh: Move out the solution engine headers to arch/sh/include/mach-se/
  sh: I2C fix for AP325RXA and Migo-R
  sh: Shuffle the board directories in to mach groups.
  sh: dma-sh: Fix up dreamcast dma.h mach path.
  sh: Switch KBUILD_DEFCONFIG to shx3_defconfig.
  sh: Add ARCH_DEFCONFIG entries for sh and sh64.
  sh: Fix compile error of Solution Engine
  sh: Proper __put_user_asm() size mismatch fix.
  sh: Stub in a dummy ENTRY_OFFSET for uImage offset calculation.
  ...

241 files changed, 16287 insertions, 0 deletions

diff --git a/arch/sh/include/asm/.gitignore b/arch/sh/include/asm/.gitignore
new file mode 100644
index 000000000000..378db779fb6c
--- /dev/null
+++ b/arch/sh/include/asm/.gitignore
@@ -0,0 +1 @@
+machtypes.h
diff --git a/arch/sh/include/asm/Kbuild b/arch/sh/include/asm/Kbuild
new file mode 100644
index 000000000000..43910cdf78a5
--- /dev/null
+++ b/arch/sh/include/asm/Kbuild
@@ -0,0 +1,8 @@
+include include/asm-generic/Kbuild.asm
+
+header-y += cpu-features.h
+
+unifdef-y += unistd_32.h
+unifdef-y += unistd_64.h
+unifdef-y += posix_types_32.h
+unifdef-y += posix_types_64.h
diff --git a/arch/sh/include/asm/a.out.h b/arch/sh/include/asm/a.out.h
new file mode 100644
index 000000000000..1f93130e179c
--- /dev/null
+++ b/arch/sh/include/asm/a.out.h
@@ -0,0 +1,20 @@
+#ifndef __ASM_SH_A_OUT_H
+#define __ASM_SH_A_OUT_H
+
+struct exec
+{
+  unsigned long a_info;         /* Use macros N_MAGIC, etc for access */
+  unsigned a_text;              /* length of text, in bytes */
+  unsigned a_data;              /* length of data, in bytes */
+  unsigned a_bss;               /* length of uninitialized data area for file, in bytes */
+  unsigned a_syms;              /* length of symbol table data in file, in bytes */
+  unsigned a_entry;             /* start address */
+  unsigned a_trsize;            /* length of relocation info for text, in bytes */
+  unsigned a_drsize;            /* length of relocation info for data, in bytes */
+};
+
+#define N_TRSIZE(a)     ((a).a_trsize)
+#define N_DRSIZE(a)     ((a).a_drsize)
+#define N_SYMSIZE(a)    ((a).a_syms)
+
+#endif /* __ASM_SH_A_OUT_H */
diff --git a/arch/sh/include/asm/adc.h b/arch/sh/include/asm/adc.h
new file mode 100644
index 000000000000..48824c1fab80
--- /dev/null
+++ b/arch/sh/include/asm/adc.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_ADC_H
+#define __ASM_ADC_H
+#ifdef __KERNEL__
+/*
+ * Copyright (C) 2004  Andriy Skulysh
+ */
+
+#include <cpu/adc.h>
+
+int adc_single(unsigned int channel);
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_ADC_H */
diff --git a/arch/sh/include/asm/addrspace.h b/arch/sh/include/asm/addrspace.h
new file mode 100644
index 000000000000..2702d81bfc0d
--- /dev/null
+++ b/arch/sh/include/asm/addrspace.h
@@ -0,0 +1,53 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 by Kaz Kojima
+ *
+ * Defitions for the address spaces of the SH CPUs.
+ */
+#ifndef __ASM_SH_ADDRSPACE_H
+#define __ASM_SH_ADDRSPACE_H
+
+#ifdef __KERNEL__
+
+#include <cpu/addrspace.h>
+
+/* If this CPU supports segmentation, hook up the helpers */
+#ifdef P1SEG
+
+/*
+   [ P0/U0 (virtual) ]          0x00000000     <------ User space
+   [ P1 (fixed)   cached ]      0x80000000     <------ Kernel space
+   [ P2 (fixed)  non-cachable]  0xA0000000     <------ Physical access
+   [ P3 (virtual) cached]       0xC0000000     <------ vmalloced area
+   [ P4 control   ]             0xE0000000
+ */
+
+/* Returns the privileged segment base of a given address  */
+#define PXSEG(a)        (((unsigned long)(a)) & 0xe0000000)
+
+/* Returns the physical address of a PnSEG (n=1,2) address   */
+#define PHYSADDR(a)     (((unsigned long)(a)) & 0x1fffffff)
+
+#ifdef CONFIG_29BIT
+/*
+ * Map an address to a certain privileged segment
+ */
+#define P1SEGADDR(a)    \
+        ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
+#define P2SEGADDR(a)    \
+        ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
+#define P3SEGADDR(a)    \
+        ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
+#define P4SEGADDR(a)    \
+        ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
+#endif /* 29BIT */
+#endif /* P1SEG */
+
+/* Check if an address can be reached in 29 bits */
+#define IS_29BIT(a)     (((unsigned long)(a)) < 0x20000000)
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_ADDRSPACE_H */
diff --git a/arch/sh/include/asm/atomic-grb.h b/arch/sh/include/asm/atomic-grb.h
new file mode 100644
index 000000000000..4c5b7dbfcedb
--- /dev/null
+++ b/arch/sh/include/asm/atomic-grb.h
@@ -0,0 +1,169 @@
+#ifndef __ASM_SH_ATOMIC_GRB_H
+#define __ASM_SH_ATOMIC_GRB_H
+
+static inline void atomic_add(int i, atomic_t *v)
+{
+        int tmp;
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   add     %2,   %0      \n\t" /* add */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (v)
+                : "r"   (i)
+                : "memory" , "r0", "r1");
+}
+
+static inline void atomic_sub(int i, atomic_t *v)
+{
+        int tmp;
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov     r15,  r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   sub     %2,   %0      \n\t" /* sub */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (v)
+                : "r"   (i)
+                : "memory" , "r0", "r1");
+}
+
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+        int tmp;
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   add     %2,   %0      \n\t" /* add */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (v)
+                : "r"   (i)
+                : "memory" , "r0", "r1");
+
+        return tmp;
+}
+
+static inline int atomic_sub_return(int i, atomic_t *v)
+{
+        int tmp;
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   sub     %2,   %0      \n\t" /* sub */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (v)
+                : "r"   (i)
+                : "memory", "r0", "r1");
+
+        return tmp;
+}
+
+static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
+{
+        int tmp;
+        unsigned int _mask = ~mask;
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   and     %2,   %0      \n\t" /* add */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (v)
+                : "r"   (_mask)
+                : "memory" , "r0", "r1");
+}
+
+static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
+{
+        int tmp;
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   or      %2,   %0      \n\t" /* or */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (v)
+                : "r"   (mask)
+                : "memory" , "r0", "r1");
+}
+
+static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
+{
+        int ret;
+
+        __asm__ __volatile__ (
+                "   .align 2            \n\t"
+                "   mova     1f,  r0    \n\t"
+                "   nop                 \n\t"
+                "   mov     r15,  r1    \n\t"
+                "   mov    #-8,  r15    \n\t"
+                "   mov.l   @%1,  %0    \n\t"
+                "   cmp/eq   %2,  %0    \n\t"
+                "   bf       1f         \n\t"
+                "   mov.l    %3, @%1    \n\t"
+                "1: mov      r1,  r15   \n\t"
+                : "=&r" (ret)
+                : "r" (v), "r" (old), "r" (new)
+                : "memory" , "r0", "r1" , "t");
+
+        return ret;
+}
+
+static inline int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int ret;
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+                "   .align 2            \n\t"
+                "   mova    1f,   r0    \n\t"
+                "   nop                 \n\t"
+                "   mov    r15,   r1    \n\t"
+                "   mov    #-12,  r15   \n\t"
+                "   mov.l  @%2,   %1    \n\t"
+                "   mov     %1,   %0    \n\t"
+                "   cmp/eq  %4,   %0    \n\t"
+                "   bt/s    1f          \n\t"
+                "    add    %3,   %1    \n\t"
+                "   mov.l   %1,  @%2    \n\t"
+                "1: mov     r1,   r15   \n\t"
+                : "=&r" (ret), "=&r" (tmp)
+                : "r" (v), "r" (a), "r" (u)
+                : "memory" , "r0", "r1" , "t");
+
+        return ret != u;
+}
+#endif /* __ASM_SH_ATOMIC_GRB_H */
diff --git a/arch/sh/include/asm/atomic-irq.h b/arch/sh/include/asm/atomic-irq.h
new file mode 100644
index 000000000000..74f7943cff6f
--- /dev/null
+++ b/arch/sh/include/asm/atomic-irq.h
@@ -0,0 +1,71 @@
+#ifndef __ASM_SH_ATOMIC_IRQ_H
+#define __ASM_SH_ATOMIC_IRQ_H
+
+/*
+ * To get proper branch prediction for the main line, we must branch
+ * forward to code at the end of this object's .text section, then
+ * branch back to restart the operation.
+ */
+static inline void atomic_add(int i, atomic_t *v)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        *(long *)v += i;
+        local_irq_restore(flags);
+}
+
+static inline void atomic_sub(int i, atomic_t *v)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        *(long *)v -= i;
+        local_irq_restore(flags);
+}
+
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+        unsigned long temp, flags;
+
+        local_irq_save(flags);
+        temp = *(long *)v;
+        temp += i;
+        *(long *)v = temp;
+        local_irq_restore(flags);
+
+        return temp;
+}
+
+static inline int atomic_sub_return(int i, atomic_t *v)
+{
+        unsigned long temp, flags;
+
+        local_irq_save(flags);
+        temp = *(long *)v;
+        temp -= i;
+        *(long *)v = temp;
+        local_irq_restore(flags);
+
+        return temp;
+}
+
+static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        *(long *)v &= ~mask;
+        local_irq_restore(flags);
+}
+
+static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        *(long *)v |= mask;
+        local_irq_restore(flags);
+}
+
+#endif /* __ASM_SH_ATOMIC_IRQ_H */
diff --git a/arch/sh/include/asm/atomic-llsc.h b/arch/sh/include/asm/atomic-llsc.h
new file mode 100644
index 000000000000..4b00b78e3f4f
--- /dev/null
+++ b/arch/sh/include/asm/atomic-llsc.h
@@ -0,0 +1,107 @@
+#ifndef __ASM_SH_ATOMIC_LLSC_H
+#define __ASM_SH_ATOMIC_LLSC_H
+
+/*
+ * To get proper branch prediction for the main line, we must branch
+ * forward to code at the end of this object's .text section, then
+ * branch back to restart the operation.
+ */
+static inline void atomic_add(int i, atomic_t *v)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+"1:     movli.l @%2, %0         ! atomic_add    \n"
+"       add     %1, %0                          \n"
+"       movco.l %0, @%2                         \n"
+"       bf      1b                              \n"
+        : "=&z" (tmp)
+        : "r" (i), "r" (&v->counter)
+        : "t");
+}
+
+static inline void atomic_sub(int i, atomic_t *v)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+"1:     movli.l @%2, %0         ! atomic_sub    \n"
+"       sub     %1, %0                          \n"
+"       movco.l %0, @%2                         \n"
+"       bf      1b                              \n"
+        : "=&z" (tmp)
+        : "r" (i), "r" (&v->counter)
+        : "t");
+}
+
+/*
+ * SH-4A note:
+ *
+ * We basically get atomic_xxx_return() for free compared with
+ * atomic_xxx(). movli.l/movco.l require r0 due to the instruction
+ * encoding, so the retval is automatically set without having to
+ * do any special work.
+ */
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+        unsigned long temp;
+
+        __asm__ __volatile__ (
+"1:     movli.l @%2, %0         ! atomic_add_return     \n"
+"       add     %1, %0                                  \n"
+"       movco.l %0, @%2                                 \n"
+"       bf      1b                                      \n"
+"       synco                                           \n"
+        : "=&z" (temp)
+        : "r" (i), "r" (&v->counter)
+        : "t");
+
+        return temp;
+}
+
+static inline int atomic_sub_return(int i, atomic_t *v)
+{
+        unsigned long temp;
+
+        __asm__ __volatile__ (
+"1:     movli.l @%2, %0         ! atomic_sub_return     \n"
+"       sub     %1, %0                                  \n"
+"       movco.l %0, @%2                                 \n"
+"       bf      1b                                      \n"
+"       synco                                           \n"
+        : "=&z" (temp)
+        : "r" (i), "r" (&v->counter)
+        : "t");
+
+        return temp;
+}
+
+static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+"1:     movli.l @%2, %0         ! atomic_clear_mask     \n"
+"       and     %1, %0                                  \n"
+"       movco.l %0, @%2                                 \n"
+"       bf      1b                                      \n"
+        : "=&z" (tmp)
+        : "r" (~mask), "r" (&v->counter)
+        : "t");
+}
+
+static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+"1:     movli.l @%2, %0         ! atomic_set_mask       \n"
+"       or      %1, %0                                  \n"
+"       movco.l %0, @%2                                 \n"
+"       bf      1b                                      \n"
+        : "=&z" (tmp)
+        : "r" (mask), "r" (&v->counter)
+        : "t");
+}
+
+#endif /* __ASM_SH_ATOMIC_LLSC_H */
diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h
new file mode 100644
index 000000000000..c043ef003028
--- /dev/null
+++ b/arch/sh/include/asm/atomic.h
@@ -0,0 +1,89 @@
+#ifndef __ASM_SH_ATOMIC_H
+#define __ASM_SH_ATOMIC_H
+
+/*
+ * Atomic operations that C can't guarantee us.  Useful for
+ * resource counting etc..
+ *
+ */
+
+typedef struct { volatile int counter; } atomic_t;
+
+#define ATOMIC_INIT(i)  ( (atomic_t) { (i) } )
+
+#define atomic_read(v)          ((v)->counter)
+#define atomic_set(v,i)         ((v)->counter = (i))
+
+#include <linux/compiler.h>
+#include <asm/system.h>
+
+#if defined(CONFIG_GUSA_RB)
+#include <asm/atomic-grb.h>
+#elif defined(CONFIG_CPU_SH4A)
+#include <asm/atomic-llsc.h>
+#else
+#include <asm/atomic-irq.h>
+#endif
+
+#define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
+
+#define atomic_dec_return(v) atomic_sub_return(1,(v))
+#define atomic_inc_return(v) atomic_add_return(1,(v))
+
+/*
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
+
+#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
+#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
+
+#define atomic_inc(v) atomic_add(1,(v))
+#define atomic_dec(v) atomic_sub(1,(v))
+
+#ifndef CONFIG_GUSA_RB
+static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
+{
+        int ret;
+        unsigned long flags;
+
+        local_irq_save(flags);
+        ret = v->counter;
+        if (likely(ret == old))
+                v->counter = new;
+        local_irq_restore(flags);
+
+        return ret;
+}
+
+static inline int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int ret;
+        unsigned long flags;
+
+        local_irq_save(flags);
+        ret = v->counter;
+        if (ret != u)
+                v->counter += a;
+        local_irq_restore(flags);
+
+        return ret != u;
+}
+#endif
+
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
+
+/* Atomic operations are already serializing on SH */
+#define smp_mb__before_atomic_dec()     barrier()
+#define smp_mb__after_atomic_dec()      barrier()
+#define smp_mb__before_atomic_inc()     barrier()
+#define smp_mb__after_atomic_inc()      barrier()
+
+#include <asm-generic/atomic.h>
+#endif /* __ASM_SH_ATOMIC_H */
diff --git a/arch/sh/include/asm/auxvec.h b/arch/sh/include/asm/auxvec.h
new file mode 100644
index 000000000000..483effd65e00
--- /dev/null
+++ b/arch/sh/include/asm/auxvec.h
@@ -0,0 +1,36 @@
+#ifndef __ASM_SH_AUXVEC_H
+#define __ASM_SH_AUXVEC_H
+
+/*
+ * Architecture-neutral AT_ values in 0-17, leave some room
+ * for more of them.
+ */
+
+/*
+ * This entry gives some information about the FPU initialization
+ * performed by the kernel.
+ */
+#define AT_FPUCW                18      /* Used FPU control word.  */
+
+#if defined(CONFIG_VSYSCALL) || !defined(__KERNEL__)
+/*
+ * Only define this in the vsyscall case, the entry point to
+ * the vsyscall page gets placed here. The kernel will attempt
+ * to build a gate VMA we don't care about otherwise..
+ */
+#define AT_SYSINFO_EHDR         33
+#endif
+
+/*
+ * More complete cache descriptions than AT_[DIU]CACHEBSIZE.  If the
+ * value is -1, then the cache doesn't exist.  Otherwise:
+ *
+ *    bit 0-3:    Cache set-associativity; 0 means fully associative.
+ *    bit 4-7:    Log2 of cacheline size.
+ *    bit 8-31:   Size of the entire cache >> 8.
+ */
+#define AT_L1I_CACHESHAPE       34
+#define AT_L1D_CACHESHAPE       35
+#define AT_L2_CACHESHAPE        36
+
+#endif /* __ASM_SH_AUXVEC_H */
diff --git a/arch/sh/include/asm/bitops-grb.h b/arch/sh/include/asm/bitops-grb.h
new file mode 100644
index 000000000000..a5907b94395b
--- /dev/null
+++ b/arch/sh/include/asm/bitops-grb.h
@@ -0,0 +1,169 @@
+#ifndef __ASM_SH_BITOPS_GRB_H
+#define __ASM_SH_BITOPS_GRB_H
+
+static inline void set_bit(int nr, volatile void * addr)
+{
+        int     mask;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   or      %2,   %0      \n\t" /* or */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (a)
+                : "r"   (mask)
+                : "memory" , "r0", "r1");
+}
+
+static inline void clear_bit(int nr, volatile void * addr)
+{
+        int     mask;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = ~(1 << (nr & 0x1f));
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   and     %2,   %0      \n\t" /* and */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (a)
+                : "r"   (mask)
+                : "memory" , "r0", "r1");
+}
+
+static inline void change_bit(int nr, volatile void * addr)
+{
+        int     mask;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   xor     %2,   %0      \n\t" /* xor */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (a)
+                : "r"   (mask)
+                : "memory" , "r0", "r1");
+}
+
+static inline int test_and_set_bit(int nr, volatile void * addr)
+{
+        int     mask, retval;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov   #-14,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%2,   %0      \n\t" /* load old value */
+                "   mov     %0,   %1      \n\t"
+                "   tst     %1,   %3      \n\t" /* T = ((*a & mask) == 0) */
+                "   mov    #-1,   %1      \n\t" /* retvat = -1 */
+                "   negc    %1,   %1      \n\t" /* retval = (mask & *a) != 0 */
+                "   or      %3,   %0      \n\t"
+                "   mov.l   %0,  @%2      \n\t" /* store new value */
+                "1: mov     r1,  r15      \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "=&r" (retval),
+                  "+r"  (a)
+                : "r"   (mask)
+                : "memory" , "r0", "r1" ,"t");
+
+        return retval;
+}
+
+static inline int test_and_clear_bit(int nr, volatile void * addr)
+{
+        int     mask, retval,not_mask;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+
+        not_mask = ~mask;
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov   #-14,   r15     \n\t" /* LOGIN */
+                "   mov.l  @%2,   %0      \n\t" /* load old value */
+                "   mov     %0,   %1      \n\t" /* %1 = *a */
+                "   tst     %1,   %3      \n\t" /* T = ((*a & mask) == 0) */
+                "   mov    #-1,   %1      \n\t" /* retvat = -1 */
+                "   negc    %1,   %1      \n\t" /* retval = (mask & *a) != 0 */
+                "   and     %4,   %0      \n\t"
+                "   mov.l   %0,  @%2      \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "=&r" (retval),
+                  "+r"  (a)
+                : "r"   (mask),
+                  "r"   (not_mask)
+                : "memory" , "r0", "r1", "t");
+
+        return retval;
+}
+
+static inline int test_and_change_bit(int nr, volatile void * addr)
+{
+        int     mask, retval;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov   #-14,   r15     \n\t" /* LOGIN */
+                "   mov.l  @%2,   %0      \n\t" /* load old value */
+                "   mov     %0,   %1      \n\t" /* %1 = *a */
+                "   tst     %1,   %3      \n\t" /* T = ((*a & mask) == 0) */
+                "   mov    #-1,   %1      \n\t" /* retvat = -1 */
+                "   negc    %1,   %1      \n\t" /* retval = (mask & *a) != 0 */
+                "   xor     %3,   %0      \n\t"
+                "   mov.l   %0,  @%2      \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "=&r" (retval),
+                  "+r"  (a)
+                : "r"   (mask)
+                : "memory" , "r0", "r1", "t");
+
+        return retval;
+}
+#endif /* __ASM_SH_BITOPS_GRB_H */
diff --git a/arch/sh/include/asm/bitops-irq.h b/arch/sh/include/asm/bitops-irq.h
new file mode 100644
index 000000000000..653a12750584
--- /dev/null
+++ b/arch/sh/include/asm/bitops-irq.h
@@ -0,0 +1,91 @@
+#ifndef __ASM_SH_BITOPS_IRQ_H
+#define __ASM_SH_BITOPS_IRQ_H
+
+static inline void set_bit(int nr, volatile void *addr)
+{
+        int     mask;
+        volatile unsigned int *a = addr;
+        unsigned long flags;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        *a |= mask;
+        local_irq_restore(flags);
+}
+
+static inline void clear_bit(int nr, volatile void *addr)
+{
+        int     mask;
+        volatile unsigned int *a = addr;
+        unsigned long flags;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        *a &= ~mask;
+        local_irq_restore(flags);
+}
+
+static inline void change_bit(int nr, volatile void *addr)
+{
+        int     mask;
+        volatile unsigned int *a = addr;
+        unsigned long flags;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        *a ^= mask;
+        local_irq_restore(flags);
+}
+
+static inline int test_and_set_bit(int nr, volatile void *addr)
+{
+        int     mask, retval;
+        volatile unsigned int *a = addr;
+        unsigned long flags;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        retval = (mask & *a) != 0;
+        *a |= mask;
+        local_irq_restore(flags);
+
+        return retval;
+}
+
+static inline int test_and_clear_bit(int nr, volatile void *addr)
+{
+        int     mask, retval;
+        volatile unsigned int *a = addr;
+        unsigned long flags;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        retval = (mask & *a) != 0;
+        *a &= ~mask;
+        local_irq_restore(flags);
+
+        return retval;
+}
+
+static inline int test_and_change_bit(int nr, volatile void *addr)
+{
+        int     mask, retval;
+        volatile unsigned int *a = addr;
+        unsigned long flags;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        retval = (mask & *a) != 0;
+        *a ^= mask;
+        local_irq_restore(flags);
+
+        return retval;
+}
+
+#endif /* __ASM_SH_BITOPS_IRQ_H */
diff --git a/arch/sh/include/asm/bitops.h b/arch/sh/include/asm/bitops.h
new file mode 100644
index 000000000000..d7d382f63ee5
--- /dev/null
+++ b/arch/sh/include/asm/bitops.h
@@ -0,0 +1,103 @@
+#ifndef __ASM_SH_BITOPS_H
+#define __ASM_SH_BITOPS_H
+
+#ifdef __KERNEL__
+
+#ifndef _LINUX_BITOPS_H
+#error only <linux/bitops.h> can be included directly
+#endif
+
+#include <asm/system.h>
+/* For __swab32 */
+#include <asm/byteorder.h>
+
+#ifdef CONFIG_GUSA_RB
+#include <asm/bitops-grb.h>
+#else
+#include <asm/bitops-irq.h>
+#endif
+
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()      barrier()
+#define smp_mb__after_clear_bit()       barrier()
+
+#include <asm-generic/bitops/non-atomic.h>
+
+#ifdef CONFIG_SUPERH32
+static inline unsigned long ffz(unsigned long word)
+{
+        unsigned long result;
+
+        __asm__("1:\n\t"
+                "shlr   %1\n\t"
+                "bt/s   1b\n\t"
+                " add   #1, %0"
+                : "=r" (result), "=r" (word)
+                : "0" (~0L), "1" (word)
+                : "t");
+        return result;
+}
+
+/**
+ * __ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static inline unsigned long __ffs(unsigned long word)
+{
+        unsigned long result;
+
+        __asm__("1:\n\t"
+                "shlr   %1\n\t"
+                "bf/s   1b\n\t"
+                " add   #1, %0"
+                : "=r" (result), "=r" (word)
+                : "0" (~0L), "1" (word)
+                : "t");
+        return result;
+}
+#else
+static inline unsigned long ffz(unsigned long word)
+{
+        unsigned long result, __d2, __d3;
+
+        __asm__("gettr  tr0, %2\n\t"
+                "pta    $+32, tr0\n\t"
+                "andi   %1, 1, %3\n\t"
+                "beq    %3, r63, tr0\n\t"
+                "pta    $+4, tr0\n"
+                "0:\n\t"
+                "shlri.l        %1, 1, %1\n\t"
+                "addi   %0, 1, %0\n\t"
+                "andi   %1, 1, %3\n\t"
+                "beqi   %3, 1, tr0\n"
+                "1:\n\t"
+                "ptabs  %2, tr0\n\t"
+                : "=r" (result), "=r" (word), "=r" (__d2), "=r" (__d3)
+                : "0" (0L), "1" (word));
+
+        return result;
+}
+
+#include <asm-generic/bitops/__ffs.h>
+#endif
+
+#include <asm-generic/bitops/find.h>
+#include <asm-generic/bitops/ffs.h>
+#include <asm-generic/bitops/hweight.h>
+#include <asm-generic/bitops/lock.h>
+#include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/ext2-non-atomic.h>
+#include <asm-generic/bitops/ext2-atomic.h>
+#include <asm-generic/bitops/minix.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_BITOPS_H */
diff --git a/arch/sh/include/asm/bug.h b/arch/sh/include/asm/bug.h
new file mode 100644
index 000000000000..c01718040166
--- /dev/null
+++ b/arch/sh/include/asm/bug.h
@@ -0,0 +1,79 @@
+#ifndef __ASM_SH_BUG_H
+#define __ASM_SH_BUG_H
+
+#define TRAPA_BUG_OPCODE        0xc33e  /* trapa #0x3e */
+
+#ifdef CONFIG_GENERIC_BUG
+#define HAVE_ARCH_BUG
+#define HAVE_ARCH_WARN_ON
+
+/**
+ * _EMIT_BUG_ENTRY
+ * %1 - __FILE__
+ * %2 - __LINE__
+ * %3 - trap type
+ * %4 - sizeof(struct bug_entry)
+ *
+ * The trapa opcode itself sits in %0.
+ * The %O notation is used to avoid # generation.
+ *
+ * The offending file and line are encoded in the __bug_table section.
+ */
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+#define _EMIT_BUG_ENTRY                         \
+        "\t.pushsection __bug_table,\"a\"\n"    \
+        "2:\t.long 1b, %O1\n"                   \
+        "\t.short %O2, %O3\n"                   \
+        "\t.org 2b+%O4\n"                       \
+        "\t.popsection\n"
+#else
+#define _EMIT_BUG_ENTRY                         \
+        "\t.pushsection __bug_table,\"a\"\n"    \
+        "2:\t.long 1b\n"                        \
+        "\t.short %O3\n"                        \
+        "\t.org 2b+%O4\n"                       \
+        "\t.popsection\n"
+#endif
+
+#define BUG()                                           \
+do {                                                    \
+        __asm__ __volatile__ (                          \
+                "1:\t.short %O0\n"                      \
+                _EMIT_BUG_ENTRY                         \
+                 :                                      \
+                 : "n" (TRAPA_BUG_OPCODE),              \
+                   "i" (__FILE__),                      \
+                   "i" (__LINE__), "i" (0),             \
+                   "i" (sizeof(struct bug_entry)));     \
+} while (0)
+
+#define __WARN()                                        \
+do {                                                    \
+        __asm__ __volatile__ (                          \
+                "1:\t.short %O0\n"                      \
+                 _EMIT_BUG_ENTRY                        \
+                 :                                      \
+                 : "n" (TRAPA_BUG_OPCODE),              \
+                   "i" (__FILE__),                      \
+                   "i" (__LINE__),                      \
+                   "i" (BUGFLAG_WARNING),               \
+                   "i" (sizeof(struct bug_entry)));     \
+} while (0)
+
+#define WARN_ON(x) ({                                           \
+        int __ret_warn_on = !!(x);                              \
+        if (__builtin_constant_p(__ret_warn_on)) {              \
+                if (__ret_warn_on)                              \
+                        __WARN();                               \
+        } else {                                                \
+                if (unlikely(__ret_warn_on))                    \
+                        __WARN();                               \
+        }                                                       \
+        unlikely(__ret_warn_on);                                \
+})
+
+#endif /* CONFIG_GENERIC_BUG */
+
+#include <asm-generic/bug.h>
+
+#endif /* __ASM_SH_BUG_H */
diff --git a/arch/sh/include/asm/bugs.h b/arch/sh/include/asm/bugs.h
new file mode 100644
index 000000000000..121b2ecddfc3
--- /dev/null
+++ b/arch/sh/include/asm/bugs.h
@@ -0,0 +1,73 @@
+#ifndef __ASM_SH_BUGS_H
+#define __ASM_SH_BUGS_H
+
+/*
+ * This is included by init/main.c to check for architecture-dependent bugs.
+ *
+ * Needs:
+ *      void check_bugs(void);
+ */
+
+/*
+ * I don't know of any Super-H bugs yet.
+ */
+
+#include <asm/processor.h>
+
+static void __init check_bugs(void)
+{
+        extern unsigned long loops_per_jiffy;
+        char *p = &init_utsname()->machine[2]; /* "sh" */
+
+        current_cpu_data.loops_per_jiffy = loops_per_jiffy;
+
+        switch (current_cpu_data.type) {
+        case CPU_SH7619:
+                *p++ = '2';
+                break;
+        case CPU_SH7203 ... CPU_MXG:
+                *p++ = '2';
+                *p++ = 'a';
+                break;
+        case CPU_SH7705 ... CPU_SH7729:
+                *p++ = '3';
+                break;
+        case CPU_SH7750 ... CPU_SH4_501:
+                *p++ = '4';
+                break;
+        case CPU_SH7763 ... CPU_SHX3:
+                *p++ = '4';
+                *p++ = 'a';
+                break;
+        case CPU_SH7343 ... CPU_SH7366:
+                *p++ = '4';
+                *p++ = 'a';
+                *p++ = 'l';
+                *p++ = '-';
+                *p++ = 'd';
+                *p++ = 's';
+                *p++ = 'p';
+                break;
+        case CPU_SH5_101 ... CPU_SH5_103:
+                *p++ = '6';
+                *p++ = '4';
+                break;
+        case CPU_SH_NONE:
+                /*
+                 * Specifically use CPU_SH_NONE rather than default:,
+                 * so we're able to have the compiler whine about
+                 * unhandled enumerations.
+                 */
+                break;
+        }
+
+        printk("CPU: %s\n", get_cpu_subtype(&current_cpu_data));
+
+#ifndef __LITTLE_ENDIAN__
+        /* 'eb' means 'Endian Big' */
+        *p++ = 'e';
+        *p++ = 'b';
+#endif
+        *p = '\0';
+}
+#endif /* __ASM_SH_BUGS_H */
diff --git a/arch/sh/include/asm/byteorder.h b/arch/sh/include/asm/byteorder.h
new file mode 100644
index 000000000000..4c13e6117563
--- /dev/null
+++ b/arch/sh/include/asm/byteorder.h
@@ -0,0 +1,70 @@
+#ifndef __ASM_SH_BYTEORDER_H
+#define __ASM_SH_BYTEORDER_H
+
+/*
+ * Copyright (C) 1999  Niibe Yutaka
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ */
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+        __asm__(
+#ifdef __SH5__
+                "byterev        %0, %0\n\t"
+                "shari          %0, 32, %0"
+#else
+                "swap.b         %0, %0\n\t"
+                "swap.w         %0, %0\n\t"
+                "swap.b         %0, %0"
+#endif
+                : "=r" (x)
+                : "0" (x));
+
+        return x;
+}
+
+static inline __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+        __asm__(
+#ifdef __SH5__
+                "byterev        %0, %0\n\t"
+                "shari          %0, 32, %0"
+#else
+                "swap.b         %0, %0"
+#endif
+                : "=r" (x)
+                :  "0" (x));
+
+        return x;
+}
+
+static inline __u64 ___arch__swab64(__u64 val)
+{
+        union {
+                struct { __u32 a,b; } s;
+                __u64 u;
+        } v, w;
+        v.u = val;
+        w.s.b = ___arch__swab32(v.s.a);
+        w.s.a = ___arch__swab32(v.s.b);
+        return w.u;
+}
+
+#define __arch__swab64(x) ___arch__swab64(x)
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __LITTLE_ENDIAN__
+#include <linux/byteorder/little_endian.h>
+#else
+#include <linux/byteorder/big_endian.h>
+#endif
+
+#endif /* __ASM_SH_BYTEORDER_H */
diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h
new file mode 100644
index 000000000000..02df18ea9608
--- /dev/null
+++ b/arch/sh/include/asm/cache.h
@@ -0,0 +1,51 @@
+/* $Id: cache.h,v 1.6 2004/03/11 18:08:05 lethal Exp $
+ *
+ * include/asm-sh/cache.h
+ *
+ * Copyright 1999 (C) Niibe Yutaka
+ * Copyright 2002, 2003 (C) Paul Mundt
+ */
+#ifndef __ASM_SH_CACHE_H
+#define __ASM_SH_CACHE_H
+#ifdef __KERNEL__
+
+#include <linux/init.h>
+#include <cpu/cache.h>
+
+#define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
+
+#define __read_mostly __attribute__((__section__(".data.read_mostly")))
+
+#ifndef __ASSEMBLY__
+struct cache_info {
+        unsigned int ways;              /* Number of cache ways */
+        unsigned int sets;              /* Number of cache sets */
+        unsigned int linesz;            /* Cache line size (bytes) */
+
+        unsigned int way_size;          /* sets * line size */
+
+        /*
+         * way_incr is the address offset for accessing the next way
+         * in memory mapped cache array ops.
+         */
+        unsigned int way_incr;
+        unsigned int entry_shift;
+        unsigned int entry_mask;
+
+        /*
+         * Compute a mask which selects the address bits which overlap between
+         * 1. those used to select the cache set during indexing
+         * 2. those in the physical page number.
+         */
+        unsigned int alias_mask;
+
+        unsigned int n_aliases;         /* Number of aliases */
+
+        unsigned long flags;
+};
+
+int __init detect_cpu_and_cache_system(void);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_CACHE_H */
diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h
new file mode 100644
index 000000000000..09acbc32d6c7
--- /dev/null
+++ b/arch/sh/include/asm/cacheflush.h
@@ -0,0 +1,81 @@
+#ifndef __ASM_SH_CACHEFLUSH_H
+#define __ASM_SH_CACHEFLUSH_H
+
+#ifdef __KERNEL__
+
+#ifdef CONFIG_CACHE_OFF
+/*
+ * Nothing to do when the cache is disabled, initial flush and explicit
+ * disabling is handled at CPU init time.
+ *
+ * See arch/sh/kernel/cpu/init.c:cache_init().
+ */
+#define p3_cache_init()                         do { } while (0)
+#define flush_cache_all()                       do { } while (0)
+#define flush_cache_mm(mm)                      do { } while (0)
+#define flush_cache_dup_mm(mm)                  do { } while (0)
+#define flush_cache_range(vma, start, end)      do { } while (0)
+#define flush_cache_page(vma, vmaddr, pfn)      do { } while (0)
+#define flush_dcache_page(page)                 do { } while (0)
+#define flush_icache_range(start, end)          do { } while (0)
+#define flush_icache_page(vma,pg)               do { } while (0)
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+#define flush_cache_sigtramp(vaddr)             do { } while (0)
+#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
+#define __flush_wback_region(start, size)       do { (void)(start); } while (0)
+#define __flush_purge_region(start, size)       do { (void)(start); } while (0)
+#define __flush_invalidate_region(start, size)  do { (void)(start); } while (0)
+#else
+#include <cpu/cacheflush.h>
+
+/*
+ * Consistent DMA requires that the __flush_xxx() primitives must be set
+ * for any of the enabled non-coherent caches (most of the UP CPUs),
+ * regardless of PIPT or VIPT cache configurations.
+ */
+
+/* Flush (write-back only) a region (smaller than a page) */
+extern void __flush_wback_region(void *start, int size);
+/* Flush (write-back & invalidate) a region (smaller than a page) */
+extern void __flush_purge_region(void *start, int size);
+/* Flush (invalidate only) a region (smaller than a page) */
+extern void __flush_invalidate_region(void *start, int size);
+#endif
+
+#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
+static inline void flush_kernel_dcache_page(struct page *page)
+{
+        flush_dcache_page(page);
+}
+
+#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_CACHE_OFF)
+extern void copy_to_user_page(struct vm_area_struct *vma,
+        struct page *page, unsigned long vaddr, void *dst, const void *src,
+        unsigned long len);
+
+extern void copy_from_user_page(struct vm_area_struct *vma,
+        struct page *page, unsigned long vaddr, void *dst, const void *src,
+        unsigned long len);
+#else
+#define copy_to_user_page(vma, page, vaddr, dst, src, len)      \
+        do {                                                    \
+                flush_cache_page(vma, vaddr, page_to_pfn(page));\
+                memcpy(dst, src, len);                          \
+                flush_icache_user_range(vma, page, vaddr, len); \
+        } while (0)
+
+#define copy_from_user_page(vma, page, vaddr, dst, src, len)    \
+        do {                                                    \
+                flush_cache_page(vma, vaddr, page_to_pfn(page));\
+                memcpy(dst, src, len);                          \
+        } while (0)
+#endif
+
+#define flush_cache_vmap(start, end)            flush_cache_all()
+#define flush_cache_vunmap(start, end)          flush_cache_all()
+
+#define HAVE_ARCH_UNMAPPED_AREA
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_CACHEFLUSH_H */
diff --git a/arch/sh/include/asm/checksum.h b/arch/sh/include/asm/checksum.h
new file mode 100644
index 000000000000..67496ab0ef04
--- /dev/null
+++ b/arch/sh/include/asm/checksum.h
@@ -0,0 +1,5 @@
+#ifdef CONFIG_SUPERH32
+# include "checksum_32.h"
+#else
+# include "checksum_64.h"
+#endif
diff --git a/arch/sh/include/asm/checksum_32.h b/arch/sh/include/asm/checksum_32.h
new file mode 100644
index 000000000000..14b7ac2f0a07
--- /dev/null
+++ b/arch/sh/include/asm/checksum_32.h
@@ -0,0 +1,215 @@
+#ifndef __ASM_SH_CHECKSUM_H
+#define __ASM_SH_CHECKSUM_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 by Kaz Kojima & Niibe Yutaka
+ */
+
+#include <linux/in6.h>
+
+/*
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+asmlinkage __wsum csum_partial(const void *buff, int len, __wsum sum);
+
+/*
+ * the same as csum_partial, but copies from src while it
+ * checksums, and handles user-space pointer exceptions correctly, when needed.
+ *
+ * here even more important to align src and dst on a 32-bit (or even
+ * better 64-bit) boundary
+ */
+
+asmlinkage __wsum csum_partial_copy_generic(const void *src, void *dst,
+                                            int len, __wsum sum,
+                                            int *src_err_ptr, int *dst_err_ptr);
+
+/*
+ *      Note: when you get a NULL pointer exception here this means someone
+ *      passed in an incorrect kernel address to one of these functions.
+ *
+ *      If you use these functions directly please don't forget the
+ *      access_ok().
+ */
+static inline
+__wsum csum_partial_copy_nocheck(const void *src, void *dst,
+                                 int len, __wsum sum)
+{
+        return csum_partial_copy_generic(src, dst, len, sum, NULL, NULL);
+}
+
+static inline
+__wsum csum_partial_copy_from_user(const void __user *src, void *dst,
+                                   int len, __wsum sum, int *err_ptr)
+{
+        return csum_partial_copy_generic((__force const void *)src, dst,
+                                        len, sum, err_ptr, NULL);
+}
+
+/*
+ *      Fold a partial checksum
+ */
+
+static inline __sum16 csum_fold(__wsum sum)
+{
+        unsigned int __dummy;
+        __asm__("swap.w %0, %1\n\t"
+                "extu.w %0, %0\n\t"
+                "extu.w %1, %1\n\t"
+                "add    %1, %0\n\t"
+                "swap.w %0, %1\n\t"
+                "add    %1, %0\n\t"
+                "not    %0, %0\n\t"
+                : "=r" (sum), "=&r" (__dummy)
+                : "0" (sum)
+                : "t");
+        return (__force __sum16)sum;
+}
+
+/*
+ *      This is a version of ip_compute_csum() optimized for IP headers,
+ *      which always checksum on 4 octet boundaries.
+ *
+ *      i386 version by Jorge Cwik <jorge@laser.satlink.net>, adapted
+ *      for linux by * Arnt Gulbrandsen.
+ */
+static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
+{
+        unsigned int sum, __dummy0, __dummy1;
+
+        __asm__ __volatile__(
+                "mov.l  @%1+, %0\n\t"
+                "mov.l  @%1+, %3\n\t"
+                "add    #-2, %2\n\t"
+                "clrt\n\t"
+                "1:\t"
+                "addc   %3, %0\n\t"
+                "movt   %4\n\t"
+                "mov.l  @%1+, %3\n\t"
+                "dt     %2\n\t"
+                "bf/s   1b\n\t"
+                " cmp/eq #1, %4\n\t"
+                "addc   %3, %0\n\t"
+                "addc   %2, %0"     /* Here %2 is 0, add carry-bit */
+        /* Since the input registers which are loaded with iph and ihl
+           are modified, we must also specify them as outputs, or gcc
+           will assume they contain their original values. */
+        : "=r" (sum), "=r" (iph), "=r" (ihl), "=&r" (__dummy0), "=&z" (__dummy1)
+        : "1" (iph), "2" (ihl)
+        : "t", "memory");
+
+        return  csum_fold(sum);
+}
+
+static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
+                                        unsigned short len,
+                                        unsigned short proto,
+                                        __wsum sum)
+{
+#ifdef __LITTLE_ENDIAN__
+        unsigned long len_proto = (proto + len) << 8;
+#else
+        unsigned long len_proto = proto + len;
+#endif
+        __asm__("clrt\n\t"
+                "addc   %0, %1\n\t"
+                "addc   %2, %1\n\t"
+                "addc   %3, %1\n\t"
+                "movt   %0\n\t"
+                "add    %1, %0"
+                : "=r" (sum), "=r" (len_proto)
+                : "r" (daddr), "r" (saddr), "1" (len_proto), "0" (sum)
+                : "t");
+
+        return sum;
+}
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
+                                        unsigned short len,
+                                        unsigned short proto,
+                                        __wsum sum)
+{
+        return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
+}
+
+/*
+ * this routine is used for miscellaneous IP-like checksums, mainly
+ * in icmp.c
+ */
+static inline __sum16 ip_compute_csum(const void *buff, int len)
+{
+    return csum_fold(csum_partial(buff, len, 0));
+}
+
+#define _HAVE_ARCH_IPV6_CSUM
+static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
+                                      const struct in6_addr *daddr,
+                                      __u32 len, unsigned short proto,
+                                      __wsum sum)
+{
+        unsigned int __dummy;
+        __asm__("clrt\n\t"
+                "mov.l  @(0,%2), %1\n\t"
+                "addc   %1, %0\n\t"
+                "mov.l  @(4,%2), %1\n\t"
+                "addc   %1, %0\n\t"
+                "mov.l  @(8,%2), %1\n\t"
+                "addc   %1, %0\n\t"
+                "mov.l  @(12,%2), %1\n\t"
+                "addc   %1, %0\n\t"
+                "mov.l  @(0,%3), %1\n\t"
+                "addc   %1, %0\n\t"
+                "mov.l  @(4,%3), %1\n\t"
+                "addc   %1, %0\n\t"
+                "mov.l  @(8,%3), %1\n\t"
+                "addc   %1, %0\n\t"
+                "mov.l  @(12,%3), %1\n\t"
+                "addc   %1, %0\n\t"
+                "addc   %4, %0\n\t"
+                "addc   %5, %0\n\t"
+                "movt   %1\n\t"
+                "add    %1, %0\n"
+                : "=r" (sum), "=&r" (__dummy)
+                : "r" (saddr), "r" (daddr),
+                  "r" (htonl(len)), "r" (htonl(proto)), "0" (sum)
+                : "t");
+
+        return csum_fold(sum);
+}
+
+/*
+ *      Copy and checksum to user
+ */
+#define HAVE_CSUM_COPY_USER
+static inline __wsum csum_and_copy_to_user(const void *src,
+                                           void __user *dst,
+                                           int len, __wsum sum,
+                                           int *err_ptr)
+{
+        if (access_ok(VERIFY_WRITE, dst, len))
+                return csum_partial_copy_generic((__force const void *)src,
+                                                dst, len, sum, NULL, err_ptr);
+
+        if (len)
+                *err_ptr = -EFAULT;
+
+        return (__force __wsum)-1; /* invalid checksum */
+}
+#endif /* __ASM_SH_CHECKSUM_H */
diff --git a/arch/sh/include/asm/checksum_64.h b/arch/sh/include/asm/checksum_64.h
new file mode 100644
index 000000000000..9c62a031a8f5
--- /dev/null
+++ b/arch/sh/include/asm/checksum_64.h
@@ -0,0 +1,78 @@
+#ifndef __ASM_SH_CHECKSUM_64_H
+#define __ASM_SH_CHECKSUM_64_H
+
+/*
+ * include/asm-sh/checksum_64.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+/*
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+asmlinkage __wsum csum_partial(const void *buff, int len, __wsum sum);
+
+/*
+ *      Note: when you get a NULL pointer exception here this means someone
+ *      passed in an incorrect kernel address to one of these functions.
+ *
+ *      If you use these functions directly please don't forget the
+ *      access_ok().
+ */
+
+
+__wsum csum_partial_copy_nocheck(const void *src, void *dst, int len,
+                                       __wsum sum);
+
+__wsum csum_partial_copy_from_user(const void __user *src, void *dst,
+                                         int len, __wsum sum, int *err_ptr);
+
+static inline __sum16 csum_fold(__wsum csum)
+{
+        u32 sum = (__force u32)csum;
+        sum = (sum & 0xffff) + (sum >> 16);
+        sum = (sum & 0xffff) + (sum >> 16);
+        return (__force __sum16)~sum;
+}
+
+__sum16 ip_fast_csum(const void *iph, unsigned int ihl);
+
+__wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
+                                 unsigned short len, unsigned short proto,
+                                 __wsum sum);
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
+                                                   unsigned short len,
+                                                   unsigned short proto,
+                                                   __wsum sum)
+{
+        return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
+}
+
+/*
+ * this routine is used for miscellaneous IP-like checksums, mainly
+ * in icmp.c
+ */
+static inline __sum16 ip_compute_csum(const void *buff, int len)
+{
+        return csum_fold(csum_partial(buff, len, 0));
+}
+
+#endif /* __ASM_SH_CHECKSUM_64_H */
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
new file mode 100644
index 000000000000..720dfab7b15e
--- /dev/null
+++ b/arch/sh/include/asm/clock.h
@@ -0,0 +1,97 @@
+#ifndef __ASM_SH_CLOCK_H
+#define __ASM_SH_CLOCK_H
+
+#include <linux/kref.h>
+#include <linux/list.h>
+#include <linux/seq_file.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+struct clk;
+
+struct clk_ops {
+        void (*init)(struct clk *clk);
+        void (*enable)(struct clk *clk);
+        void (*disable)(struct clk *clk);
+        void (*recalc)(struct clk *clk);
+        int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
+        long (*round_rate)(struct clk *clk, unsigned long rate);
+};
+
+struct clk {
+        struct list_head        node;
+        const char              *name;
+        int                     id;
+        struct module           *owner;
+
+        struct clk              *parent;
+        struct clk_ops          *ops;
+
+        struct kref             kref;
+
+        unsigned long           rate;
+        unsigned long           flags;
+        unsigned long           arch_flags;
+};
+
+#define CLK_ALWAYS_ENABLED      (1 << 0)
+#define CLK_RATE_PROPAGATES     (1 << 1)
+
+/* Should be defined by processor-specific code */
+void arch_init_clk_ops(struct clk_ops **, int type);
+
+/* arch/sh/kernel/cpu/clock.c */
+int clk_init(void);
+
+void clk_recalc_rate(struct clk *);
+
+int clk_register(struct clk *);
+void clk_unregister(struct clk *);
+
+static inline int clk_always_enable(const char *id)
+{
+        struct clk *clk;
+        int ret;
+
+        clk = clk_get(NULL, id);
+        if (IS_ERR(clk))
+                return PTR_ERR(clk);
+
+        ret = clk_enable(clk);
+        if (ret)
+                clk_put(clk);
+
+        return ret;
+}
+
+/* the exported API, in addition to clk_set_rate */
+/**
+ * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
+ * @clk: clock source
+ * @rate: desired clock rate in Hz
+ * @algo_id: algorithm id to be passed down to ops->set_rate
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
+
+enum clk_sh_algo_id {
+        NO_CHANGE = 0,
+
+        IUS_N1_N1,
+        IUS_322,
+        IUS_522,
+        IUS_N11,
+
+        SB_N1,
+
+        SB3_N1,
+        SB3_32,
+        SB3_43,
+        SB3_54,
+
+        BP_N1,
+
+        IP_N1,
+};
+#endif /* __ASM_SH_CLOCK_H */
diff --git a/arch/sh/include/asm/cmpxchg-grb.h b/arch/sh/include/asm/cmpxchg-grb.h
new file mode 100644
index 000000000000..e2681abe764f
--- /dev/null
+++ b/arch/sh/include/asm/cmpxchg-grb.h
@@ -0,0 +1,70 @@
+#ifndef __ASM_SH_CMPXCHG_GRB_H
+#define __ASM_SH_CMPXCHG_GRB_H
+
+static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
+{
+        unsigned long retval;
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   nop                   \n\t"
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-4,   r15     \n\t" /* LOGIN */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   mov.l   %2,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (retval),
+                  "+r"  (m)
+                : "r"   (val)
+                : "memory", "r0", "r1");
+
+        return retval;
+}
+
+static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
+{
+        unsigned long retval;
+
+        __asm__ __volatile__ (
+                "   .align  2             \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN */
+                "   mov.b  @%1,   %0      \n\t" /* load  old value */
+                "   extu.b  %0,   %0      \n\t" /* extend as unsigned */
+                "   mov.b   %2,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (retval),
+                  "+r"  (m)
+                : "r"   (val)
+                : "memory" , "r0", "r1");
+
+        return retval;
+}
+
+static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old,
+                                          unsigned long new)
+{
+        unsigned long retval;
+
+        __asm__ __volatile__ (
+                "   .align  2             \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   nop                   \n\t"
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-8,   r15     \n\t" /* LOGIN */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   cmp/eq  %0,   %2      \n\t"
+                "   bf            1f      \n\t" /* if not equal */
+                "   mov.l   %2,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (retval),
+                  "+r"  (m)
+                : "r"   (new)
+                : "memory" , "r0", "r1", "t");
+
+        return retval;
+}
+
+#endif /* __ASM_SH_CMPXCHG_GRB_H */
diff --git a/arch/sh/include/asm/cmpxchg-irq.h b/arch/sh/include/asm/cmpxchg-irq.h
new file mode 100644
index 000000000000..43049ec0554b
--- /dev/null
+++ b/arch/sh/include/asm/cmpxchg-irq.h
@@ -0,0 +1,40 @@
+#ifndef __ASM_SH_CMPXCHG_IRQ_H
+#define __ASM_SH_CMPXCHG_IRQ_H
+
+static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
+{
+        unsigned long flags, retval;
+
+        local_irq_save(flags);
+        retval = *m;
+        *m = val;
+        local_irq_restore(flags);
+        return retval;
+}
+
+static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
+{
+        unsigned long flags, retval;
+
+        local_irq_save(flags);
+        retval = *m;
+        *m = val & 0xff;
+        local_irq_restore(flags);
+        return retval;
+}
+
+static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old,
+        unsigned long new)
+{
+        __u32 retval;
+        unsigned long flags;
+
+        local_irq_save(flags);
+        retval = *m;
+        if (retval == old)
+                *m = new;
+        local_irq_restore(flags);       /* implies memory barrier  */
+        return retval;
+}
+
+#endif /* __ASM_SH_CMPXCHG_IRQ_H */
diff --git a/arch/sh/include/asm/cpu-features.h b/arch/sh/include/asm/cpu-features.h
new file mode 100644
index 000000000000..86308aa39731
--- /dev/null
+++ b/arch/sh/include/asm/cpu-features.h
@@ -0,0 +1,25 @@
+#ifndef __ASM_SH_CPU_FEATURES_H
+#define __ASM_SH_CPU_FEATURES_H
+
+/*
+ * Processor flags
+ *
+ * Note: When adding a new flag, keep cpu_flags[] in
+ * arch/sh/kernel/setup.c in sync so symbolic name
+ * mapping of the processor flags has a chance of being
+ * reasonably accurate.
+ *
+ * These flags are also available through the ELF
+ * auxiliary vector as AT_HWCAP.
+ */
+#define CPU_HAS_FPU             0x0001  /* Hardware FPU support */
+#define CPU_HAS_P2_FLUSH_BUG    0x0002  /* Need to flush the cache in P2 area */
+#define CPU_HAS_MMU_PAGE_ASSOC  0x0004  /* SH3: TLB way selection bit support */
+#define CPU_HAS_DSP             0x0008  /* SH-DSP: DSP support */
+#define CPU_HAS_PERF_COUNTER    0x0010  /* Hardware performance counters */
+#define CPU_HAS_PTEA            0x0020  /* PTEA register */
+#define CPU_HAS_LLSC            0x0040  /* movli.l/movco.l */
+#define CPU_HAS_L2_CACHE        0x0080  /* Secondary cache / URAM */
+#define CPU_HAS_OP32            0x0100  /* 32-bit instruction support */
+
+#endif /* __ASM_SH_CPU_FEATURES_H */
diff --git a/arch/sh/include/asm/cputime.h b/arch/sh/include/asm/cputime.h
new file mode 100644
index 000000000000..6ca395d1393e
--- /dev/null
+++ b/arch/sh/include/asm/cputime.h
@@ -0,0 +1,6 @@
+#ifndef __SH_CPUTIME_H
+#define __SH_CPUTIME_H
+
+#include <asm-generic/cputime.h>
+
+#endif /* __SH_CPUTIME_H */
diff --git a/arch/sh/include/asm/current.h b/arch/sh/include/asm/current.h
new file mode 100644
index 000000000000..62b63880b333
--- /dev/null
+++ b/arch/sh/include/asm/current.h
@@ -0,0 +1,20 @@
+#ifndef __ASM_SH_CURRENT_H
+#define __ASM_SH_CURRENT_H
+
+/*
+ * Copyright (C) 1999 Niibe Yutaka
+ *
+ */
+
+#include <linux/thread_info.h>
+
+struct task_struct;
+
+static __inline__ struct task_struct * get_current(void)
+{
+        return current_thread_info()->task;
+}
+
+#define current get_current()
+
+#endif /* __ASM_SH_CURRENT_H */
diff --git a/arch/sh/include/asm/delay.h b/arch/sh/include/asm/delay.h
new file mode 100644
index 000000000000..4b16bf9b56bd
--- /dev/null
+++ b/arch/sh/include/asm/delay.h
@@ -0,0 +1,26 @@
+#ifndef __ASM_SH_DELAY_H
+#define __ASM_SH_DELAY_H
+
+/*
+ * Copyright (C) 1993 Linus Torvalds
+ *
+ * Delay routines calling functions in arch/sh/lib/delay.c
+ */
+
+extern void __bad_udelay(void);
+extern void __bad_ndelay(void);
+
+extern void __udelay(unsigned long usecs);
+extern void __ndelay(unsigned long nsecs);
+extern void __const_udelay(unsigned long xloops);
+extern void __delay(unsigned long loops);
+
+#define udelay(n) (__builtin_constant_p(n) ? \
+        ((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 0x10c6ul)) : \
+        __udelay(n))
+
+#define ndelay(n) (__builtin_constant_p(n) ? \
+        ((n) > 20000 ? __bad_ndelay() : __const_udelay((n) * 5ul)) : \
+        __ndelay(n))
+
+#endif /* __ASM_SH_DELAY_H */
diff --git a/arch/sh/include/asm/device.h b/arch/sh/include/asm/device.h
new file mode 100644
index 000000000000..efd511d0803a
--- /dev/null
+++ b/arch/sh/include/asm/device.h
@@ -0,0 +1,12 @@
+/*
+ * Arch specific extensions to struct device
+ *
+ * This file is released under the GPLv2
+ */
+#include <asm-generic/device.h>
+
+struct platform_device;
+/* allocate contiguous memory chunk and fill in struct resource */
+int platform_resource_setup_memory(struct platform_device *pdev,
+                                   char *name, unsigned long memsize);
+
diff --git a/arch/sh/include/asm/div64.h b/arch/sh/include/asm/div64.h
new file mode 100644
index 000000000000..6cd978cefb28
--- /dev/null
+++ b/arch/sh/include/asm/div64.h
@@ -0,0 +1 @@
+#include <asm-generic/div64.h>
diff --git a/arch/sh/include/asm/dma-mapping.h b/arch/sh/include/asm/dma-mapping.h
new file mode 100644
index 000000000000..627315ecdb52
--- /dev/null
+++ b/arch/sh/include/asm/dma-mapping.h
@@ -0,0 +1,193 @@
+#ifndef __ASM_SH_DMA_MAPPING_H
+#define __ASM_SH_DMA_MAPPING_H
+
+#include <linux/mm.h>
+#include <linux/scatterlist.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm-generic/dma-coherent.h>
+
+extern struct bus_type pci_bus_type;
+
+#define dma_supported(dev, mask)        (1)
+
+static inline int dma_set_mask(struct device *dev, u64 mask)
+{
+        if (!dev->dma_mask || !dma_supported(dev, mask))
+                return -EIO;
+
+        *dev->dma_mask = mask;
+
+        return 0;
+}
+
+void *dma_alloc_coherent(struct device *dev, size_t size,
+                         dma_addr_t *dma_handle, gfp_t flag);
+
+void dma_free_coherent(struct device *dev, size_t size,
+                       void *vaddr, dma_addr_t dma_handle);
+
+void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+                    enum dma_data_direction dir);
+
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+#define dma_is_consistent(d, h) (1)
+
+static inline dma_addr_t dma_map_single(struct device *dev,
+                                        void *ptr, size_t size,
+                                        enum dma_data_direction dir)
+{
+#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
+        if (dev->bus == &pci_bus_type)
+                return virt_to_phys(ptr);
+#endif
+        dma_cache_sync(dev, ptr, size, dir);
+
+        return virt_to_phys(ptr);
+}
+
+#define dma_unmap_single(dev, addr, size, dir)  do { } while (0)
+
+static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
+                             int nents, enum dma_data_direction dir)
+{
+        int i;
+
+        for (i = 0; i < nents; i++) {
+#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
+                dma_cache_sync(dev, sg_virt(&sg[i]), sg[i].length, dir);
+#endif
+                sg[i].dma_address = sg_phys(&sg[i]);
+        }
+
+        return nents;
+}
+
+#define dma_unmap_sg(dev, sg, nents, dir)       do { } while (0)
+
+static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
+                                      unsigned long offset, size_t size,
+                                      enum dma_data_direction dir)
+{
+        return dma_map_single(dev, page_address(page) + offset, size, dir);
+}
+
+static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
+                                  size_t size, enum dma_data_direction dir)
+{
+        dma_unmap_single(dev, dma_address, size, dir);
+}
+
+static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle,
+                                   size_t size, enum dma_data_direction dir)
+{
+#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
+        if (dev->bus == &pci_bus_type)
+                return;
+#endif
+        dma_cache_sync(dev, phys_to_virt(dma_handle), size, dir);
+}
+
+static inline void dma_sync_single_range(struct device *dev,
+                                         dma_addr_t dma_handle,
+                                         unsigned long offset, size_t size,
+                                         enum dma_data_direction dir)
+{
+#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
+        if (dev->bus == &pci_bus_type)
+                return;
+#endif
+        dma_cache_sync(dev, phys_to_virt(dma_handle) + offset, size, dir);
+}
+
+static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg,
+                               int nelems, enum dma_data_direction dir)
+{
+        int i;
+
+        for (i = 0; i < nelems; i++) {
+#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
+                dma_cache_sync(dev, sg_virt(&sg[i]), sg[i].length, dir);
+#endif
+                sg[i].dma_address = sg_phys(&sg[i]);
+        }
+}
+
+static inline void dma_sync_single_for_cpu(struct device *dev,
+                                           dma_addr_t dma_handle, size_t size,
+                                           enum dma_data_direction dir)
+{
+        dma_sync_single(dev, dma_handle, size, dir);
+}
+
+static inline void dma_sync_single_for_device(struct device *dev,
+                                              dma_addr_t dma_handle,
+                                              size_t size,
+                                              enum dma_data_direction dir)
+{
+        dma_sync_single(dev, dma_handle, size, dir);
+}
+
+static inline void dma_sync_single_range_for_cpu(struct device *dev,
+                                                 dma_addr_t dma_handle,
+                                                 unsigned long offset,
+                                                 size_t size,
+                                                 enum dma_data_direction direction)
+{
+        dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
+}
+
+static inline void dma_sync_single_range_for_device(struct device *dev,
+                                                    dma_addr_t dma_handle,
+                                                    unsigned long offset,
+                                                    size_t size,
+                                                    enum dma_data_direction direction)
+{
+        dma_sync_single_for_device(dev, dma_handle+offset, size, direction);
+}
+
+
+static inline void dma_sync_sg_for_cpu(struct device *dev,
+                                       struct scatterlist *sg, int nelems,
+                                       enum dma_data_direction dir)
+{
+        dma_sync_sg(dev, sg, nelems, dir);
+}
+
+static inline void dma_sync_sg_for_device(struct device *dev,
+                                          struct scatterlist *sg, int nelems,
+                                          enum dma_data_direction dir)
+{
+        dma_sync_sg(dev, sg, nelems, dir);
+}
+
+
+static inline int dma_get_cache_alignment(void)
+{
+        /*
+         * Each processor family will define its own L1_CACHE_SHIFT,
+         * L1_CACHE_BYTES wraps to this, so this is always safe.
+         */
+        return L1_CACHE_BYTES;
+}
+
+static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+{
+        return dma_addr == 0;
+}
+
+#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
+
+extern int
+dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
+                            dma_addr_t device_addr, size_t size, int flags);
+
+extern void
+dma_release_declared_memory(struct device *dev);
+
+extern void *
+dma_mark_declared_memory_occupied(struct device *dev,
+                                  dma_addr_t device_addr, size_t size);
+
+#endif /* __ASM_SH_DMA_MAPPING_H */
diff --git a/arch/sh/include/asm/dma.h b/arch/sh/include/asm/dma.h
new file mode 100644
index 000000000000..beca7128e2ab
--- /dev/null
+++ b/arch/sh/include/asm/dma.h
@@ -0,0 +1,166 @@
+/*
+ * include/asm-sh/dma.h
+ *
+ * Copyright (C) 2003, 2004  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_DMA_H
+#define __ASM_SH_DMA_H
+#ifdef __KERNEL__
+
+#include <linux/spinlock.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
+#include <linux/sysdev.h>
+#include <cpu/dma.h>
+
+/* The maximum address that we can perform a DMA transfer to on this platform */
+/* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any
+   occurrence should be flagged as an error.  */
+/* But... */
+/* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */
+#define MAX_DMA_ADDRESS         (PAGE_OFFSET+0x10000000)
+
+#ifdef CONFIG_NR_DMA_CHANNELS
+#  define MAX_DMA_CHANNELS      (CONFIG_NR_DMA_CHANNELS)
+#else
+#  define MAX_DMA_CHANNELS      (CONFIG_NR_ONCHIP_DMA_CHANNELS)
+#endif
+
+/*
+ * Read and write modes can mean drastically different things depending on the
+ * channel configuration. Consult your DMAC documentation and module
+ * implementation for further clues.
+ */
+#define DMA_MODE_READ           0x00
+#define DMA_MODE_WRITE          0x01
+#define DMA_MODE_MASK           0x01
+
+#define DMA_AUTOINIT            0x10
+
+/*
+ * DMAC (dma_info) flags
+ */
+enum {
+        DMAC_CHANNELS_CONFIGURED        = 0x01,
+        DMAC_CHANNELS_TEI_CAPABLE       = 0x02, /* Transfer end interrupt */
+};
+
+/*
+ * DMA channel capabilities / flags
+ */
+enum {
+        DMA_CONFIGURED                  = 0x01,
+
+        /*
+         * Transfer end interrupt, inherited from DMAC.
+         * wait_queue used in dma_wait_for_completion.
+         */
+        DMA_TEI_CAPABLE                 = 0x02,
+};
+
+extern spinlock_t dma_spin_lock;
+
+struct dma_channel;
+
+struct dma_ops {
+        int (*request)(struct dma_channel *chan);
+        void (*free)(struct dma_channel *chan);
+
+        int (*get_residue)(struct dma_channel *chan);
+        int (*xfer)(struct dma_channel *chan);
+        int (*configure)(struct dma_channel *chan, unsigned long flags);
+        int (*extend)(struct dma_channel *chan, unsigned long op, void *param);
+};
+
+struct dma_channel {
+        char dev_id[16];                /* unique name per DMAC of channel */
+
+        unsigned int chan;              /* DMAC channel number */
+        unsigned int vchan;             /* Virtual channel number */
+
+        unsigned int mode;
+        unsigned int count;
+
+        unsigned long sar;
+        unsigned long dar;
+
+        const char **caps;
+
+        unsigned long flags;
+        atomic_t busy;
+
+        wait_queue_head_t wait_queue;
+
+        struct sys_device dev;
+        void *priv_data;
+};
+
+struct dma_info {
+        struct platform_device *pdev;
+
+        const char *name;
+        unsigned int nr_channels;
+        unsigned long flags;
+
+        struct dma_ops *ops;
+        struct dma_channel *channels;
+
+        struct list_head list;
+        int first_channel_nr;
+        int first_vchannel_nr;
+};
+
+struct dma_chan_caps {
+        int ch_num;
+        const char **caplist;
+};
+
+#define to_dma_channel(channel) container_of(channel, struct dma_channel, dev)
+
+/* arch/sh/drivers/dma/dma-api.c */
+extern int dma_xfer(unsigned int chan, unsigned long from,
+                    unsigned long to, size_t size, unsigned int mode);
+
+#define dma_write(chan, from, to, size) \
+        dma_xfer(chan, from, to, size, DMA_MODE_WRITE)
+#define dma_write_page(chan, from, to)  \
+        dma_write(chan, from, to, PAGE_SIZE)
+
+#define dma_read(chan, from, to, size)  \
+        dma_xfer(chan, from, to, size, DMA_MODE_READ)
+#define dma_read_page(chan, from, to)   \
+        dma_read(chan, from, to, PAGE_SIZE)
+
+extern int request_dma_bycap(const char **dmac, const char **caps,
+                             const char *dev_id);
+extern int request_dma(unsigned int chan, const char *dev_id);
+extern void free_dma(unsigned int chan);
+extern int get_dma_residue(unsigned int chan);
+extern struct dma_info *get_dma_info(unsigned int chan);
+extern struct dma_channel *get_dma_channel(unsigned int chan);
+extern void dma_wait_for_completion(unsigned int chan);
+extern void dma_configure_channel(unsigned int chan, unsigned long flags);
+
+extern int register_dmac(struct dma_info *info);
+extern void unregister_dmac(struct dma_info *info);
+extern struct dma_info *get_dma_info_by_name(const char *dmac_name);
+
+extern int dma_extend(unsigned int chan, unsigned long op, void *param);
+extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist);
+
+/* arch/sh/drivers/dma/dma-sysfs.c */
+extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *);
+extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *);
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy    (0)
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_DMA_H */
diff --git a/arch/sh/include/asm/dmabrg.h b/arch/sh/include/asm/dmabrg.h
new file mode 100644
index 000000000000..c5edba216cf1
--- /dev/null
+++ b/arch/sh/include/asm/dmabrg.h
@@ -0,0 +1,23 @@
+/*
+ * SH7760 DMABRG (USB/Audio) support
+ */
+
+#ifndef _DMABRG_H_
+#define _DMABRG_H_
+
+/* IRQ sources */
+#define DMABRGIRQ_USBDMA        0
+#define DMABRGIRQ_USBDMAERR     1
+#define DMABRGIRQ_A0TXF         2
+#define DMABRGIRQ_A0TXH         3
+#define DMABRGIRQ_A0RXF         4
+#define DMABRGIRQ_A0RXH         5
+#define DMABRGIRQ_A1TXF         6
+#define DMABRGIRQ_A1TXH         7
+#define DMABRGIRQ_A1RXF         8
+#define DMABRGIRQ_A1RXH         9
+
+extern int dmabrg_request_irq(unsigned int, void(*)(void *), void *);
+extern void dmabrg_free_irq(unsigned int);
+
+#endif
diff --git a/arch/sh/include/asm/edosk7705.h b/arch/sh/include/asm/edosk7705.h
new file mode 100644
index 000000000000..5bdc9d9be3de
--- /dev/null
+++ b/arch/sh/include/asm/edosk7705.h
@@ -0,0 +1,30 @@
+/*
+ * include/asm-sh/edosk7705.h
+ *
+ * Modified version of io_se.h for the EDOSK7705 specific functions.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * IO functions for an Hitachi EDOSK7705 development board
+ */
+
+#ifndef __ASM_SH_EDOSK7705_IO_H
+#define __ASM_SH_EDOSK7705_IO_H
+
+#include <asm/io_generic.h>
+
+extern unsigned char sh_edosk7705_inb(unsigned long port);
+extern unsigned int sh_edosk7705_inl(unsigned long port);
+
+extern void sh_edosk7705_outb(unsigned char value, unsigned long port);
+extern void sh_edosk7705_outl(unsigned int value, unsigned long port);
+
+extern void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count);
+extern void sh_edosk7705_insl(unsigned long port, void *addr, unsigned long count);
+extern void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count);
+extern void sh_edosk7705_outsl(unsigned long port, const void *addr, unsigned long count);
+
+extern unsigned long sh_edosk7705_isa_port2addr(unsigned long offset);
+
+#endif /* __ASM_SH_EDOSK7705_IO_H */
diff --git a/arch/sh/include/asm/elf.h b/arch/sh/include/asm/elf.h
new file mode 100644
index 000000000000..f01449a8d378
--- /dev/null
+++ b/arch/sh/include/asm/elf.h
@@ -0,0 +1,244 @@
+#ifndef __ASM_SH_ELF_H
+#define __ASM_SH_ELF_H
+
+#include <linux/utsname.h>
+#include <asm/auxvec.h>
+#include <asm/ptrace.h>
+#include <asm/user.h>
+
+/* ELF header e_flags defines */
+#define EF_SH_PIC               0x100   /* -fpic */
+#define EF_SH_FDPIC             0x8000  /* -mfdpic */
+
+/* SH (particularly SHcompact) relocation types  */
+#define R_SH_NONE               0
+#define R_SH_DIR32              1
+#define R_SH_REL32              2
+#define R_SH_DIR8WPN            3
+#define R_SH_IND12W             4
+#define R_SH_DIR8WPL            5
+#define R_SH_DIR8WPZ            6
+#define R_SH_DIR8BP             7
+#define R_SH_DIR8W              8
+#define R_SH_DIR8L              9
+#define R_SH_SWITCH16           25
+#define R_SH_SWITCH32           26
+#define R_SH_USES               27
+#define R_SH_COUNT              28
+#define R_SH_ALIGN              29
+#define R_SH_CODE               30
+#define R_SH_DATA               31
+#define R_SH_LABEL              32
+#define R_SH_SWITCH8            33
+#define R_SH_GNU_VTINHERIT      34
+#define R_SH_GNU_VTENTRY        35
+#define R_SH_TLS_GD_32          144
+#define R_SH_TLS_LD_32          145
+#define R_SH_TLS_LDO_32         146
+#define R_SH_TLS_IE_32          147
+#define R_SH_TLS_LE_32          148
+#define R_SH_TLS_DTPMOD32       149
+#define R_SH_TLS_DTPOFF32       150
+#define R_SH_TLS_TPOFF32        151
+#define R_SH_GOT32              160
+#define R_SH_PLT32              161
+#define R_SH_COPY               162
+#define R_SH_GLOB_DAT           163
+#define R_SH_JMP_SLOT           164
+#define R_SH_RELATIVE           165
+#define R_SH_GOTOFF             166
+#define R_SH_GOTPC              167
+
+/* FDPIC relocs */
+#define R_SH_GOT20              70
+#define R_SH_GOTOFF20           71
+#define R_SH_GOTFUNCDESC        72
+#define R_SH_GOTFUNCDESC20      73
+#define R_SH_GOTOFFFUNCDESC     74
+#define R_SH_GOTOFFFUNCDESC20   75
+#define R_SH_FUNCDESC           76
+#define R_SH_FUNCDESC_VALUE     77
+
+#if 0 /* XXX - later .. */
+#define R_SH_GOT20              198
+#define R_SH_GOTOFF20           199
+#define R_SH_GOTFUNCDESC        200
+#define R_SH_GOTFUNCDESC20      201
+#define R_SH_GOTOFFFUNCDESC     202
+#define R_SH_GOTOFFFUNCDESC20   203
+#define R_SH_FUNCDESC           204
+#define R_SH_FUNCDESC_VALUE     205
+#endif
+
+/* SHmedia relocs */
+#define R_SH_IMM_LOW16          246
+#define R_SH_IMM_LOW16_PCREL    247
+#define R_SH_IMM_MEDLOW16       248
+#define R_SH_IMM_MEDLOW16_PCREL 249
+/* Keep this the last entry.  */
+#define R_SH_NUM                256
+
+/*
+ * ELF register definitions..
+ */
+
+typedef unsigned long elf_greg_t;
+
+#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef struct user_fpu_struct elf_fpregset_t;
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS       ELFCLASS32
+#ifdef __LITTLE_ENDIAN__
+#define ELF_DATA        ELFDATA2LSB
+#else
+#define ELF_DATA        ELFDATA2MSB
+#endif
+#define ELF_ARCH        EM_SH
+
+#ifdef __KERNEL__
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x)               ((x)->e_machine == EM_SH)
+#define elf_check_fdpic(x)              ((x)->e_flags & EF_SH_FDPIC)
+#define elf_check_const_displacement(x) ((x)->e_flags & EF_SH_PIC)
+
+#define USE_ELF_CORE_DUMP
+#define ELF_FDPIC_CORE_EFLAGS   EF_SH_FDPIC
+#define ELF_EXEC_PAGESIZE       PAGE_SIZE
+
+/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+   use of this is to invoke "./ld.so someprog" to test out a new version of
+   the loader.  We need to make sure that it is out of the way of the program
+   that it will "exec", and that there is sufficient room for the brk.  */
+
+#define ELF_ET_DYN_BASE         (2 * TASK_SIZE / 3)
+
+#define ELF_CORE_COPY_REGS(_dest,_regs)                         \
+        memcpy((char *) &_dest, (char *) _regs,                 \
+               sizeof(struct pt_regs));
+
+/* This yields a mask that user programs can use to figure out what
+   instruction set this CPU supports.  This could be done in user space,
+   but it's not easy, and we've already done it here.  */
+
+#define ELF_HWCAP       (boot_cpu_data.flags)
+
+/* This yields a string that ld.so will use to load implementation
+   specific libraries for optimization.  This is more specific in
+   intent than poking at uname or /proc/cpuinfo.
+
+   For the moment, we have only optimizations for the Intel generations,
+   but that could change... */
+
+#define ELF_PLATFORM    (utsname()->machine)
+
+#ifdef __SH5__
+#define ELF_PLAT_INIT(_r, load_addr) \
+  do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \
+       _r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \
+       _r->regs[8]=0; _r->regs[9]=0; _r->regs[10]=0; _r->regs[11]=0; \
+       _r->regs[12]=0; _r->regs[13]=0; _r->regs[14]=0; _r->regs[15]=0; \
+       _r->regs[16]=0; _r->regs[17]=0; _r->regs[18]=0; _r->regs[19]=0; \
+       _r->regs[20]=0; _r->regs[21]=0; _r->regs[22]=0; _r->regs[23]=0; \
+       _r->regs[24]=0; _r->regs[25]=0; _r->regs[26]=0; _r->regs[27]=0; \
+       _r->regs[28]=0; _r->regs[29]=0; _r->regs[30]=0; _r->regs[31]=0; \
+       _r->regs[32]=0; _r->regs[33]=0; _r->regs[34]=0; _r->regs[35]=0; \
+       _r->regs[36]=0; _r->regs[37]=0; _r->regs[38]=0; _r->regs[39]=0; \
+       _r->regs[40]=0; _r->regs[41]=0; _r->regs[42]=0; _r->regs[43]=0; \
+       _r->regs[44]=0; _r->regs[45]=0; _r->regs[46]=0; _r->regs[47]=0; \
+       _r->regs[48]=0; _r->regs[49]=0; _r->regs[50]=0; _r->regs[51]=0; \
+       _r->regs[52]=0; _r->regs[53]=0; _r->regs[54]=0; _r->regs[55]=0; \
+       _r->regs[56]=0; _r->regs[57]=0; _r->regs[58]=0; _r->regs[59]=0; \
+       _r->regs[60]=0; _r->regs[61]=0; _r->regs[62]=0; \
+       _r->tregs[0]=0; _r->tregs[1]=0; _r->tregs[2]=0; _r->tregs[3]=0; \
+       _r->tregs[4]=0; _r->tregs[5]=0; _r->tregs[6]=0; _r->tregs[7]=0; \
+       _r->sr = SR_FD | SR_MMU; } while (0)
+#else
+#define ELF_PLAT_INIT(_r, load_addr) \
+  do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \
+       _r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \
+       _r->regs[8]=0; _r->regs[9]=0; _r->regs[10]=0; _r->regs[11]=0; \
+       _r->regs[12]=0; _r->regs[13]=0; _r->regs[14]=0; \
+       _r->sr = SR_FD; } while (0)
+
+#define ELF_FDPIC_PLAT_INIT(_r, _exec_map_addr, _interp_map_addr,       \
+                            _dynamic_addr)                              \
+do {                                                                    \
+        _r->regs[0]     = 0;                                            \
+        _r->regs[1]     = 0;                                            \
+        _r->regs[2]     = 0;                                            \
+        _r->regs[3]     = 0;                                            \
+        _r->regs[4]     = 0;                                            \
+        _r->regs[5]     = 0;                                            \
+        _r->regs[6]     = 0;                                            \
+        _r->regs[7]     = 0;                                            \
+        _r->regs[8]     = _exec_map_addr;                               \
+        _r->regs[9]     = _interp_map_addr;                             \
+        _r->regs[10]    = _dynamic_addr;                                \
+        _r->regs[11]    = 0;                                            \
+        _r->regs[12]    = 0;                                            \
+        _r->regs[13]    = 0;                                            \
+        _r->regs[14]    = 0;                                            \
+        _r->sr          = SR_FD;                                        \
+} while (0)
+#endif
+
+#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT)
+struct task_struct;
+extern int dump_task_regs (struct task_struct *, elf_gregset_t *);
+extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *);
+
+#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
+#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
+
+#ifdef CONFIG_VSYSCALL
+/* vDSO has arch_setup_additional_pages */
+#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
+struct linux_binprm;
+extern int arch_setup_additional_pages(struct linux_binprm *bprm,
+                                       int executable_stack);
+
+extern unsigned int vdso_enabled;
+extern void __kernel_vsyscall;
+
+#define VDSO_BASE               ((unsigned long)current->mm->context.vdso)
+#define VDSO_SYM(x)             (VDSO_BASE + (unsigned long)(x))
+
+#define VSYSCALL_AUX_ENT                                        \
+        if (vdso_enabled)                                       \
+                NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_BASE);
+#else
+#define VSYSCALL_AUX_ENT
+#endif /* CONFIG_VSYSCALL */
+
+#ifdef CONFIG_SH_FPU
+#define FPU_AUX_ENT     NEW_AUX_ENT(AT_FPUCW, FPSCR_INIT)
+#else
+#define FPU_AUX_ENT
+#endif
+
+extern int l1i_cache_shape, l1d_cache_shape, l2_cache_shape;
+
+/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
+#define ARCH_DLINFO                                             \
+do {                                                            \
+        /* Optional FPU initialization */                       \
+        FPU_AUX_ENT;                                            \
+                                                                \
+        /* Optional vsyscall entry */                           \
+        VSYSCALL_AUX_ENT;                                       \
+                                                                \
+        /* Cache desc */                                        \
+        NEW_AUX_ENT(AT_L1I_CACHESHAPE, l1i_cache_shape);        \
+        NEW_AUX_ENT(AT_L1D_CACHESHAPE, l1d_cache_shape);        \
+        NEW_AUX_ENT(AT_L2_CACHESHAPE, l2_cache_shape);          \
+} while (0)
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_ELF_H */
diff --git a/arch/sh/include/asm/emergency-restart.h b/arch/sh/include/asm/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/arch/sh/include/asm/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/sh/include/asm/entry-macros.S b/arch/sh/include/asm/entry-macros.S
new file mode 100644
index 000000000000..2dab0b8d9454
--- /dev/null
+++ b/arch/sh/include/asm/entry-macros.S
@@ -0,0 +1,33 @@
+! entry.S macro define
+        
+        .macro  cli
+        stc     sr, r0
+        or      #0xf0, r0
+        ldc     r0, sr
+        .endm
+
+        .macro  sti
+        mov     #0xf0, r11
+        extu.b  r11, r11
+        not     r11, r11
+        stc     sr, r10
+        and     r11, r10
+#ifdef CONFIG_CPU_HAS_SR_RB
+        stc     k_g_imask, r11
+        or      r11, r10
+#endif
+        ldc     r10, sr
+        .endm
+
+        .macro  get_current_thread_info, ti, tmp
+#ifdef CONFIG_CPU_HAS_SR_RB
+        stc     r7_bank, \ti
+#else
+        mov     #((THREAD_SIZE - 1) >> 10) ^ 0xff, \tmp
+        shll8   \tmp
+        shll2   \tmp
+        mov     r15, \ti
+        and     \tmp, \ti
+#endif  
+        .endm
+
diff --git a/arch/sh/include/asm/errno.h b/arch/sh/include/asm/errno.h
new file mode 100644
index 000000000000..51cf6f9cebb8
--- /dev/null
+++ b/arch/sh/include/asm/errno.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SH_ERRNO_H
+#define __ASM_SH_ERRNO_H
+
+#include <asm-generic/errno.h>
+
+#endif /* __ASM_SH_ERRNO_H */
diff --git a/arch/sh/include/asm/fb.h b/arch/sh/include/asm/fb.h
new file mode 100644
index 000000000000..d92e99cd8c8a
--- /dev/null
+++ b/arch/sh/include/asm/fb.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_FB_H_
+#define _ASM_FB_H_
+
+#include <linux/fb.h>
+#include <linux/fs.h>
+#include <asm/page.h>
+
+static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
+                                unsigned long off)
+{
+        vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+}
+
+static inline int fb_is_primary_device(struct fb_info *info)
+{
+        return 0;
+}
+
+#endif /* _ASM_FB_H_ */
diff --git a/arch/sh/include/asm/fcntl.h b/arch/sh/include/asm/fcntl.h
new file mode 100644
index 000000000000..46ab12db5739
--- /dev/null
+++ b/arch/sh/include/asm/fcntl.h
@@ -0,0 +1 @@
+#include <asm-generic/fcntl.h>
diff --git a/arch/sh/include/asm/fixmap.h b/arch/sh/include/asm/fixmap.h
new file mode 100644
index 000000000000..721fcc4d5e98
--- /dev/null
+++ b/arch/sh/include/asm/fixmap.h
@@ -0,0 +1,117 @@
+/*
+ * fixmap.h: compile-time virtual memory allocation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998 Ingo Molnar
+ *
+ * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
+ */
+
+#ifndef _ASM_FIXMAP_H
+#define _ASM_FIXMAP_H
+
+#include <linux/kernel.h>
+#include <asm/page.h>
+#ifdef CONFIG_HIGHMEM
+#include <linux/threads.h>
+#include <asm/kmap_types.h>
+#endif
+
+/*
+ * Here we define all the compile-time 'special' virtual
+ * addresses. The point is to have a constant address at
+ * compile time, but to set the physical address only
+ * in the boot process. We allocate these special  addresses
+ * from the end of P3 backwards.
+ * Also this lets us do fail-safe vmalloc(), we
+ * can guarantee that these special addresses and
+ * vmalloc()-ed addresses never overlap.
+ *
+ * these 'compile-time allocated' memory buffers are
+ * fixed-size 4k pages. (or larger if used with an increment
+ * highger than 1) use fixmap_set(idx,phys) to associate
+ * physical memory with fixmap indices.
+ *
+ * TLB entries of such buffers will not be flushed across
+ * task switches.
+ */
+
+/*
+ * on UP currently we will have no trace of the fixmap mechanizm,
+ * no page table allocations, etc. This might change in the
+ * future, say framebuffers for the console driver(s) could be
+ * fix-mapped?
+ */
+enum fixed_addresses {
+#define FIX_N_COLOURS 16
+        FIX_CMAP_BEGIN,
+        FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS,
+        FIX_UNCACHED,
+#ifdef CONFIG_HIGHMEM
+        FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
+        FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
+#endif
+        __end_of_fixed_addresses
+};
+
+extern void __set_fixmap(enum fixed_addresses idx,
+                         unsigned long phys, pgprot_t flags);
+
+#define set_fixmap(idx, phys) \
+                __set_fixmap(idx, phys, PAGE_KERNEL)
+/*
+ * Some hardware wants to get fixmapped without caching.
+ */
+#define set_fixmap_nocache(idx, phys) \
+                __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
+/*
+ * used by vmalloc.c.
+ *
+ * Leave one empty page between vmalloc'ed areas and
+ * the start of the fixmap, and leave one page empty
+ * at the top of mem..
+ */
+#ifdef CONFIG_SUPERH32
+#define FIXADDR_TOP     (P4SEG - PAGE_SIZE)
+#else
+#define FIXADDR_TOP     (0xff000000 - PAGE_SIZE)
+#endif
+#define FIXADDR_SIZE    (__end_of_fixed_addresses << PAGE_SHIFT)
+#define FIXADDR_START   (FIXADDR_TOP - FIXADDR_SIZE)
+
+#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
+#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
+
+extern void __this_fixmap_does_not_exist(void);
+
+/*
+ * 'index to address' translation. If anyone tries to use the idx
+ * directly without tranlation, we catch the bug with a NULL-deference
+ * kernel oops. Illegal ranges of incoming indices are caught too.
+ */
+static inline unsigned long fix_to_virt(const unsigned int idx)
+{
+        /*
+         * this branch gets completely eliminated after inlining,
+         * except when someone tries to use fixaddr indices in an
+         * illegal way. (such as mixing up address types or using
+         * out-of-range indices).
+         *
+         * If it doesn't get removed, the linker will complain
+         * loudly with a reasonably clear error message..
+         */
+        if (idx >= __end_of_fixed_addresses)
+                __this_fixmap_does_not_exist();
+
+        return __fix_to_virt(idx);
+}
+
+static inline unsigned long virt_to_fix(const unsigned long vaddr)
+{
+        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
+        return __virt_to_fix(vaddr);
+}
+#endif
diff --git a/arch/sh/include/asm/flat.h b/arch/sh/include/asm/flat.h
new file mode 100644
index 000000000000..0cc800299e06
--- /dev/null
+++ b/arch/sh/include/asm/flat.h
@@ -0,0 +1,24 @@
+/*
+ * include/asm-sh/flat.h
+ *
+ * uClinux flat-format executables
+ *
+ * Copyright (C) 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive for
+ * more details.
+ */
+#ifndef __ASM_SH_FLAT_H
+#define __ASM_SH_FLAT_H
+
+#define flat_stack_align(sp)                    /* nothing needed */
+#define flat_argvp_envp_on_stack()              0
+#define flat_old_ram_flag(flags)                (flags)
+#define flat_reloc_valid(reloc, size)           ((reloc) <= (size))
+#define flat_get_addr_from_rp(rp, relval, flags, p)     get_unaligned(rp)
+#define flat_put_addr_at_rp(rp, val, relval)    put_unaligned(val,rp)
+#define flat_get_relocate_addr(rel)             (rel)
+#define flat_set_persistent(relval, p)          ({ (void)p; 0; })
+
+#endif /* __ASM_SH_FLAT_H */
diff --git a/arch/sh/include/asm/fpu.h b/arch/sh/include/asm/fpu.h
new file mode 100644
index 000000000000..91462fea1507
--- /dev/null
+++ b/arch/sh/include/asm/fpu.h
@@ -0,0 +1,55 @@
+#ifndef __ASM_SH_FPU_H
+#define __ASM_SH_FPU_H
+
+#ifndef __ASSEMBLY__
+#include <linux/preempt.h>
+#include <asm/ptrace.h>
+
+#ifdef CONFIG_SH_FPU
+static inline void release_fpu(struct pt_regs *regs)
+{
+        regs->sr |= SR_FD;
+}
+
+static inline void grab_fpu(struct pt_regs *regs)
+{
+        regs->sr &= ~SR_FD;
+}
+
+struct task_struct;
+
+extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs);
+#else
+
+#define release_fpu(regs)       do { } while (0)
+#define grab_fpu(regs)          do { } while (0)
+
+static inline void save_fpu(struct task_struct *tsk, struct pt_regs *regs)
+{
+        clear_tsk_thread_flag(tsk, TIF_USEDFPU);
+}
+#endif
+
+extern int do_fpu_inst(unsigned short, struct pt_regs *);
+
+static inline void unlazy_fpu(struct task_struct *tsk, struct pt_regs *regs)
+{
+        preempt_disable();
+        if (test_tsk_thread_flag(tsk, TIF_USEDFPU))
+                save_fpu(tsk, regs);
+        preempt_enable();
+}
+
+static inline void clear_fpu(struct task_struct *tsk, struct pt_regs *regs)
+{
+        preempt_disable();
+        if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) {
+                clear_tsk_thread_flag(tsk, TIF_USEDFPU);
+                release_fpu(regs);
+        }
+        preempt_enable();
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_SH_FPU_H */
diff --git a/arch/sh/include/asm/freq.h b/arch/sh/include/asm/freq.h
new file mode 100644
index 000000000000..4ece90b09b9c
--- /dev/null
+++ b/arch/sh/include/asm/freq.h
@@ -0,0 +1,18 @@
+/*
+ * include/asm-sh/freq.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __ASM_SH_FREQ_H
+#define __ASM_SH_FREQ_H
+#ifdef __KERNEL__
+
+#include <cpu/freq.h>
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_FREQ_H */
diff --git a/arch/sh/include/asm/futex-irq.h b/arch/sh/include/asm/futex-irq.h
new file mode 100644
index 000000000000..a9f16a7f9aea
--- /dev/null
+++ b/arch/sh/include/asm/futex-irq.h
@@ -0,0 +1,111 @@
+#ifndef __ASM_SH_FUTEX_IRQ_H
+#define __ASM_SH_FUTEX_IRQ_H
+
+#include <asm/system.h>
+
+static inline int atomic_futex_op_xchg_set(int oparg, int __user *uaddr,
+                                           int *oldval)
+{
+        unsigned long flags;
+        int ret;
+
+        local_irq_save(flags);
+
+        ret = get_user(*oldval, uaddr);
+        if (!ret)
+                ret = put_user(oparg, uaddr);
+
+        local_irq_restore(flags);
+
+        return ret;
+}
+
+static inline int atomic_futex_op_xchg_add(int oparg, int __user *uaddr,
+                                           int *oldval)
+{
+        unsigned long flags;
+        int ret;
+
+        local_irq_save(flags);
+
+        ret = get_user(*oldval, uaddr);
+        if (!ret)
+                ret = put_user(*oldval + oparg, uaddr);
+
+        local_irq_restore(flags);
+
+        return ret;
+}
+
+static inline int atomic_futex_op_xchg_or(int oparg, int __user *uaddr,
+                                          int *oldval)
+{
+        unsigned long flags;
+        int ret;
+
+        local_irq_save(flags);
+
+        ret = get_user(*oldval, uaddr);
+        if (!ret)
+                ret = put_user(*oldval | oparg, uaddr);
+
+        local_irq_restore(flags);
+
+        return ret;
+}
+
+static inline int atomic_futex_op_xchg_and(int oparg, int __user *uaddr,
+                                           int *oldval)
+{
+        unsigned long flags;
+        int ret;
+
+        local_irq_save(flags);
+
+        ret = get_user(*oldval, uaddr);
+        if (!ret)
+                ret = put_user(*oldval & oparg, uaddr);
+
+        local_irq_restore(flags);
+
+        return ret;
+}
+
+static inline int atomic_futex_op_xchg_xor(int oparg, int __user *uaddr,
+                                           int *oldval)
+{
+        unsigned long flags;
+        int ret;
+
+        local_irq_save(flags);
+
+        ret = get_user(*oldval, uaddr);
+        if (!ret)
+                ret = put_user(*oldval ^ oparg, uaddr);
+
+        local_irq_restore(flags);
+
+        return ret;
+}
+
+static inline int atomic_futex_op_cmpxchg_inatomic(int __user *uaddr,
+                                                   int oldval, int newval)
+{
+        unsigned long flags;
+        int ret, prev = 0;
+
+        local_irq_save(flags);
+
+        ret = get_user(prev, uaddr);
+        if (!ret && oldval == prev)
+                ret = put_user(newval, uaddr);
+
+        local_irq_restore(flags);
+
+        if (ret)
+                return ret;
+
+        return prev;
+}
+
+#endif /* __ASM_SH_FUTEX_IRQ_H */
diff --git a/arch/sh/include/asm/futex.h b/arch/sh/include/asm/futex.h
new file mode 100644
index 000000000000..68256ec5fa35
--- /dev/null
+++ b/arch/sh/include/asm/futex.h
@@ -0,0 +1,77 @@
+#ifndef __ASM_SH_FUTEX_H
+#define __ASM_SH_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <linux/uaccess.h>
+#include <asm/errno.h>
+
+/* XXX: UP variants, fix for SH-4A and SMP.. */
+#include <asm/futex-irq.h>
+
+static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret;
+
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        pagefault_disable();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+                ret = atomic_futex_op_xchg_set(oparg, uaddr, &oldval);
+                break;
+        case FUTEX_OP_ADD:
+                ret = atomic_futex_op_xchg_add(oparg, uaddr, &oldval);
+                break;
+        case FUTEX_OP_OR:
+                ret = atomic_futex_op_xchg_or(oparg, uaddr, &oldval);
+                break;
+        case FUTEX_OP_ANDN:
+                ret = atomic_futex_op_xchg_and(~oparg, uaddr, &oldval);
+                break;
+        case FUTEX_OP_XOR:
+                ret = atomic_futex_op_xchg_xor(oparg, uaddr, &oldval);
+                break;
+        default:
+                ret = -ENOSYS;
+                break;
+        }
+
+        pagefault_enable();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+
+        return ret;
+}
+
+static inline int
+futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
+{
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        return atomic_futex_op_cmpxchg_inatomic(uaddr, oldval, newval);
+}
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_FUTEX_H */
diff --git a/arch/sh/include/asm/gpio.h b/arch/sh/include/asm/gpio.h
new file mode 100644
index 000000000000..cf32bd2df881
--- /dev/null
+++ b/arch/sh/include/asm/gpio.h
@@ -0,0 +1,19 @@
+/*
+ *  include/asm-sh/gpio.h
+ *
+ *  Copyright (C) 2007 Markus Brunner, Mark Jonas
+ *
+ *  Addresses for the Pin Function Controller
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_GPIO_H
+#define __ASM_SH_GPIO_H
+
+#if defined(CONFIG_CPU_SH3)
+#include <cpu/gpio.h>
+#endif
+
+#endif /* __ASM_SH_GPIO_H */
diff --git a/arch/sh/include/asm/hardirq.h b/arch/sh/include/asm/hardirq.h
new file mode 100644
index 000000000000..715ee237fc77
--- /dev/null
+++ b/arch/sh/include/asm/hardirq.h
@@ -0,0 +1,16 @@
+#ifndef __ASM_SH_HARDIRQ_H
+#define __ASM_SH_HARDIRQ_H
+
+#include <linux/threads.h>
+#include <linux/irq.h>
+
+/* entry.S is sensitive to the offsets of these fields */
+typedef struct {
+        unsigned int __softirq_pending;
+} ____cacheline_aligned irq_cpustat_t;
+
+#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
+
+extern void ack_bad_irq(unsigned int irq);
+
+#endif /* __ASM_SH_HARDIRQ_H */
diff --git a/arch/sh/include/asm/hd64461.h b/arch/sh/include/asm/hd64461.h
new file mode 100644
index 000000000000..8c1353baf00f
--- /dev/null
+++ b/arch/sh/include/asm/hd64461.h
@@ -0,0 +1,250 @@
+#ifndef __ASM_SH_HD64461
+#define __ASM_SH_HD64461
+/*
+ *      Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
+ *      Copyright (C) 2004 Paul Mundt
+ *      Copyright (C) 2000 YAEGASHI Takeshi
+ *
+ *              Hitachi HD64461 companion chip support
+ *      (please note manual reference 0x10000000 = 0xb0000000)
+ */
+
+/* Constants for PCMCIA mappings */
+#define HD64461_PCC_WINDOW      0x01000000
+
+/* Area 6 - Slot 0 - memory and/or IO card */
+#define HD64461_PCC0_BASE       (CONFIG_HD64461_IOBASE + 0x8000000)
+#define HD64461_PCC0_ATTR       (HD64461_PCC0_BASE)                             /* 0xb80000000 */
+#define HD64461_PCC0_COMM       (HD64461_PCC0_BASE+HD64461_PCC_WINDOW)          /* 0xb90000000 */
+#define HD64461_PCC0_IO         (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)        /* 0xba0000000 */
+
+/* Area 5 - Slot 1 - memory card only */
+#define HD64461_PCC1_BASE       (CONFIG_HD64461_IOBASE + 0x4000000)
+#define HD64461_PCC1_ATTR       (HD64461_PCC1_BASE)                             /* 0xb4000000 */
+#define HD64461_PCC1_COMM       (HD64461_PCC1_BASE+HD64461_PCC_WINDOW)          /* 0xb5000000 */
+
+/* Standby Control Register for HD64461 */
+#define HD64461_STBCR                   CONFIG_HD64461_IOBASE
+#define HD64461_STBCR_CKIO_STBY         0x2000
+#define HD64461_STBCR_SAFECKE_IST       0x1000
+#define HD64461_STBCR_SLCKE_IST         0x0800
+#define HD64461_STBCR_SAFECKE_OST       0x0400
+#define HD64461_STBCR_SLCKE_OST         0x0200
+#define HD64461_STBCR_SMIAST            0x0100
+#define HD64461_STBCR_SLCDST            0x0080
+#define HD64461_STBCR_SPC0ST            0x0040
+#define HD64461_STBCR_SPC1ST            0x0020
+#define HD64461_STBCR_SAFEST            0x0010
+#define HD64461_STBCR_STM0ST            0x0008
+#define HD64461_STBCR_STM1ST            0x0004
+#define HD64461_STBCR_SIRST             0x0002
+#define HD64461_STBCR_SURTST            0x0001
+
+/* System Configuration Register */
+#define HD64461_SYSCR           (CONFIG_HD64461_IOBASE + 0x02)
+
+/* CPU Data Bus Control Register */
+#define HD64461_SCPUCR          (CONFIG_HD64461_IOBASE + 0x04)
+
+/* Base Address Register */
+#define HD64461_LCDCBAR         (CONFIG_HD64461_IOBASE + 0x1000)
+
+/* Line increment address */
+#define HD64461_LCDCLOR         (CONFIG_HD64461_IOBASE + 0x1002)
+
+/* Controls LCD controller */
+#define HD64461_LCDCCR          (CONFIG_HD64461_IOBASE + 0x1004)
+
+/* LCCDR control bits */
+#define HD64461_LCDCCR_STBACK   0x0400  /* Standby Back */
+#define HD64461_LCDCCR_STREQ    0x0100  /* Standby Request */
+#define HD64461_LCDCCR_MOFF     0x0080  /* Memory Off */
+#define HD64461_LCDCCR_REFSEL   0x0040  /* Refresh Select */
+#define HD64461_LCDCCR_EPON     0x0020  /* End Power On */
+#define HD64461_LCDCCR_SPON     0x0010  /* Start Power On */
+
+/* Controls LCD (1) */
+#define HD64461_LDR1            (CONFIG_HD64461_IOBASE + 0x1010)
+#define HD64461_LDR1_DON        0x01    /* Display On */
+#define HD64461_LDR1_DINV       0x80    /* Display Invert */
+
+/* Controls LCD (2) */
+#define HD64461_LDR2            (CONFIG_HD64461_IOBASE + 0x1012)
+#define HD64461_LDHNCR          (CONFIG_HD64461_IOBASE + 0x1014)        /* Number of horizontal characters */
+#define HD64461_LDHNSR          (CONFIG_HD64461_IOBASE + 0x1016)        /* Specify output start position + width of CL1 */
+#define HD64461_LDVNTR          (CONFIG_HD64461_IOBASE + 0x1018)        /* Specify total vertical lines */
+#define HD64461_LDVNDR          (CONFIG_HD64461_IOBASE + 0x101a)        /* specify number of display vertical lines */
+#define HD64461_LDVSPR          (CONFIG_HD64461_IOBASE + 0x101c)        /* specify vertical synchronization pos and AC nr */
+
+/* Controls LCD (3) */
+#define HD64461_LDR3            (CONFIG_HD64461_IOBASE + 0x101e)
+
+/* Palette Registers */
+#define HD64461_CPTWAR          (CONFIG_HD64461_IOBASE + 0x1030)        /* Color Palette Write Address Register */
+#define HD64461_CPTWDR          (CONFIG_HD64461_IOBASE + 0x1032)        /* Color Palette Write Data Register */
+#define HD64461_CPTRAR          (CONFIG_HD64461_IOBASE + 0x1034)        /* Color Palette Read Address Register */
+#define HD64461_CPTRDR          (CONFIG_HD64461_IOBASE + 0x1036)        /* Color Palette Read Data Register */
+
+#define HD64461_GRDOR           (CONFIG_HD64461_IOBASE + 0x1040)        /* Display Resolution Offset Register */
+#define HD64461_GRSCR           (CONFIG_HD64461_IOBASE + 0x1042)        /* Solid Color Register */
+#define HD64461_GRCFGR          (CONFIG_HD64461_IOBASE + 0x1044)        /* Accelerator Configuration Register */
+
+#define HD64461_GRCFGR_ACCSTATUS        0x10    /* Accelerator Status */
+#define HD64461_GRCFGR_ACCRESET         0x08    /* Accelerator Reset */
+#define HD64461_GRCFGR_ACCSTART_BITBLT  0x06    /* Accelerator Start BITBLT */
+#define HD64461_GRCFGR_ACCSTART_LINE    0x04    /* Accelerator Start Line Drawing */
+#define HD64461_GRCFGR_COLORDEPTH16     0x01    /* Sets Colordepth 16 for Accelerator */
+#define HD64461_GRCFGR_COLORDEPTH8      0x01    /* Sets Colordepth 8 for Accelerator */
+
+/* Line Drawing Registers */
+#define HD64461_LNSARH          (CONFIG_HD64461_IOBASE + 0x1046)        /* Line Start Address Register (H) */
+#define HD64461_LNSARL          (CONFIG_HD64461_IOBASE + 0x1048)        /* Line Start Address Register (L) */
+#define HD64461_LNAXLR          (CONFIG_HD64461_IOBASE + 0x104a)        /* Axis Pixel Length Register */
+#define HD64461_LNDGR           (CONFIG_HD64461_IOBASE + 0x104c)        /* Diagonal Register */
+#define HD64461_LNAXR           (CONFIG_HD64461_IOBASE + 0x104e)        /* Axial Register */
+#define HD64461_LNERTR          (CONFIG_HD64461_IOBASE + 0x1050)        /* Start Error Term Register */
+#define HD64461_LNMDR           (CONFIG_HD64461_IOBASE + 0x1052)        /* Line Mode Register */
+
+/* BitBLT Registers */
+#define HD64461_BBTSSARH        (CONFIG_HD64461_IOBASE + 0x1054)        /* Source Start Address Register (H) */
+#define HD64461_BBTSSARL        (CONFIG_HD64461_IOBASE + 0x1056)        /* Source Start Address Register (L) */
+#define HD64461_BBTDSARH        (CONFIG_HD64461_IOBASE + 0x1058)        /* Destination Start Address Register (H) */
+#define HD64461_BBTDSARL        (CONFIG_HD64461_IOBASE + 0x105a)        /* Destination Start Address Register (L) */
+#define HD64461_BBTDWR          (CONFIG_HD64461_IOBASE + 0x105c)        /* Destination Block Width Register */
+#define HD64461_BBTDHR          (CONFIG_HD64461_IOBASE + 0x105e)        /* Destination Block Height Register */
+#define HD64461_BBTPARH         (CONFIG_HD64461_IOBASE + 0x1060)        /* Pattern Start Address Register (H) */
+#define HD64461_BBTPARL         (CONFIG_HD64461_IOBASE + 0x1062)        /* Pattern Start Address Register (L) */
+#define HD64461_BBTMARH         (CONFIG_HD64461_IOBASE + 0x1064)        /* Mask Start Address Register (H) */
+#define HD64461_BBTMARL         (CONFIG_HD64461_IOBASE + 0x1066)        /* Mask Start Address Register (L) */
+#define HD64461_BBTROPR         (CONFIG_HD64461_IOBASE + 0x1068)        /* ROP Register */
+#define HD64461_BBTMDR          (CONFIG_HD64461_IOBASE + 0x106a)        /* BitBLT Mode Register */
+
+/* PC Card Controller Registers */
+/* Maps to Physical Area 6 */
+#define HD64461_PCC0ISR         (CONFIG_HD64461_IOBASE + 0x2000)        /* socket 0 interface status */
+#define HD64461_PCC0GCR         (CONFIG_HD64461_IOBASE + 0x2002)        /* socket 0 general control */
+#define HD64461_PCC0CSCR        (CONFIG_HD64461_IOBASE + 0x2004)        /* socket 0 card status change */
+#define HD64461_PCC0CSCIER      (CONFIG_HD64461_IOBASE + 0x2006)        /* socket 0 card status change interrupt enable */
+#define HD64461_PCC0SCR         (CONFIG_HD64461_IOBASE + 0x2008)        /* socket 0 software control */
+/* Maps to Physical Area 5 */
+#define HD64461_PCC1ISR         (CONFIG_HD64461_IOBASE + 0x2010)        /* socket 1 interface status */
+#define HD64461_PCC1GCR         (CONFIG_HD64461_IOBASE + 0x2012)        /* socket 1 general control */
+#define HD64461_PCC1CSCR        (CONFIG_HD64461_IOBASE + 0x2014)        /* socket 1 card status change */
+#define HD64461_PCC1CSCIER      (CONFIG_HD64461_IOBASE + 0x2016)        /* socket 1 card status change interrupt enable */
+#define HD64461_PCC1SCR         (CONFIG_HD64461_IOBASE + 0x2018)        /* socket 1 software control */
+
+/* PCC Interface Status Register */
+#define HD64461_PCCISR_READY            0x80    /* card ready */
+#define HD64461_PCCISR_MWP              0x40    /* card write-protected */
+#define HD64461_PCCISR_VS2              0x20    /* voltage select pin 2 */
+#define HD64461_PCCISR_VS1              0x10    /* voltage select pin 1 */
+#define HD64461_PCCISR_CD2              0x08    /* card detect 2 */
+#define HD64461_PCCISR_CD1              0x04    /* card detect 1 */
+#define HD64461_PCCISR_BVD2             0x02    /* battery 1 */
+#define HD64461_PCCISR_BVD1             0x01    /* battery 1 */
+
+#define HD64461_PCCISR_PCD_MASK         0x0c    /* card detect */
+#define HD64461_PCCISR_BVD_MASK         0x03    /* battery voltage */
+#define HD64461_PCCISR_BVD_BATGOOD      0x03    /* battery good */
+#define HD64461_PCCISR_BVD_BATWARN      0x01    /* battery low warning */
+#define HD64461_PCCISR_BVD_BATDEAD1     0x02    /* battery dead */
+#define HD64461_PCCISR_BVD_BATDEAD2     0x00    /* battery dead */
+
+/* PCC General Control Register */
+#define HD64461_PCCGCR_DRVE             0x80    /* output drive */
+#define HD64461_PCCGCR_PCCR             0x40    /* PC card reset */
+#define HD64461_PCCGCR_PCCT             0x20    /* PC card type, 1=IO&mem, 0=mem */
+#define HD64461_PCCGCR_VCC0             0x10    /* voltage control pin VCC0SEL0 */
+#define HD64461_PCCGCR_PMMOD            0x08    /* memory mode */
+#define HD64461_PCCGCR_PA25             0x04    /* pin A25 */
+#define HD64461_PCCGCR_PA24             0x02    /* pin A24 */
+#define HD64461_PCCGCR_REG              0x01    /* pin PCC0REG# */
+
+/* PCC Card Status Change Register */
+#define HD64461_PCCCSCR_SCDI            0x80    /* sw card detect intr */
+#define HD64461_PCCCSCR_SRV1            0x40    /* reserved */
+#define HD64461_PCCCSCR_IREQ            0x20    /* IREQ intr req */
+#define HD64461_PCCCSCR_SC              0x10    /* STSCHG (status change) pin */
+#define HD64461_PCCCSCR_CDC             0x08    /* CD (card detect) change */
+#define HD64461_PCCCSCR_RC              0x04    /* READY change */
+#define HD64461_PCCCSCR_BW              0x02    /* battery warning change */
+#define HD64461_PCCCSCR_BD              0x01    /* battery dead change */
+
+/* PCC Card Status Change Interrupt Enable Register */
+#define HD64461_PCCCSCIER_CRE           0x80    /* change reset enable */
+#define HD64461_PCCCSCIER_IREQE_MASK    0x60    /* IREQ enable */
+#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00   /* IREQ disabled */
+#define HD64461_PCCCSCIER_IREQE_LEVEL   0x20    /* IREQ level-triggered */
+#define HD64461_PCCCSCIER_IREQE_FALLING 0x40    /* IREQ falling-edge-trig */
+#define HD64461_PCCCSCIER_IREQE_RISING  0x60    /* IREQ rising-edge-trig */
+
+#define HD64461_PCCCSCIER_SCE           0x10    /* status change enable */
+#define HD64461_PCCCSCIER_CDE           0x08    /* card detect change enable */
+#define HD64461_PCCCSCIER_RE            0x04    /* ready change enable */
+#define HD64461_PCCCSCIER_BWE           0x02    /* battery warn change enable */
+#define HD64461_PCCCSCIER_BDE           0x01    /* battery dead change enable*/
+
+/* PCC Software Control Register */
+#define HD64461_PCCSCR_VCC1             0x02    /* voltage control pin 1 */
+#define HD64461_PCCSCR_SWP              0x01    /* write protect */
+
+/* PCC0 Output Pins Control Register */
+#define HD64461_P0OCR           (CONFIG_HD64461_IOBASE + 0x202a)
+
+/* PCC1 Output Pins Control Register */
+#define HD64461_P1OCR           (CONFIG_HD64461_IOBASE + 0x202c)
+
+/* PC Card General Control Register */
+#define HD64461_PGCR            (CONFIG_HD64461_IOBASE + 0x202e)
+
+/* Port Control Registers */
+#define HD64461_GPACR           (CONFIG_HD64461_IOBASE + 0x4000)        /* Port A - Handles IRDA/TIMER */
+#define HD64461_GPBCR           (CONFIG_HD64461_IOBASE + 0x4002)        /* Port B - Handles UART */
+#define HD64461_GPCCR           (CONFIG_HD64461_IOBASE + 0x4004)        /* Port C - Handles PCMCIA 1 */
+#define HD64461_GPDCR           (CONFIG_HD64461_IOBASE + 0x4006)        /* Port D - Handles PCMCIA 1 */
+
+/* Port Control Data Registers */
+#define HD64461_GPADR           (CONFIG_HD64461_IOBASE + 0x4010)        /* A */
+#define HD64461_GPBDR           (CONFIG_HD64461_IOBASE + 0x4012)        /* B */
+#define HD64461_GPCDR           (CONFIG_HD64461_IOBASE + 0x4014)        /* C */
+#define HD64461_GPDDR           (CONFIG_HD64461_IOBASE + 0x4016)        /* D */
+
+/* Interrupt Control Registers */
+#define HD64461_GPAICR          (CONFIG_HD64461_IOBASE + 0x4020)        /* A */
+#define HD64461_GPBICR          (CONFIG_HD64461_IOBASE + 0x4022)        /* B */
+#define HD64461_GPCICR          (CONFIG_HD64461_IOBASE + 0x4024)        /* C */
+#define HD64461_GPDICR          (CONFIG_HD64461_IOBASE + 0x4026)        /* D */
+
+/* Interrupt Status Registers */
+#define HD64461_GPAISR          (CONFIG_HD64461_IOBASE + 0x4040)        /* A */
+#define HD64461_GPBISR          (CONFIG_HD64461_IOBASE + 0x4042)        /* B */
+#define HD64461_GPCISR          (CONFIG_HD64461_IOBASE + 0x4044)        /* C */
+#define HD64461_GPDISR          (CONFIG_HD64461_IOBASE + 0x4046)        /* D */
+
+/* Interrupt Request Register & Interrupt Mask Register */
+#define HD64461_NIRR            (CONFIG_HD64461_IOBASE + 0x5000)
+#define HD64461_NIMR            (CONFIG_HD64461_IOBASE + 0x5002)
+
+#define HD64461_IRQBASE         OFFCHIP_IRQ_BASE
+#define OFFCHIP_IRQ_BASE        64
+#define HD64461_IRQ_NUM         16
+
+#define HD64461_IRQ_UART        (HD64461_IRQBASE+5)
+#define HD64461_IRQ_IRDA        (HD64461_IRQBASE+6)
+#define HD64461_IRQ_TMU1        (HD64461_IRQBASE+9)
+#define HD64461_IRQ_TMU0        (HD64461_IRQBASE+10)
+#define HD64461_IRQ_GPIO        (HD64461_IRQBASE+11)
+#define HD64461_IRQ_AFE         (HD64461_IRQBASE+12)
+#define HD64461_IRQ_PCC1        (HD64461_IRQBASE+13)
+#define HD64461_IRQ_PCC0        (HD64461_IRQBASE+14)
+
+#define __IO_PREFIX     hd64461
+#include <asm/io_generic.h>
+
+/* arch/sh/cchips/hd6446x/hd64461/setup.c */
+int hd64461_irq_demux(int irq);
+void hd64461_register_irq_demux(int irq,
+                                int (*demux) (int irq, void *dev), void *dev);
+void hd64461_unregister_irq_demux(int irq);
+
+#endif
diff --git a/arch/sh/include/asm/hd64465/gpio.h b/arch/sh/include/asm/hd64465/gpio.h
new file mode 100644
index 000000000000..a3cdca2713dd
--- /dev/null
+++ b/arch/sh/include/asm/hd64465/gpio.h
@@ -0,0 +1,46 @@
+#ifndef _ASM_SH_HD64465_GPIO_
+#define _ASM_SH_HD64465_GPIO_ 1
+/*
+ * $Id: gpio.h,v 1.3 2003/05/04 19:30:14 lethal Exp $
+ *
+ * Hitachi HD64465 companion chip: General Purpose IO pins support.
+ * This layer enables other device drivers to configure GPIO
+ * pins, get and set their values, and register an interrupt
+ * routine for when input pins change in hardware.
+ *
+ * by Greg Banks <gbanks@pocketpenguins.com>
+ * (c) 2000 PocketPenguins Inc.
+ */
+#include <asm/hd64465.h>
+
+/* Macro to construct a portpin number (used in all
+ * subsequent functions) from a port letter and a pin
+ * number, e.g. HD64465_GPIO_PORTPIN('A', 5).
+ */
+#define HD64465_GPIO_PORTPIN(port,pin)  (((port)-'A')<<3|(pin))
+
+/* Pin configuration constants for _configure() */
+#define HD64465_GPIO_FUNCTION2  0       /* use the pin's *other* function */
+#define HD64465_GPIO_OUT        1       /* output */
+#define HD64465_GPIO_IN_PULLUP  2       /* input, pull-up MOS on */
+#define HD64465_GPIO_IN         3       /* input */
+
+/* Configure a pin's direction */
+extern void hd64465_gpio_configure(int portpin, int direction);
+
+/* Get, set value */
+extern void hd64465_gpio_set_pin(int portpin, unsigned int value);
+extern unsigned int hd64465_gpio_get_pin(int portpin);
+extern void hd64465_gpio_set_port(int port, unsigned int value);
+extern unsigned int hd64465_gpio_get_port(int port);
+
+/* mode constants for _register_irq() */
+#define HD64465_GPIO_FALLING    0
+#define HD64465_GPIO_RISING     1
+
+/* Interrupt on external value change */
+extern void hd64465_gpio_register_irq(int portpin, int mode,
+        void (*handler)(int portpin, void *dev), void *dev);
+extern void hd64465_gpio_unregister_irq(int portpin);
+
+#endif /* _ASM_SH_HD64465_GPIO_  */
diff --git a/arch/sh/include/asm/hd64465/hd64465.h b/arch/sh/include/asm/hd64465/hd64465.h
new file mode 100644
index 000000000000..cfd0e803d2a2
--- /dev/null
+++ b/arch/sh/include/asm/hd64465/hd64465.h
@@ -0,0 +1,256 @@
+#ifndef _ASM_SH_HD64465_
+#define _ASM_SH_HD64465_ 1
+/*
+ * $Id: hd64465.h,v 1.3 2003/05/04 19:30:15 lethal Exp $
+ *
+ * Hitachi HD64465 companion chip support
+ *
+ * by Greg Banks <gbanks@pocketpenguins.com>
+ * (c) 2000 PocketPenguins Inc.
+ *
+ * Derived from <asm/hd64461.h> which bore the message:
+ * Copyright (C) 2000 YAEGASHI Takeshi
+ */
+#include <asm/io.h>
+#include <asm/irq.h>
+
+/*
+ * Note that registers are defined here as virtual port numbers,
+ * which have no meaning except to get translated by hd64465_isa_port2addr()
+ * to an address in the range 0xb0000000-0xb3ffffff.  Note that
+ * this translation happens to consist of adding the lower 16 bits
+ * of the virtual port number to 0xb0000000.  Note also that the manual
+ * shows addresses as absolute physical addresses starting at 0x10000000,
+ * so e.g. the NIRR register is listed as 0x15000 here, 0x10005000 in the
+ * manual, and accessed using address 0xb0005000 - Greg.
+ */
+
+/* System registers */
+#define HD64465_REG_SRR     0x1000c     /* System Revision Register */
+#define HD64465_REG_SDID    0x10010     /* System Device ID Reg */
+#define     HD64465_SDID            0x8122  /* 64465 device ID */
+
+/* Power Management registers */
+#define HD64465_REG_SMSCR   0x10000     /* System Module Standby Control Reg */
+#define     HD64465_SMSCR_PS2ST     0x4000  /* PS/2 Standby */
+#define     HD64465_SMSCR_ADCST     0x1000  /* ADC Standby */
+#define     HD64465_SMSCR_UARTST    0x0800  /* UART Standby */
+#define     HD64465_SMSCR_SCDIST    0x0200  /* Serial Codec Standby */
+#define     HD64465_SMSCR_PPST      0x0100  /* Parallel Port Standby */
+#define     HD64465_SMSCR_PC0ST     0x0040  /* PCMCIA0 Standby */
+#define     HD64465_SMSCR_PC1ST     0x0020  /* PCMCIA1 Standby */
+#define     HD64465_SMSCR_AFEST     0x0010  /* AFE Standby */
+#define     HD64465_SMSCR_TM0ST     0x0008  /* Timer0 Standby */
+#define     HD64465_SMSCR_TM1ST     0x0004  /* Timer1 Standby */
+#define     HD64465_SMSCR_IRDAST    0x0002  /* IRDA Standby */
+#define     HD64465_SMSCR_KBCST     0x0001  /* Keyboard Controller Standby */
+ 
+/* Interrupt Controller registers */
+#define HD64465_REG_NIRR    0x15000     /* Interrupt Request Register */
+#define HD64465_REG_NIMR    0x15002     /* Interrupt Mask Register */
+#define HD64465_REG_NITR    0x15004     /* Interrupt Trigger Mode Register */
+
+/* Timer registers */
+#define HD64465_REG_TCVR1   0x16000     /* Timer 1 constant value register  */
+#define HD64465_REG_TCVR0   0x16002     /* Timer 0 constant value register  */
+#define HD64465_REG_TRVR1   0x16004     /* Timer 1 read value register  */
+#define HD64465_REG_TRVR0   0x16006     /* Timer 0 read value register  */
+#define HD64465_REG_TCR1    0x16008     /* Timer 1 control register  */
+#define HD64465_REG_TCR0    0x1600A     /* Timer 0 control register  */
+#define     HD64465_TCR_EADT    0x10        /* Enable ADTRIG# signal */
+#define     HD64465_TCR_ETMO    0x08        /* Enable TMO signal */
+#define     HD64465_TCR_PST_MASK 0x06       /* Clock Prescale */
+#define     HD64465_TCR_PST_1   0x06        /* 1:1 */
+#define     HD64465_TCR_PST_4   0x04        /* 1:4 */
+#define     HD64465_TCR_PST_8   0x02        /* 1:8 */
+#define     HD64465_TCR_PST_16  0x00        /* 1:16 */
+#define     HD64465_TCR_TSTP    0x01        /* Start/Stop timer */
+#define HD64465_REG_TIRR    0x1600C     /* Timer interrupt request register  */
+#define HD64465_REG_TIDR    0x1600E     /* Timer interrupt disable register  */
+#define HD64465_REG_PWM1CS  0x16010     /* PWM 1 clock scale register  */
+#define HD64465_REG_PWM1LPC 0x16012     /* PWM 1 low pulse width counter register  */
+#define HD64465_REG_PWM1HPC 0x16014     /* PWM 1 high pulse width counter register  */
+#define HD64465_REG_PWM0CS  0x16018     /* PWM 0 clock scale register  */
+#define HD64465_REG_PWM0LPC 0x1601A     /* PWM 0 low pulse width counter register  */
+#define HD64465_REG_PWM0HPC 0x1601C     /* PWM 0 high pulse width counter register  */
+
+/* Analog/Digital Converter registers */
+#define HD64465_REG_ADDRA   0x1E000     /* A/D data register A */
+#define HD64465_REG_ADDRB   0x1E002     /* A/D data register B */
+#define HD64465_REG_ADDRC   0x1E004     /* A/D data register C */
+#define HD64465_REG_ADDRD   0x1E006     /* A/D data register D */
+#define HD64465_REG_ADCSR   0x1E008     /* A/D control/status register */
+#define     HD64465_ADCSR_ADF       0x80    /* A/D End Flag */
+#define     HD64465_ADCSR_ADST      0x40    /* A/D Start Flag */
+#define     HD64465_ADCSR_ADIS      0x20    /* A/D Interrupt Status */
+#define     HD64465_ADCSR_TRGE      0x10    /* A/D Trigger Enable */
+#define     HD64465_ADCSR_ADIE      0x08    /* A/D Interrupt Enable */
+#define     HD64465_ADCSR_SCAN      0x04    /* A/D Scan Mode */
+#define     HD64465_ADCSR_CH_MASK   0x03    /* A/D Channel */
+#define HD64465_REG_ADCALCR 0x1E00A     /* A/D calibration sample control */
+#define HD64465_REG_ADCAL   0x1E00C     /* A/D calibration data register */
+
+
+/* General Purpose I/O ports registers */
+#define HD64465_REG_GPACR   0x14000     /* Port A Control Register */
+#define HD64465_REG_GPBCR   0x14002     /* Port B Control Register */
+#define HD64465_REG_GPCCR   0x14004     /* Port C Control Register */
+#define HD64465_REG_GPDCR   0x14006     /* Port D Control Register */
+#define HD64465_REG_GPECR   0x14008     /* Port E Control Register */
+#define HD64465_REG_GPADR   0x14010     /* Port A Data Register */
+#define HD64465_REG_GPBDR   0x14012     /* Port B Data Register */
+#define HD64465_REG_GPCDR   0x14014     /* Port C Data Register */
+#define HD64465_REG_GPDDR   0x14016     /* Port D Data Register */
+#define HD64465_REG_GPEDR   0x14018     /* Port E Data Register */
+#define HD64465_REG_GPAICR  0x14020     /* Port A Interrupt Control Register */
+#define HD64465_REG_GPBICR  0x14022     /* Port B Interrupt Control Register */
+#define HD64465_REG_GPCICR  0x14024     /* Port C Interrupt Control Register */
+#define HD64465_REG_GPDICR  0x14026     /* Port D Interrupt Control Register */
+#define HD64465_REG_GPEICR  0x14028     /* Port E Interrupt Control Register */
+#define HD64465_REG_GPAISR  0x14040     /* Port A Interrupt Status Register */
+#define HD64465_REG_GPBISR  0x14042     /* Port B Interrupt Status Register */
+#define HD64465_REG_GPCISR  0x14044     /* Port C Interrupt Status Register */
+#define HD64465_REG_GPDISR  0x14046     /* Port D Interrupt Status Register */
+#define HD64465_REG_GPEISR  0x14048     /* Port E Interrupt Status Register */
+
+/* PCMCIA bridge interface */
+#define HD64465_REG_PCC0ISR     0x12000 /* socket 0 interface status */ 
+#define     HD64465_PCCISR_PREADY        0x80    /* mem card ready / io card IREQ */
+#define     HD64465_PCCISR_PIREQ         0x80
+#define     HD64465_PCCISR_PMWP          0x40    /* mem card write-protected */
+#define     HD64465_PCCISR_PVS2          0x20    /* voltage select pin 2 */
+#define     HD64465_PCCISR_PVS1          0x10    /* voltage select pin 1 */
+#define     HD64465_PCCISR_PCD_MASK      0x0c    /* card detect */
+#define     HD64465_PCCISR_PBVD_MASK     0x03    /* battery voltage */
+#define     HD64465_PCCISR_PBVD_BATGOOD  0x03    /* battery good */
+#define     HD64465_PCCISR_PBVD_BATWARN  0x01    /* battery low warning */
+#define     HD64465_PCCISR_PBVD_BATDEAD1 0x02    /* battery dead */
+#define     HD64465_PCCISR_PBVD_BATDEAD2 0x00    /* battery dead */
+#define HD64465_REG_PCC0GCR     0x12002 /* socket 0 general control */ 
+#define     HD64465_PCCGCR_PDRV          0x80    /* output drive */
+#define     HD64465_PCCGCR_PCCR          0x40    /* PC card reset */
+#define     HD64465_PCCGCR_PCCT          0x20    /* PC card type, 1=IO&mem, 0=mem */
+#define     HD64465_PCCGCR_PVCC0         0x10    /* voltage control pin VCC0SEL0 */
+#define     HD64465_PCCGCR_PMMOD         0x08    /* memory mode */
+#define     HD64465_PCCGCR_PPA25         0x04    /* pin A25 */
+#define     HD64465_PCCGCR_PPA24         0x02    /* pin A24 */
+#define     HD64465_PCCGCR_PREG          0x01    /* ping PCC0REG# */
+#define HD64465_REG_PCC0CSCR    0x12004 /* socket 0 card status change */ 
+#define     HD64465_PCCCSCR_PSCDI        0x80    /* sw card detect intr */
+#define     HD64465_PCCCSCR_PSWSEL       0x40    /* power select */
+#define     HD64465_PCCCSCR_PIREQ        0x20    /* IREQ intr req */
+#define     HD64465_PCCCSCR_PSC          0x10    /* STSCHG (status change) pin */
+#define     HD64465_PCCCSCR_PCDC         0x08    /* CD (card detect) change */
+#define     HD64465_PCCCSCR_PRC          0x04    /* ready change */
+#define     HD64465_PCCCSCR_PBW          0x02    /* battery warning change */
+#define     HD64465_PCCCSCR_PBD          0x01    /* battery dead change */
+#define HD64465_REG_PCC0CSCIER  0x12006 /* socket 0 card status change interrupt enable */ 
+#define     HD64465_PCCCSCIER_PCRE       0x80    /* change reset enable */
+#define     HD64465_PCCCSCIER_PIREQE_MASK       0x60   /* IREQ enable */
+#define     HD64465_PCCCSCIER_PIREQE_DISABLED   0x00   /* IREQ disabled */
+#define     HD64465_PCCCSCIER_PIREQE_LEVEL      0x20   /* IREQ level-triggered */
+#define     HD64465_PCCCSCIER_PIREQE_FALLING    0x40   /* IREQ falling-edge-trig */
+#define     HD64465_PCCCSCIER_PIREQE_RISING     0x60   /* IREQ rising-edge-trig */
+#define     HD64465_PCCCSCIER_PSCE       0x10    /* status change enable */
+#define     HD64465_PCCCSCIER_PCDE       0x08    /* card detect change enable */
+#define     HD64465_PCCCSCIER_PRE        0x04    /* ready change enable */
+#define     HD64465_PCCCSCIER_PBWE       0x02    /* battery warn change enable */
+#define     HD64465_PCCCSCIER_PBDE       0x01    /* battery dead change enable*/
+#define HD64465_REG_PCC0SCR     0x12008 /* socket 0 software control */ 
+#define     HD64465_PCCSCR_SHDN          0x10    /* TPS2206 SHutDowN pin */
+#define     HD64465_PCCSCR_SWP           0x01    /* write protect */
+#define HD64465_REG_PCCPSR      0x1200A /* serial power switch control */ 
+#define HD64465_REG_PCC1ISR     0x12010 /* socket 1 interface status */ 
+#define HD64465_REG_PCC1GCR     0x12012 /* socket 1 general control */ 
+#define HD64465_REG_PCC1CSCR    0x12014 /* socket 1 card status change */ 
+#define HD64465_REG_PCC1CSCIER  0x12016 /* socket 1 card status change interrupt enable */ 
+#define HD64465_REG_PCC1SCR     0x12018 /* socket 1 software control */ 
+
+
+/* PS/2 Keyboard and mouse controller -- *not* register compatible */
+#define HD64465_REG_KBCSR       0x1dc00 /* Keyboard Control/Status reg */
+#define     HD64465_KBCSR_KBCIE          0x8000    /* KBCK Input Enable */
+#define     HD64465_KBCSR_KBCOE          0x4000    /* KBCK Output Enable */
+#define     HD64465_KBCSR_KBDOE          0x2000    /* KB DATA Output Enable */
+#define     HD64465_KBCSR_KBCD           0x1000    /* KBCK Driven */
+#define     HD64465_KBCSR_KBDD           0x0800    /* KB DATA Driven */
+#define     HD64465_KBCSR_KBCS           0x0400    /* KBCK pin Status */
+#define     HD64465_KBCSR_KBDS           0x0200    /* KB DATA pin Status */
+#define     HD64465_KBCSR_KBDP           0x0100    /* KB DATA Parity bit */
+#define     HD64465_KBCSR_KBD_MASK       0x00ff    /* KD DATA shift reg */
+#define HD64465_REG_KBISR       0x1dc04 /* Keyboard Interrupt Status reg */
+#define     HD64465_KBISR_KBRDF          0x0001    /* KB Received Data Full */
+#define HD64465_REG_MSCSR       0x1dc10 /* Mouse Control/Status reg */
+#define HD64465_REG_MSISR       0x1dc14 /* Mouse Interrupt Status reg */
+
+
+/*
+ * Logical address at which the HD64465 is mapped.  Note that this
+ * should always be in the P2 segment (uncached and untranslated).
+ */
+#ifndef CONFIG_HD64465_IOBASE
+#define CONFIG_HD64465_IOBASE   0xb0000000
+#endif
+/*
+ * The HD64465 multiplexes all its modules' interrupts onto
+ * this single interrupt.
+ */
+#ifndef CONFIG_HD64465_IRQ
+#define CONFIG_HD64465_IRQ      5
+#endif
+
+
+#define _HD64465_IO_MASK        0xf8000000
+#define is_hd64465_addr(addr) \
+        ((addr & _HD64465_IO_MASK) == (CONFIG_HD64465_IOBASE & _HD64465_IO_MASK))
+
+/*
+ * A range of 16 virtual interrupts generated by
+ * demuxing the HD64465 muxed interrupt.
+ */
+#define HD64465_IRQ_BASE        OFFCHIP_IRQ_BASE
+#define HD64465_IRQ_NUM         16
+#define HD64465_IRQ_ADC         (HD64465_IRQ_BASE+0)
+#define HD64465_IRQ_USB         (HD64465_IRQ_BASE+1)
+#define HD64465_IRQ_SCDI        (HD64465_IRQ_BASE+2)
+#define HD64465_IRQ_PARALLEL    (HD64465_IRQ_BASE+3)
+/* bit 4 is reserved */
+#define HD64465_IRQ_UART        (HD64465_IRQ_BASE+5)
+#define HD64465_IRQ_IRDA        (HD64465_IRQ_BASE+6)
+#define HD64465_IRQ_PS2MOUSE    (HD64465_IRQ_BASE+7)
+#define HD64465_IRQ_KBC         (HD64465_IRQ_BASE+8)
+#define HD64465_IRQ_TIMER1      (HD64465_IRQ_BASE+9)
+#define HD64465_IRQ_TIMER0      (HD64465_IRQ_BASE+10)
+#define HD64465_IRQ_GPIO        (HD64465_IRQ_BASE+11)
+#define HD64465_IRQ_AFE         (HD64465_IRQ_BASE+12)
+#define HD64465_IRQ_PCMCIA1     (HD64465_IRQ_BASE+13)
+#define HD64465_IRQ_PCMCIA0     (HD64465_IRQ_BASE+14)
+#define HD64465_IRQ_PS2KBD      (HD64465_IRQ_BASE+15)
+
+/* Constants for PCMCIA mappings */
+#define HD64465_PCC_WINDOW      0x01000000
+
+#define HD64465_PCC0_BASE       0xb8000000      /* area 6 */
+#define HD64465_PCC0_ATTR       (HD64465_PCC0_BASE)
+#define HD64465_PCC0_COMM       (HD64465_PCC0_BASE+HD64465_PCC_WINDOW)
+#define HD64465_PCC0_IO         (HD64465_PCC0_BASE+2*HD64465_PCC_WINDOW)
+
+#define HD64465_PCC1_BASE       0xb4000000      /* area 5 */
+#define HD64465_PCC1_ATTR       (HD64465_PCC1_BASE)
+#define HD64465_PCC1_COMM       (HD64465_PCC1_BASE+HD64465_PCC_WINDOW)
+#define HD64465_PCC1_IO         (HD64465_PCC1_BASE+2*HD64465_PCC_WINDOW)
+
+/*
+ * Base of USB controller interface (as memory)
+ */
+#define HD64465_USB_BASE        (CONFIG_HD64465_IOBASE+0xb000)
+#define HD64465_USB_LEN         0x1000
+/*
+ * Base of embedded SRAM, used for USB controller.
+ */
+#define HD64465_SRAM_BASE       (CONFIG_HD64465_IOBASE+0x9000)
+#define HD64465_SRAM_LEN        0x1000
+
+
+
+#endif /* _ASM_SH_HD64465_  */
diff --git a/arch/sh/include/asm/hd64465/io.h b/arch/sh/include/asm/hd64465/io.h
new file mode 100644
index 000000000000..139f1472e5bb
--- /dev/null
+++ b/arch/sh/include/asm/hd64465/io.h
@@ -0,0 +1,44 @@
+/*
+ * include/asm-sh/hd64465/io.h
+ *
+ * By Greg Banks <gbanks@pocketpenguins.com>
+ * (c) 2000 PocketPenguins Inc.
+ *
+ * Derived from io_hd64461.h, which bore the message:
+ * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * IO functions for an HD64465 "Windows CE Intelligent Peripheral Controller".
+ */
+
+#ifndef _ASM_SH_IO_HD64465_H
+#define _ASM_SH_IO_HD64465_H
+
+extern unsigned char hd64465_inb(unsigned long port);
+extern unsigned short hd64465_inw(unsigned long port);
+extern unsigned int hd64465_inl(unsigned long port);
+
+extern void hd64465_outb(unsigned char value, unsigned long port);
+extern void hd64465_outw(unsigned short value, unsigned long port);
+extern void hd64465_outl(unsigned int value, unsigned long port);
+
+extern unsigned char hd64465_inb_p(unsigned long port);
+extern void hd64465_outb_p(unsigned char value, unsigned long port);
+
+extern unsigned long hd64465_isa_port2addr(unsigned long offset);
+extern int hd64465_irq_demux(int irq);
+/* Provision for generic secondary demux step -- used by PCMCIA code */
+extern void hd64465_register_irq_demux(int irq,
+                int (*demux)(int irq, void *dev), void *dev);
+extern void hd64465_unregister_irq_demux(int irq);
+/* Set this variable to 1 to see port traffic */
+extern int hd64465_io_debug;
+/* Map a range of ports to a range of kernel virtual memory.
+ */
+extern void hd64465_port_map(unsigned short baseport, unsigned int nports,
+                             unsigned long addr, unsigned char shift);
+extern void hd64465_port_unmap(unsigned short baseport, unsigned int nports);
+
+#endif /* _ASM_SH_IO_HD64465_H */
diff --git a/arch/sh/include/asm/heartbeat.h b/arch/sh/include/asm/heartbeat.h
new file mode 100644
index 000000000000..724a43ed245e
--- /dev/null
+++ b/arch/sh/include/asm/heartbeat.h
@@ -0,0 +1,17 @@
+#ifndef __ASM_SH_HEARTBEAT_H
+#define __ASM_SH_HEARTBEAT_H
+
+#include <linux/timer.h>
+
+#define HEARTBEAT_INVERTED      (1 << 0)
+
+struct heartbeat_data {
+        void __iomem *base;
+        unsigned char *bit_pos;
+        unsigned int nr_bits;
+        struct timer_list timer;
+        unsigned int regsize;
+        unsigned long flags;
+};
+
+#endif /* __ASM_SH_HEARTBEAT_H */
diff --git a/arch/sh/include/asm/hp6xx.h b/arch/sh/include/asm/hp6xx.h
new file mode 100644
index 000000000000..0d4165a32dcd
--- /dev/null
+++ b/arch/sh/include/asm/hp6xx.h
@@ -0,0 +1,58 @@
+#ifndef __ASM_SH_HP6XX_H
+#define __ASM_SH_HP6XX_H
+
+/*
+ * Copyright (C) 2003, 2004, 2005  Andriy Skulysh
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#define HP680_BTN_IRQ           32      /* IRQ0_IRQ */
+#define HP680_TS_IRQ            35      /* IRQ3_IRQ */
+#define HP680_HD64461_IRQ       36      /* IRQ4_IRQ */
+
+#define DAC_LCD_BRIGHTNESS      0
+#define DAC_SPEAKER_VOLUME      1
+
+#define PGDR_OPENED             0x01
+#define PGDR_MAIN_BATTERY_OUT   0x04
+#define PGDR_PLAY_BUTTON        0x08
+#define PGDR_REWIND_BUTTON      0x10
+#define PGDR_RECORD_BUTTON      0x20
+
+#define PHDR_TS_PEN_DOWN        0x08
+
+#define PJDR_LED_BLINK          0x02
+
+#define PKDR_LED_GREEN          0x10
+
+#define SCPDR_TS_SCAN_ENABLE    0x20
+#define SCPDR_TS_SCAN_Y         0x02
+#define SCPDR_TS_SCAN_X         0x01
+
+#define SCPCR_TS_ENABLE         0x405
+#define SCPCR_TS_MASK           0xc0f
+
+#define ADC_CHANNEL_TS_Y        1
+#define ADC_CHANNEL_TS_X        2
+#define ADC_CHANNEL_BATTERY     3
+#define ADC_CHANNEL_BACKUP      4
+#define ADC_CHANNEL_CHARGE      5
+
+#define HD64461_GPADR_SPEAKER   0x01
+#define HD64461_GPADR_PCMCIA0   (0x02|0x08)
+
+#define HD64461_GPBDR_LCDOFF    0x01
+#define HD64461_GPBDR_LCD_CONTRAST_MASK 0x78
+#define HD64461_GPBDR_LED_RED   0x80
+
+#include <asm/hd64461.h>
+#include <asm/io.h>
+
+#define PJDR    0xa4000130
+#define PKDR    0xa4000132
+
+#endif /* __ASM_SH_HP6XX_H */
diff --git a/arch/sh/include/asm/hugetlb.h b/arch/sh/include/asm/hugetlb.h
new file mode 100644
index 000000000000..967068fb79ac
--- /dev/null
+++ b/arch/sh/include/asm/hugetlb.h
@@ -0,0 +1,92 @@
+#ifndef _ASM_SH_HUGETLB_H
+#define _ASM_SH_HUGETLB_H
+
+#include <asm/page.h>
+
+
+static inline int is_hugepage_only_range(struct mm_struct *mm,
+                                         unsigned long addr,
+                                         unsigned long len) {
+        return 0;
+}
+
+/*
+ * If the arch doesn't supply something else, assume that hugepage
+ * size aligned regions are ok without further preparation.
+ */
+static inline int prepare_hugepage_range(struct file *file,
+                        unsigned long addr, unsigned long len)
+{
+        if (len & ~HPAGE_MASK)
+                return -EINVAL;
+        if (addr & ~HPAGE_MASK)
+                return -EINVAL;
+        return 0;
+}
+
+static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm) {
+}
+
+static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
+                                          unsigned long addr, unsigned long end,
+                                          unsigned long floor,
+                                          unsigned long ceiling)
+{
+        free_pgd_range(tlb, addr, end, floor, ceiling);
+}
+
+static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+                                   pte_t *ptep, pte_t pte)
+{
+        set_pte_at(mm, addr, ptep, pte);
+}
+
+static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+                                            unsigned long addr, pte_t *ptep)
+{
+        return ptep_get_and_clear(mm, addr, ptep);
+}
+
+static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
+                                         unsigned long addr, pte_t *ptep)
+{
+}
+
+static inline int huge_pte_none(pte_t pte)
+{
+        return pte_none(pte);
+}
+
+static inline pte_t huge_pte_wrprotect(pte_t pte)
+{
+        return pte_wrprotect(pte);
+}
+
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+                                           unsigned long addr, pte_t *ptep)
+{
+        ptep_set_wrprotect(mm, addr, ptep);
+}
+
+static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+                                             unsigned long addr, pte_t *ptep,
+                                             pte_t pte, int dirty)
+{
+        return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+}
+
+static inline pte_t huge_ptep_get(pte_t *ptep)
+{
+        return *ptep;
+}
+
+static inline int arch_prepare_hugepage(struct page *page)
+{
+        return 0;
+}
+
+static inline void arch_release_hugepage(struct page *page)
+{
+}
+
+#endif /* _ASM_SH_HUGETLB_H */
diff --git a/arch/sh/include/asm/hw_irq.h b/arch/sh/include/asm/hw_irq.h
new file mode 100644
index 000000000000..d557b00111bf
--- /dev/null
+++ b/arch/sh/include/asm/hw_irq.h
@@ -0,0 +1,123 @@
+#ifndef __ASM_SH_HW_IRQ_H
+#define __ASM_SH_HW_IRQ_H
+
+#include <linux/init.h>
+#include <asm/atomic.h>
+
+extern atomic_t irq_err_count;
+
+struct ipr_data {
+        unsigned char irq;
+        unsigned char ipr_idx;          /* Index for the IPR registered */
+        unsigned char shift;            /* Number of bits to shift the data */
+        unsigned char priority;         /* The priority */
+};
+
+struct ipr_desc {
+        unsigned long *ipr_offsets;
+        unsigned int nr_offsets;
+        struct ipr_data *ipr_data;
+        unsigned int nr_irqs;
+        struct irq_chip chip;
+};
+
+void register_ipr_controller(struct ipr_desc *);
+
+typedef unsigned char intc_enum;
+
+struct intc_vect {
+        intc_enum enum_id;
+        unsigned short vect;
+};
+
+#define INTC_VECT(enum_id, vect) { enum_id, vect }
+#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
+
+struct intc_group {
+        intc_enum enum_id;
+        intc_enum enum_ids[32];
+};
+
+#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
+
+struct intc_mask_reg {
+        unsigned long set_reg, clr_reg, reg_width;
+        intc_enum enum_ids[32];
+#ifdef CONFIG_SMP
+        unsigned long smp;
+#endif
+};
+
+struct intc_prio_reg {
+        unsigned long set_reg, clr_reg, reg_width, field_width;
+        intc_enum enum_ids[16];
+#ifdef CONFIG_SMP
+        unsigned long smp;
+#endif
+};
+
+struct intc_sense_reg {
+        unsigned long reg, reg_width, field_width;
+        intc_enum enum_ids[16];
+};
+
+#ifdef CONFIG_SMP
+#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8)
+#else
+#define INTC_SMP(stride, nr)
+#endif
+
+struct intc_desc {
+        struct intc_vect *vectors;
+        unsigned int nr_vectors;
+        struct intc_group *groups;
+        unsigned int nr_groups;
+        struct intc_mask_reg *mask_regs;
+        unsigned int nr_mask_regs;
+        struct intc_prio_reg *prio_regs;
+        unsigned int nr_prio_regs;
+        struct intc_sense_reg *sense_regs;
+        unsigned int nr_sense_regs;
+        char *name;
+#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
+        struct intc_mask_reg *ack_regs;
+        unsigned int nr_ack_regs;
+#endif
+};
+
+#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
+#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups,            \
+        mask_regs, prio_regs, sense_regs)                               \
+struct intc_desc symbol __initdata = {                                  \
+        _INTC_ARRAY(vectors), _INTC_ARRAY(groups),                      \
+        _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),                 \
+        _INTC_ARRAY(sense_regs),                                        \
+        chipname,                                                       \
+}
+
+#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
+#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups,        \
+        mask_regs, prio_regs, sense_regs, ack_regs)                     \
+struct intc_desc symbol __initdata = {                                  \
+        _INTC_ARRAY(vectors), _INTC_ARRAY(groups),                      \
+        _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),                 \
+        _INTC_ARRAY(sense_regs),                                        \
+        chipname,                                                       \
+        _INTC_ARRAY(ack_regs),                                          \
+}
+#endif
+
+void __init register_intc_controller(struct intc_desc *desc);
+int intc_set_priority(unsigned int irq, unsigned int prio);
+
+void __init plat_irq_setup(void);
+#ifdef CONFIG_CPU_SH3
+void __init plat_irq_setup_sh3(void);
+#endif
+
+enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
+       IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
+       IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
+void __init plat_irq_setup_pins(int mode);
+
+#endif /* __ASM_SH_HW_IRQ_H */
diff --git a/arch/sh/include/asm/i2c-sh7760.h b/arch/sh/include/asm/i2c-sh7760.h
new file mode 100644
index 000000000000..24182116711f
--- /dev/null
+++ b/arch/sh/include/asm/i2c-sh7760.h
@@ -0,0 +1,22 @@
+/*
+ * MMIO/IRQ and platform data for SH7760 I2C channels
+ */
+
+#ifndef _I2C_SH7760_H_
+#define _I2C_SH7760_H_
+
+#define SH7760_I2C_DEVNAME      "sh7760-i2c"
+
+#define SH7760_I2C0_MMIO        0xFE140000
+#define SH7760_I2C0_MMIOEND     0xFE14003B
+#define SH7760_I2C0_IRQ         62
+
+#define SH7760_I2C1_MMIO        0xFE150000
+#define SH7760_I2C1_MMIOEND     0xFE15003B
+#define SH7760_I2C1_IRQ         63
+
+struct sh7760_i2c_platdata {
+        unsigned int speed_khz;
+};
+
+#endif
diff --git a/arch/sh/include/asm/ilsel.h b/arch/sh/include/asm/ilsel.h
new file mode 100644
index 000000000000..e3d304b280f6
--- /dev/null
+++ b/arch/sh/include/asm/ilsel.h
@@ -0,0 +1,45 @@
+#ifndef __ASM_SH_ILSEL_H
+#define __ASM_SH_ILSEL_H
+
+typedef enum {
+        ILSEL_NONE,
+        ILSEL_LAN,
+        ILSEL_USBH_I,
+        ILSEL_USBH_S,
+        ILSEL_USBH_V,
+        ILSEL_RTC,
+        ILSEL_USBP_I,
+        ILSEL_USBP_S,
+        ILSEL_USBP_V,
+        ILSEL_KEY,
+
+        /*
+         * ILSEL Aliases - corner cases for interleaved level tables.
+         *
+         * Someone thought this was a good idea and less hassle than
+         * demuxing a shared vector, really.
+         */
+
+        /* ILSEL0 and 2 */
+        ILSEL_FPGA0,
+        ILSEL_FPGA1,
+        ILSEL_EX1,
+        ILSEL_EX2,
+        ILSEL_EX3,
+        ILSEL_EX4,
+
+        /* ILSEL1 and 3 */
+        ILSEL_FPGA2 = ILSEL_FPGA0,
+        ILSEL_FPGA3 = ILSEL_FPGA1,
+        ILSEL_EX5 = ILSEL_EX1,
+        ILSEL_EX6 = ILSEL_EX2,
+        ILSEL_EX7 = ILSEL_EX3,
+        ILSEL_EX8 = ILSEL_EX4,
+} ilsel_source_t;
+
+/* arch/sh/boards/renesas/x3proto/ilsel.c */
+int ilsel_enable(ilsel_source_t set);
+int ilsel_enable_fixed(ilsel_source_t set, unsigned int level);
+void ilsel_disable(unsigned int irq);
+
+#endif /* __ASM_SH_ILSEL_H */
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
new file mode 100644
index 000000000000..a4fbf0c84fb1
--- /dev/null
+++ b/arch/sh/include/asm/io.h
@@ -0,0 +1,366 @@
+#ifndef __ASM_SH_IO_H
+#define __ASM_SH_IO_H
+
+/*
+ * Convention:
+ *    read{b,w,l}/write{b,w,l} are for PCI,
+ *    while in{b,w,l}/out{b,w,l} are for ISA
+ * These may (will) be platform specific function.
+ * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
+ * and 'string' versions: ins{b,w,l}/outs{b,w,l}
+ * For read{b,w,l} and write{b,w,l} there are also __raw versions, which
+ * do not have a memory barrier after them.
+ *
+ * In addition, we have
+ *   ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O.
+ *   which are processor specific.
+ */
+
+/*
+ * We follow the Alpha convention here:
+ *  __inb expands to an inline function call (which calls via the mv)
+ *  _inb  is a real function call (note ___raw fns are _ version of __raw)
+ *  inb   by default expands to _inb, but the machine specific code may
+ *        define it to __inb if it chooses.
+ */
+#include <asm/cache.h>
+#include <asm/system.h>
+#include <asm/addrspace.h>
+#include <asm/machvec.h>
+#include <asm/pgtable.h>
+#include <asm-generic/iomap.h>
+
+#ifdef __KERNEL__
+
+/*
+ * Depending on which platform we are running on, we need different
+ * I/O functions.
+ */
+#define __IO_PREFIX     generic
+#include <asm/io_generic.h>
+#include <asm/io_trapped.h>
+
+#define maybebadio(port) \
+  printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
+         __FUNCTION__, __LINE__, (port), (u32)__builtin_return_address(0))
+
+/*
+ * Since boards are able to define their own set of I/O routines through
+ * their respective machine vector, we always wrap through the mv.
+ *
+ * Also, in the event that a board hasn't provided its own definition for
+ * a given routine, it will be wrapped to generic code at run-time.
+ */
+
+#define __inb(p)        sh_mv.mv_inb((p))
+#define __inw(p)        sh_mv.mv_inw((p))
+#define __inl(p)        sh_mv.mv_inl((p))
+#define __outb(x,p)     sh_mv.mv_outb((x),(p))
+#define __outw(x,p)     sh_mv.mv_outw((x),(p))
+#define __outl(x,p)     sh_mv.mv_outl((x),(p))
+
+#define __inb_p(p)      sh_mv.mv_inb_p((p))
+#define __inw_p(p)      sh_mv.mv_inw_p((p))
+#define __inl_p(p)      sh_mv.mv_inl_p((p))
+#define __outb_p(x,p)   sh_mv.mv_outb_p((x),(p))
+#define __outw_p(x,p)   sh_mv.mv_outw_p((x),(p))
+#define __outl_p(x,p)   sh_mv.mv_outl_p((x),(p))
+
+#define __insb(p,b,c)   sh_mv.mv_insb((p), (b), (c))
+#define __insw(p,b,c)   sh_mv.mv_insw((p), (b), (c))
+#define __insl(p,b,c)   sh_mv.mv_insl((p), (b), (c))
+#define __outsb(p,b,c)  sh_mv.mv_outsb((p), (b), (c))
+#define __outsw(p,b,c)  sh_mv.mv_outsw((p), (b), (c))
+#define __outsl(p,b,c)  sh_mv.mv_outsl((p), (b), (c))
+
+#define __readb(a)      sh_mv.mv_readb((a))
+#define __readw(a)      sh_mv.mv_readw((a))
+#define __readl(a)      sh_mv.mv_readl((a))
+#define __writeb(v,a)   sh_mv.mv_writeb((v),(a))
+#define __writew(v,a)   sh_mv.mv_writew((v),(a))
+#define __writel(v,a)   sh_mv.mv_writel((v),(a))
+
+#define inb             __inb
+#define inw             __inw
+#define inl             __inl
+#define outb            __outb
+#define outw            __outw
+#define outl            __outl
+
+#define inb_p           __inb_p
+#define inw_p           __inw_p
+#define inl_p           __inl_p
+#define outb_p          __outb_p
+#define outw_p          __outw_p
+#define outl_p          __outl_p
+
+#define insb            __insb
+#define insw            __insw
+#define insl            __insl
+#define outsb           __outsb
+#define outsw           __outsw
+#define outsl           __outsl
+
+#define __raw_readb(a)          __readb((void __iomem *)(a))
+#define __raw_readw(a)          __readw((void __iomem *)(a))
+#define __raw_readl(a)          __readl((void __iomem *)(a))
+#define __raw_writeb(v, a)      __writeb(v, (void __iomem *)(a))
+#define __raw_writew(v, a)      __writew(v, (void __iomem *)(a))
+#define __raw_writel(v, a)      __writel(v, (void __iomem *)(a))
+
+void __raw_writesl(unsigned long addr, const void *data, int longlen);
+void __raw_readsl(unsigned long addr, void *data, int longlen);
+
+/*
+ * The platform header files may define some of these macros to use
+ * the inlined versions where appropriate.  These macros may also be
+ * redefined by userlevel programs.
+ */
+#ifdef __readb
+# define readb(a)       ({ unsigned int r_ = __raw_readb(a); mb(); r_; })
+#endif
+#ifdef __raw_readw
+# define readw(a)       ({ unsigned int r_ = __raw_readw(a); mb(); r_; })
+#endif
+#ifdef __raw_readl
+# define readl(a)       ({ unsigned int r_ = __raw_readl(a); mb(); r_; })
+#endif
+
+#ifdef __raw_writeb
+# define writeb(v,a)    ({ __raw_writeb((v),(a)); mb(); })
+#endif
+#ifdef __raw_writew
+# define writew(v,a)    ({ __raw_writew((v),(a)); mb(); })
+#endif
+#ifdef __raw_writel
+# define writel(v,a)    ({ __raw_writel((v),(a)); mb(); })
+#endif
+
+#define __BUILD_MEMORY_STRING(bwlq, type)                               \
+                                                                        \
+static inline void writes##bwlq(volatile void __iomem *mem,             \
+                                const void *addr, unsigned int count)   \
+{                                                                       \
+        const volatile type *__addr = addr;                             \
+                                                                        \
+        while (count--) {                                               \
+                __raw_write##bwlq(*__addr, mem);                        \
+                __addr++;                                               \
+        }                                                               \
+}                                                                       \
+                                                                        \
+static inline void reads##bwlq(volatile void __iomem *mem, void *addr,  \
+                               unsigned int count)                      \
+{                                                                       \
+        volatile type *__addr = addr;                                   \
+                                                                        \
+        while (count--) {                                               \
+                *__addr = __raw_read##bwlq(mem);                        \
+                __addr++;                                               \
+        }                                                               \
+}
+
+__BUILD_MEMORY_STRING(b, u8)
+__BUILD_MEMORY_STRING(w, u16)
+#define writesl __raw_writesl
+#define readsl  __raw_readsl
+
+#define readb_relaxed(a) readb(a)
+#define readw_relaxed(a) readw(a)
+#define readl_relaxed(a) readl(a)
+
+/* Simple MMIO */
+#define ioread8(a)              readb(a)
+#define ioread16(a)             readw(a)
+#define ioread16be(a)           be16_to_cpu(__raw_readw((a)))
+#define ioread32(a)             readl(a)
+#define ioread32be(a)           be32_to_cpu(__raw_readl((a)))
+
+#define iowrite8(v,a)           writeb((v),(a))
+#define iowrite16(v,a)          writew((v),(a))
+#define iowrite16be(v,a)        __raw_writew(cpu_to_be16((v)),(a))
+#define iowrite32(v,a)          writel((v),(a))
+#define iowrite32be(v,a)        __raw_writel(cpu_to_be32((v)),(a))
+
+#define ioread8_rep(a, d, c)    readsb((a), (d), (c))
+#define ioread16_rep(a, d, c)   readsw((a), (d), (c))
+#define ioread32_rep(a, d, c)   readsl((a), (d), (c))
+
+#define iowrite8_rep(a, s, c)   writesb((a), (s), (c))
+#define iowrite16_rep(a, s, c)  writesw((a), (s), (c))
+#define iowrite32_rep(a, s, c)  writesl((a), (s), (c))
+
+#define mmiowb()        wmb()   /* synco on SH-4A, otherwise a nop */
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * This function provides a method for the generic case where a board-specific
+ * ioport_map simply needs to return the port + some arbitrary port base.
+ *
+ * We use this at board setup time to implicitly set the port base, and
+ * as a result, we can use the generic ioport_map.
+ */
+static inline void __set_io_port_base(unsigned long pbase)
+{
+        extern unsigned long generic_io_base;
+
+        generic_io_base = pbase;
+}
+
+#define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
+
+/* We really want to try and get these to memcpy etc */
+extern void memcpy_fromio(void *, volatile void __iomem *, unsigned long);
+extern void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
+extern void memset_io(volatile void __iomem *, int, unsigned long);
+
+/* SuperH on-chip I/O functions */
+static inline unsigned char ctrl_inb(unsigned long addr)
+{
+        return *(volatile unsigned char*)addr;
+}
+
+static inline unsigned short ctrl_inw(unsigned long addr)
+{
+        return *(volatile unsigned short*)addr;
+}
+
+static inline unsigned int ctrl_inl(unsigned long addr)
+{
+        return *(volatile unsigned long*)addr;
+}
+
+static inline unsigned long long ctrl_inq(unsigned long addr)
+{
+        return *(volatile unsigned long long*)addr;
+}
+
+static inline void ctrl_outb(unsigned char b, unsigned long addr)
+{
+        *(volatile unsigned char*)addr = b;
+}
+
+static inline void ctrl_outw(unsigned short b, unsigned long addr)
+{
+        *(volatile unsigned short*)addr = b;
+}
+
+static inline void ctrl_outl(unsigned int b, unsigned long addr)
+{
+        *(volatile unsigned long*)addr = b;
+}
+
+static inline void ctrl_outq(unsigned long long b, unsigned long addr)
+{
+        *(volatile unsigned long long*)addr = b;
+}
+
+static inline void ctrl_delay(void)
+{
+#ifdef P2SEG
+        ctrl_inw(P2SEG);
+#endif
+}
+
+/* Quad-word real-mode I/O, don't ask.. */
+unsigned long long peek_real_address_q(unsigned long long addr);
+unsigned long long poke_real_address_q(unsigned long long addr,
+                                       unsigned long long val);
+
+#if !defined(CONFIG_MMU)
+#define virt_to_phys(address)   ((unsigned long)(address))
+#define phys_to_virt(address)   ((void *)(address))
+#else
+#define virt_to_phys(address)   (__pa(address))
+#define phys_to_virt(address)   (__va(address))
+#endif
+
+/*
+ * On 32-bit SH, we traditionally have the whole physical address space
+ * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
+ * not need to do anything but place the address in the proper segment.
+ * This is true for P1 and P2 addresses, as well as some P3 ones.
+ * However, most of the P3 addresses and newer cores using extended
+ * addressing need to map through page tables, so the ioremap()
+ * implementation becomes a bit more complicated.
+ *
+ * See arch/sh/mm/ioremap.c for additional notes on this.
+ *
+ * We cheat a bit and always return uncachable areas until we've fixed
+ * the drivers to handle caching properly.
+ *
+ * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
+ * doesn't exist, so everything must go through page tables.
+ */
+#ifdef CONFIG_MMU
+void __iomem *__ioremap(unsigned long offset, unsigned long size,
+                        unsigned long flags);
+void __iounmap(void __iomem *addr);
+
+/* arch/sh/mm/ioremap_64.c */
+unsigned long onchip_remap(unsigned long addr, unsigned long size,
+                           const char *name);
+extern void onchip_unmap(unsigned long vaddr);
+#else
+#define __ioremap(offset, size, flags)  ((void __iomem *)(offset))
+#define __iounmap(addr)                 do { } while (0)
+#define onchip_remap(addr, size, name)  (addr)
+#define onchip_unmap(addr)              do { } while (0)
+#endif /* CONFIG_MMU */
+
+static inline void __iomem *
+__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
+{
+#ifdef CONFIG_SUPERH32
+        unsigned long last_addr = offset + size - 1;
+#endif
+        void __iomem *ret;
+
+        ret = __ioremap_trapped(offset, size);
+        if (ret)
+                return ret;
+
+#ifdef CONFIG_SUPERH32
+        /*
+         * For P1 and P2 space this is trivial, as everything is already
+         * mapped. Uncached access for P1 addresses are done through P2.
+         * In the P3 case or for addresses outside of the 29-bit space,
+         * mapping must be done by the PMB or by using page tables.
+         */
+        if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
+                if (unlikely(flags & _PAGE_CACHABLE))
+                        return (void __iomem *)P1SEGADDR(offset);
+
+                return (void __iomem *)P2SEGADDR(offset);
+        }
+#endif
+
+        return __ioremap(offset, size, flags);
+}
+
+#define ioremap(offset, size)                           \
+        __ioremap_mode((offset), (size), 0)
+#define ioremap_nocache(offset, size)                   \
+        __ioremap_mode((offset), (size), 0)
+#define ioremap_cache(offset, size)                     \
+        __ioremap_mode((offset), (size), _PAGE_CACHABLE)
+#define p3_ioremap(offset, size, flags)                 \
+        __ioremap((offset), (size), (flags))
+#define iounmap(addr)                                   \
+        __iounmap((addr))
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p)    __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p)   p
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_IO_H */
diff --git a/arch/sh/include/asm/io_generic.h b/arch/sh/include/asm/io_generic.h
new file mode 100644
index 000000000000..92fc6070d7b3
--- /dev/null
+++ b/arch/sh/include/asm/io_generic.h
@@ -0,0 +1,49 @@
+/*
+ * Trivial I/O routine definitions, intentionally meant to be included
+ * multiple times. Ugly I/O routine concatenation helpers taken from
+ * alpha. Must be included _before_ io.h to avoid preprocessor-induced
+ * routine mismatch.
+ */
+#define IO_CONCAT(a,b)  _IO_CONCAT(a,b)
+#define _IO_CONCAT(a,b) a ## _ ## b
+
+#ifndef __IO_PREFIX
+#error "Don't include this header without a valid system prefix"
+#endif
+
+u8 IO_CONCAT(__IO_PREFIX,inb)(unsigned long);
+u16 IO_CONCAT(__IO_PREFIX,inw)(unsigned long);
+u32 IO_CONCAT(__IO_PREFIX,inl)(unsigned long);
+
+void IO_CONCAT(__IO_PREFIX,outb)(u8, unsigned long);
+void IO_CONCAT(__IO_PREFIX,outw)(u16, unsigned long);
+void IO_CONCAT(__IO_PREFIX,outl)(u32, unsigned long);
+
+u8 IO_CONCAT(__IO_PREFIX,inb_p)(unsigned long);
+u16 IO_CONCAT(__IO_PREFIX,inw_p)(unsigned long);
+u32 IO_CONCAT(__IO_PREFIX,inl_p)(unsigned long);
+void IO_CONCAT(__IO_PREFIX,outb_p)(u8, unsigned long);
+void IO_CONCAT(__IO_PREFIX,outw_p)(u16, unsigned long);
+void IO_CONCAT(__IO_PREFIX,outl_p)(u32, unsigned long);
+
+void IO_CONCAT(__IO_PREFIX,insb)(unsigned long, void *dst, unsigned long count);
+void IO_CONCAT(__IO_PREFIX,insw)(unsigned long, void *dst, unsigned long count);
+void IO_CONCAT(__IO_PREFIX,insl)(unsigned long, void *dst, unsigned long count);
+void IO_CONCAT(__IO_PREFIX,outsb)(unsigned long, const void *src, unsigned long count);
+void IO_CONCAT(__IO_PREFIX,outsw)(unsigned long, const void *src, unsigned long count);
+void IO_CONCAT(__IO_PREFIX,outsl)(unsigned long, const void *src, unsigned long count);
+
+u8 IO_CONCAT(__IO_PREFIX,readb)(void __iomem *);
+u16 IO_CONCAT(__IO_PREFIX,readw)(void __iomem *);
+u32 IO_CONCAT(__IO_PREFIX,readl)(void __iomem *);
+void IO_CONCAT(__IO_PREFIX,writeb)(u8, void __iomem *);
+void IO_CONCAT(__IO_PREFIX,writew)(u16, void __iomem *);
+void IO_CONCAT(__IO_PREFIX,writel)(u32, void __iomem *);
+
+void *IO_CONCAT(__IO_PREFIX,ioremap)(unsigned long offset, unsigned long size);
+void IO_CONCAT(__IO_PREFIX,iounmap)(void *addr);
+
+void __iomem *IO_CONCAT(__IO_PREFIX,ioport_map)(unsigned long addr, unsigned int size);
+void IO_CONCAT(__IO_PREFIX,ioport_unmap)(void __iomem *addr);
+
+#undef __IO_PREFIX
diff --git a/arch/sh/include/asm/io_trapped.h b/arch/sh/include/asm/io_trapped.h
new file mode 100644
index 000000000000..f1251d4f0ba9
--- /dev/null
+++ b/arch/sh/include/asm/io_trapped.h
@@ -0,0 +1,58 @@
+#ifndef __ASM_SH_IO_TRAPPED_H
+#define __ASM_SH_IO_TRAPPED_H
+
+#include <linux/list.h>
+#include <linux/ioport.h>
+#include <asm/page.h>
+
+#define IO_TRAPPED_MAGIC 0xfeedbeef
+
+struct trapped_io {
+        unsigned int magic;
+        struct resource *resource;
+        unsigned int num_resources;
+        unsigned int minimum_bus_width;
+        struct list_head list;
+        void __iomem *virt_base;
+} __aligned(PAGE_SIZE);
+
+#ifdef CONFIG_IO_TRAPPED
+int register_trapped_io(struct trapped_io *tiop);
+int handle_trapped_io(struct pt_regs *regs, unsigned long address);
+
+void __iomem *match_trapped_io_handler(struct list_head *list,
+                                       unsigned long offset,
+                                       unsigned long size);
+
+#ifdef CONFIG_HAS_IOMEM
+extern struct list_head trapped_mem;
+
+static inline void __iomem *
+__ioremap_trapped(unsigned long offset, unsigned long size)
+{
+        return match_trapped_io_handler(&trapped_mem, offset, size);
+}
+#else
+#define __ioremap_trapped(offset, size) NULL
+#endif
+
+#ifdef CONFIG_HAS_IOPORT
+extern struct list_head trapped_io;
+
+static inline void __iomem *
+__ioport_map_trapped(unsigned long offset, unsigned long size)
+{
+        return match_trapped_io_handler(&trapped_io, offset, size);
+}
+#else
+#define __ioport_map_trapped(offset, size) NULL
+#endif
+
+#else
+#define register_trapped_io(tiop) (-1)
+#define handle_trapped_io(tiop, address) 0
+#define __ioremap_trapped(offset, size) NULL
+#define __ioport_map_trapped(offset, size) NULL
+#endif
+
+#endif /* __ASM_SH_IO_TRAPPED_H */
diff --git a/arch/sh/include/asm/ioctl.h b/arch/sh/include/asm/ioctl.h
new file mode 100644
index 000000000000..b279fe06dfe5
--- /dev/null
+++ b/arch/sh/include/asm/ioctl.h
@@ -0,0 +1 @@
+#include <asm-generic/ioctl.h>
diff --git a/arch/sh/include/asm/ioctls.h b/arch/sh/include/asm/ioctls.h
new file mode 100644
index 000000000000..c212c371a4a5
--- /dev/null
+++ b/arch/sh/include/asm/ioctls.h
@@ -0,0 +1,103 @@
+#ifndef __ASM_SH_IOCTLS_H
+#define __ASM_SH_IOCTLS_H
+
+#include <asm/ioctl.h>
+
+#define FIOCLEX         _IO('f', 1)
+#define FIONCLEX        _IO('f', 2)
+#define FIOASYNC        _IOW('f', 125, int)
+#define FIONBIO         _IOW('f', 126, int)
+#define FIONREAD        _IOR('f', 127, int)
+#define TIOCINQ         FIONREAD
+#define FIOQSIZE        _IOR('f', 128, loff_t)
+
+#define TCGETS          0x5401
+#define TCSETS          0x5402
+#define TCSETSW         0x5403
+#define TCSETSF         0x5404
+
+#define TCGETA          0x80127417      /* _IOR('t', 23, struct termio) */
+#define TCSETA          0x40127418      /* _IOW('t', 24, struct termio) */
+#define TCSETAW         0x40127419      /* _IOW('t', 25, struct termio) */
+#define TCSETAF         0x4012741C      /* _IOW('t', 28, struct termio) */
+
+#define TCSBRK          _IO('t', 29)
+#define TCXONC          _IO('t', 30)
+#define TCFLSH          _IO('t', 31)
+
+#define TIOCSWINSZ      0x40087467      /* _IOW('t', 103, struct winsize) */
+#define TIOCGWINSZ      0x80087468      /* _IOR('t', 104, struct winsize) */
+#define TIOCSTART       _IO('t', 110)           /* start output, like ^Q */
+#define TIOCSTOP        _IO('t', 111)           /* stop output, like ^S */
+#define TIOCOUTQ        _IOR('t', 115, int)     /* output queue size */
+
+#define TIOCSPGRP       _IOW('t', 118, int)
+#define TIOCGPGRP       _IOR('t', 119, int)
+
+#define TIOCEXCL        _IO('T', 12) /* 0x540C */
+#define TIOCNXCL        _IO('T', 13) /* 0x540D */
+#define TIOCSCTTY       _IO('T', 14) /* 0x540E */
+
+#define TIOCSTI         _IOW('T', 18, char) /* 0x5412 */
+#define TIOCMGET        _IOR('T', 21, unsigned int) /* 0x5415 */
+#define TIOCMBIS        _IOW('T', 22, unsigned int) /* 0x5416 */
+#define TIOCMBIC        _IOW('T', 23, unsigned int) /* 0x5417 */
+#define TIOCMSET        _IOW('T', 24, unsigned int) /* 0x5418 */
+# define TIOCM_LE       0x001
+# define TIOCM_DTR      0x002
+# define TIOCM_RTS      0x004
+# define TIOCM_ST       0x008
+# define TIOCM_SR       0x010
+# define TIOCM_CTS      0x020
+# define TIOCM_CAR      0x040
+# define TIOCM_RNG      0x080
+# define TIOCM_DSR      0x100
+# define TIOCM_CD       TIOCM_CAR
+# define TIOCM_RI       TIOCM_RNG
+
+#define TIOCGSOFTCAR    _IOR('T', 25, unsigned int) /* 0x5419 */
+#define TIOCSSOFTCAR    _IOW('T', 26, unsigned int) /* 0x541A */
+#define TIOCLINUX       _IOW('T', 28, char) /* 0x541C */
+#define TIOCCONS        _IO('T', 29) /* 0x541D */
+#define TIOCGSERIAL     0x803C541E      /* _IOR('T', 30, struct serial_struct) 0x541E */
+#define TIOCSSERIAL     0x403C541F      /* _IOW('T', 31, struct serial_struct) 0x541F */
+#define TIOCPKT         _IOW('T', 32, int) /* 0x5420 */
+# define TIOCPKT_DATA            0
+# define TIOCPKT_FLUSHREAD       1
+# define TIOCPKT_FLUSHWRITE      2
+# define TIOCPKT_STOP            4
+# define TIOCPKT_START           8
+# define TIOCPKT_NOSTOP         16
+# define TIOCPKT_DOSTOP         32
+
+
+#define TIOCNOTTY       _IO('T', 34) /* 0x5422 */
+#define TIOCSETD        _IOW('T', 35, int) /* 0x5423 */
+#define TIOCGETD        _IOR('T', 36, int) /* 0x5424 */
+#define TCSBRKP         _IOW('T', 37, int) /* 0x5425 */ /* Needed for POSIX tcsendbreak() */
+#define TIOCSBRK        _IO('T', 39) /* 0x5427 */ /* BSD compatibility */
+#define TIOCCBRK        _IO('T', 40) /* 0x5428 */ /* BSD compatibility */
+#define TIOCGSID        _IOR('T', 41, pid_t) /* 0x5429 */ /* Return the session ID of FD */
+#define TCGETS2         _IOR('T', 42, struct termios2)
+#define TCSETS2         _IOW('T', 43, struct termios2)
+#define TCSETSW2        _IOW('T', 44, struct termios2)
+#define TCSETSF2        _IOW('T', 45, struct termios2)
+#define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
+#define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+
+#define TIOCSERCONFIG   _IO('T', 83) /* 0x5453 */
+#define TIOCSERGWILD    _IOR('T', 84,  int) /* 0x5454 */
+#define TIOCSERSWILD    _IOW('T', 85,  int) /* 0x5455 */
+#define TIOCGLCKTRMIOS  0x5456
+#define TIOCSLCKTRMIOS  0x5457
+#define TIOCSERGSTRUCT  0x80d85458      /* _IOR('T', 88, struct async_struct) 0x5458 */ /* For debugging only */
+#define TIOCSERGETLSR   _IOR('T', 89, unsigned int) /* 0x5459 */ /* Get line status register */
+  /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+# define TIOCSER_TEMT    0x01   /* Transmitter physically empty */
+#define TIOCSERGETMULTI 0x80A8545A      /* _IOR('T', 90, struct serial_multiport_struct) 0x545A */ /* Get multiport config */
+#define TIOCSERSETMULTI 0x40A8545B      /* _IOW('T', 91, struct serial_multiport_struct) 0x545B */ /* Set multiport config */
+
+#define TIOCMIWAIT      _IO('T', 92) /* 0x545C */       /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
+
+#endif /* __ASM_SH_IOCTLS_H */
diff --git a/arch/sh/include/asm/ipcbuf.h b/arch/sh/include/asm/ipcbuf.h
new file mode 100644
index 000000000000..5ffc9972a7ea
--- /dev/null
+++ b/arch/sh/include/asm/ipcbuf.h
@@ -0,0 +1,29 @@
+#ifndef __ASM_SH_IPCBUF_H__
+#define __ASM_SH_IPCBUF_H__
+
+/*
+ * The ipc64_perm structure for i386 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit mode_t and seq
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct ipc64_perm
+{
+        __kernel_key_t          key;
+        __kernel_uid32_t        uid;
+        __kernel_gid32_t        gid;
+        __kernel_uid32_t        cuid;
+        __kernel_gid32_t        cgid;
+        __kernel_mode_t         mode;
+        unsigned short          __pad1;
+        unsigned short          seq;
+        unsigned short          __pad2;
+        unsigned long           __unused1;
+        unsigned long           __unused2;
+};
+
+#endif /* __ASM_SH_IPCBUF_H__ */
diff --git a/arch/sh/include/asm/irq.h b/arch/sh/include/asm/irq.h
new file mode 100644
index 000000000000..6195a531c1b0
--- /dev/null
+++ b/arch/sh/include/asm/irq.h
@@ -0,0 +1,57 @@
+#ifndef __ASM_SH_IRQ_H
+#define __ASM_SH_IRQ_H
+
+#include <asm/machvec.h>
+
+/*
+ * A sane default based on a reasonable vector table size, platforms are
+ * advised to cap this at the hard limit that they're interested in
+ * through the machvec.
+ */
+#define NR_IRQS 256
+
+/*
+ * Convert back and forth between INTEVT and IRQ values.
+ */
+#ifdef CONFIG_CPU_HAS_INTEVT
+#define evt2irq(evt)            (((evt) >> 5) - 16)
+#define irq2evt(irq)            (((irq) + 16) << 5)
+#else
+#define evt2irq(evt)            (evt)
+#define irq2evt(irq)            (irq)
+#endif
+
+/*
+ * Simple Mask Register Support
+ */
+extern void make_maskreg_irq(unsigned int irq);
+extern unsigned short *irq_mask_register;
+
+/*
+ * PINT IRQs
+ */
+void init_IRQ_pint(void);
+void make_imask_irq(unsigned int irq);
+
+static inline int generic_irq_demux(int irq)
+{
+        return irq;
+}
+
+#define irq_canonicalize(irq)   (irq)
+#define irq_demux(irq)          sh_mv.mv_irq_demux(irq)
+
+#ifdef CONFIG_IRQSTACKS
+extern void irq_ctx_init(int cpu);
+extern void irq_ctx_exit(int cpu);
+# define __ARCH_HAS_DO_SOFTIRQ
+#else
+# define irq_ctx_init(cpu) do { } while (0)
+# define irq_ctx_exit(cpu) do { } while (0)
+#endif
+
+#ifdef CONFIG_CPU_SH5
+#include <cpu/irq.h>
+#endif
+
+#endif /* __ASM_SH_IRQ_H */
diff --git a/arch/sh/include/asm/irq_regs.h b/arch/sh/include/asm/irq_regs.h
new file mode 100644
index 000000000000..3dd9c0b70270
--- /dev/null
+++ b/arch/sh/include/asm/irq_regs.h
@@ -0,0 +1 @@
+#include <asm-generic/irq_regs.h>
diff --git a/arch/sh/include/asm/irqflags.h b/arch/sh/include/asm/irqflags.h
new file mode 100644
index 000000000000..46e71da5be6b
--- /dev/null
+++ b/arch/sh/include/asm/irqflags.h
@@ -0,0 +1,34 @@
+#ifndef __ASM_SH_IRQFLAGS_H
+#define __ASM_SH_IRQFLAGS_H
+
+#ifdef CONFIG_SUPERH32
+#include "irqflags_32.h"
+#else
+#include "irqflags_64.h"
+#endif
+
+#define raw_local_save_flags(flags) \
+                do { (flags) = __raw_local_save_flags(); } while (0)
+
+static inline int raw_irqs_disabled_flags(unsigned long flags)
+{
+        return (flags != 0);
+}
+
+static inline int raw_irqs_disabled(void)
+{
+        unsigned long flags = __raw_local_save_flags();
+
+        return raw_irqs_disabled_flags(flags);
+}
+
+#define raw_local_irq_save(flags) \
+                do { (flags) = __raw_local_irq_save(); } while (0)
+
+static inline void raw_local_irq_restore(unsigned long flags)
+{
+        if ((flags & 0xf0) != 0xf0)
+                raw_local_irq_enable();
+}
+
+#endif /* __ASM_SH_IRQFLAGS_H */
diff --git a/arch/sh/include/asm/irqflags_32.h b/arch/sh/include/asm/irqflags_32.h
new file mode 100644
index 000000000000..60218f541340
--- /dev/null
+++ b/arch/sh/include/asm/irqflags_32.h
@@ -0,0 +1,99 @@
+#ifndef __ASM_SH_IRQFLAGS_32_H
+#define __ASM_SH_IRQFLAGS_32_H
+
+static inline void raw_local_irq_enable(void)
+{
+        unsigned long __dummy0, __dummy1;
+
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "and    %1, %0\n\t"
+#ifdef CONFIG_CPU_HAS_SR_RB
+                "stc    r6_bank, %1\n\t"
+                "or     %1, %0\n\t"
+#endif
+                "ldc    %0, sr\n\t"
+                : "=&r" (__dummy0), "=r" (__dummy1)
+                : "1" (~0x000000f0)
+                : "memory"
+        );
+}
+
+static inline void raw_local_irq_disable(void)
+{
+        unsigned long flags;
+
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "or     #0xf0, %0\n\t"
+                "ldc    %0, sr\n\t"
+                : "=&z" (flags)
+                : /* no inputs */
+                : "memory"
+        );
+}
+
+static inline void set_bl_bit(void)
+{
+        unsigned long __dummy0, __dummy1;
+
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "or     %2, %0\n\t"
+                "and    %3, %0\n\t"
+                "ldc    %0, sr\n\t"
+                : "=&r" (__dummy0), "=r" (__dummy1)
+                : "r" (0x10000000), "r" (0xffffff0f)
+                : "memory"
+        );
+}
+
+static inline void clear_bl_bit(void)
+{
+        unsigned long __dummy0, __dummy1;
+
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "and    %2, %0\n\t"
+                "ldc    %0, sr\n\t"
+                : "=&r" (__dummy0), "=r" (__dummy1)
+                : "1" (~0x10000000)
+                : "memory"
+        );
+}
+
+static inline unsigned long __raw_local_save_flags(void)
+{
+        unsigned long flags;
+
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "and    #0xf0, %0\n\t"
+                : "=&z" (flags)
+                : /* no inputs */
+                : "memory"
+        );
+
+        return flags;
+}
+
+static inline unsigned long __raw_local_irq_save(void)
+{
+        unsigned long flags, __dummy;
+
+        __asm__ __volatile__ (
+                "stc    sr, %1\n\t"
+                "mov    %1, %0\n\t"
+                "or     #0xf0, %0\n\t"
+                "ldc    %0, sr\n\t"
+                "mov    %1, %0\n\t"
+                "and    #0xf0, %0\n\t"
+                : "=&z" (flags), "=&r" (__dummy)
+                : /* no inputs */
+                : "memory"
+        );
+
+        return flags;
+}
+
+#endif /* __ASM_SH_IRQFLAGS_32_H */
diff --git a/arch/sh/include/asm/irqflags_64.h b/arch/sh/include/asm/irqflags_64.h
new file mode 100644
index 000000000000..88f65222c1d4
--- /dev/null
+++ b/arch/sh/include/asm/irqflags_64.h
@@ -0,0 +1,85 @@
+#ifndef __ASM_SH_IRQFLAGS_64_H
+#define __ASM_SH_IRQFLAGS_64_H
+
+#include <cpu/registers.h>
+
+#define SR_MASK_LL      0x00000000000000f0LL
+#define SR_BL_LL        0x0000000010000000LL
+
+static inline void raw_local_irq_enable(void)
+{
+        unsigned long long __dummy0, __dummy1 = ~SR_MASK_LL;
+
+        __asm__ __volatile__("getcon    " __SR ", %0\n\t"
+                             "and       %0, %1, %0\n\t"
+                             "putcon    %0, " __SR "\n\t"
+                             : "=&r" (__dummy0)
+                             : "r" (__dummy1));
+}
+
+static inline void raw_local_irq_disable(void)
+{
+        unsigned long long __dummy0, __dummy1 = SR_MASK_LL;
+
+        __asm__ __volatile__("getcon    " __SR ", %0\n\t"
+                             "or        %0, %1, %0\n\t"
+                             "putcon    %0, " __SR "\n\t"
+                             : "=&r" (__dummy0)
+                             : "r" (__dummy1));
+}
+
+static inline void set_bl_bit(void)
+{
+        unsigned long long __dummy0, __dummy1 = SR_BL_LL;
+
+        __asm__ __volatile__("getcon    " __SR ", %0\n\t"
+                             "or        %0, %1, %0\n\t"
+                             "putcon    %0, " __SR "\n\t"
+                             : "=&r" (__dummy0)
+                             : "r" (__dummy1));
+
+}
+
+static inline void clear_bl_bit(void)
+{
+        unsigned long long __dummy0, __dummy1 = ~SR_BL_LL;
+
+        __asm__ __volatile__("getcon    " __SR ", %0\n\t"
+                             "and       %0, %1, %0\n\t"
+                             "putcon    %0, " __SR "\n\t"
+                             : "=&r" (__dummy0)
+                             : "r" (__dummy1));
+}
+
+static inline unsigned long __raw_local_save_flags(void)
+{
+        unsigned long long __dummy = SR_MASK_LL;
+        unsigned long flags;
+
+        __asm__ __volatile__ (
+                "getcon " __SR ", %0\n\t"
+                "and    %0, %1, %0"
+                : "=&r" (flags)
+                : "r" (__dummy));
+
+        return flags;
+}
+
+static inline unsigned long __raw_local_irq_save(void)
+{
+        unsigned long long __dummy0, __dummy1 = SR_MASK_LL;
+        unsigned long flags;
+
+        __asm__ __volatile__ (
+                "getcon " __SR ", %1\n\t"
+                "or     %1, r63, %0\n\t"
+                "or     %1, %2, %1\n\t"
+                "putcon %1, " __SR "\n\t"
+                "and    %0, %2, %0"
+                : "=&r" (flags), "=&r" (__dummy0)
+                : "r" (__dummy1));
+
+        return flags;
+}
+
+#endif /* __ASM_SH_IRQFLAGS_64_H */
diff --git a/arch/sh/include/asm/kdebug.h b/arch/sh/include/asm/kdebug.h
new file mode 100644
index 000000000000..49cd69051a88
--- /dev/null
+++ b/arch/sh/include/asm/kdebug.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_SH_KDEBUG_H
+#define __ASM_SH_KDEBUG_H
+
+/* Grossly misnamed. */
+enum die_val {
+        DIE_TRAP,
+};
+
+#endif /* __ASM_SH_KDEBUG_H */
diff --git a/arch/sh/include/asm/kexec.h b/arch/sh/include/asm/kexec.h
new file mode 100644
index 000000000000..00f4260ef09b
--- /dev/null
+++ b/arch/sh/include/asm/kexec.h
@@ -0,0 +1,62 @@
+#ifndef __ASM_SH_KEXEC_H
+#define __ASM_SH_KEXEC_H
+
+#include <asm/ptrace.h>
+#include <asm/string.h>
+
+/*
+ * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
+ * I.e. Maximum page that is mapped directly into kernel memory,
+ * and kmap is not required.
+ *
+ * Someone correct me if FIXADDR_START - PAGEOFFSET is not the correct
+ * calculation for the amount of memory directly mappable into the
+ * kernel memory space.
+ */
+
+/* Maximum physical address we can use pages from */
+#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
+/* Maximum address we can reach in physical address mode */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
+/* Maximum address we can use for the control code buffer */
+#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
+
+#define KEXEC_CONTROL_CODE_SIZE 4096
+
+/* The native architecture */
+#define KEXEC_ARCH KEXEC_ARCH_SH
+
+static inline void crash_setup_regs(struct pt_regs *newregs,
+                                    struct pt_regs *oldregs)
+{
+        if (oldregs)
+                memcpy(newregs, oldregs, sizeof(*newregs));
+        else {
+                __asm__ __volatile__ ("mov r0, %0" : "=r" (newregs->regs[0]));
+                __asm__ __volatile__ ("mov r1, %0" : "=r" (newregs->regs[1]));
+                __asm__ __volatile__ ("mov r2, %0" : "=r" (newregs->regs[2]));
+                __asm__ __volatile__ ("mov r3, %0" : "=r" (newregs->regs[3]));
+                __asm__ __volatile__ ("mov r4, %0" : "=r" (newregs->regs[4]));
+                __asm__ __volatile__ ("mov r5, %0" : "=r" (newregs->regs[5]));
+                __asm__ __volatile__ ("mov r6, %0" : "=r" (newregs->regs[6]));
+                __asm__ __volatile__ ("mov r7, %0" : "=r" (newregs->regs[7]));
+                __asm__ __volatile__ ("mov r8, %0" : "=r" (newregs->regs[8]));
+                __asm__ __volatile__ ("mov r9, %0" : "=r" (newregs->regs[9]));
+                __asm__ __volatile__ ("mov r10, %0" : "=r" (newregs->regs[10]));
+                __asm__ __volatile__ ("mov r11, %0" : "=r" (newregs->regs[11]));
+                __asm__ __volatile__ ("mov r12, %0" : "=r" (newregs->regs[12]));
+                __asm__ __volatile__ ("mov r13, %0" : "=r" (newregs->regs[13]));
+                __asm__ __volatile__ ("mov r14, %0" : "=r" (newregs->regs[14]));
+                __asm__ __volatile__ ("mov r15, %0" : "=r" (newregs->regs[15]));
+
+                __asm__ __volatile__ ("sts pr, %0" : "=r" (newregs->pr));
+                __asm__ __volatile__ ("sts macl, %0" : "=r" (newregs->macl));
+                __asm__ __volatile__ ("sts mach, %0" : "=r" (newregs->mach));
+
+                __asm__ __volatile__ ("stc gbr, %0" : "=r" (newregs->gbr));
+                __asm__ __volatile__ ("stc sr, %0" : "=r" (newregs->sr));
+
+                newregs->pc = (unsigned long)current_text_addr();
+        }
+}
+#endif /* __ASM_SH_KEXEC_H */
diff --git a/arch/sh/include/asm/kgdb.h b/arch/sh/include/asm/kgdb.h
new file mode 100644
index 000000000000..24e42078f36f
--- /dev/null
+++ b/arch/sh/include/asm/kgdb.h
@@ -0,0 +1,69 @@
+/*
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * Based on original code by Glenn Engel, Jim Kingdon,
+ * David Grothe <dave@gcom.com>, Tigran Aivazian, <tigran@sco.com> and
+ * Amit S. Kale <akale@veritas.com>
+ * 
+ * Super-H port based on sh-stub.c (Ben Lee and Steve Chamberlain) by
+ * Henry Bell <henry.bell@st.com>
+ * 
+ * Header file for low-level support for remote debug using GDB. 
+ *
+ */
+
+#ifndef __KGDB_H
+#define __KGDB_H
+
+#include <asm/ptrace.h>
+
+/* Same as pt_regs but has vbr in place of syscall_nr */
+struct kgdb_regs {
+        unsigned long regs[16];
+        unsigned long pc;
+        unsigned long pr;
+        unsigned long sr;
+        unsigned long gbr;
+        unsigned long mach;
+        unsigned long macl;
+        unsigned long vbr;
+};
+
+/* State info */
+extern char kgdb_in_gdb_mode;
+extern int kgdb_nofault;        /* Ignore bus errors (in gdb mem access) */
+extern char in_nmi;             /* Debounce flag to prevent NMI reentry*/
+
+/* SCI */
+extern int kgdb_portnum;
+extern int kgdb_baud;
+extern char kgdb_parity;
+extern char kgdb_bits;
+
+/* Init and interface stuff */
+extern int kgdb_init(void);
+extern int (*kgdb_getchar)(void);
+extern void (*kgdb_putchar)(int);
+
+/* Trap functions */
+typedef void (kgdb_debug_hook_t)(struct pt_regs *regs);
+typedef void (kgdb_bus_error_hook_t)(void);
+extern kgdb_debug_hook_t  *kgdb_debug_hook;
+extern kgdb_bus_error_hook_t *kgdb_bus_err_hook;
+
+/* Console */
+struct console;
+void kgdb_console_write(struct console *co, const char *s, unsigned count);
+extern int kgdb_console_setup(struct console *, char *);
+
+/* Prototypes for jmp fns */
+#define _JBLEN 9
+typedef        int jmp_buf[_JBLEN];
+extern void    longjmp(jmp_buf __jmpb, int __retval);
+extern int     setjmp(jmp_buf __jmpb);
+
+/* Forced breakpoint */
+#define breakpoint()    __asm__ __volatile__("trapa   #0x3c")
+
+#endif
diff --git a/arch/sh/include/asm/kmap_types.h b/arch/sh/include/asm/kmap_types.h
new file mode 100644
index 000000000000..84d565c696be
--- /dev/null
+++ b/arch/sh/include/asm/kmap_types.h
@@ -0,0 +1,32 @@
+#ifndef __SH_KMAP_TYPES_H
+#define __SH_KMAP_TYPES_H
+
+/* Dummy header just to define km_type. */
+
+
+#ifdef CONFIG_DEBUG_HIGHMEM
+# define D(n) __KM_FENCE_##n ,
+#else
+# define D(n)
+#endif
+
+enum km_type {
+D(0)    KM_BOUNCE_READ,
+D(1)    KM_SKB_SUNRPC_DATA,
+D(2)    KM_SKB_DATA_SOFTIRQ,
+D(3)    KM_USER0,
+D(4)    KM_USER1,
+D(5)    KM_BIO_SRC_IRQ,
+D(6)    KM_BIO_DST_IRQ,
+D(7)    KM_PTE0,
+D(8)    KM_PTE1,
+D(9)    KM_IRQ0,
+D(10)   KM_IRQ1,
+D(11)   KM_SOFTIRQ0,
+D(12)   KM_SOFTIRQ1,
+D(13)   KM_TYPE_NR
+};
+
+#undef D
+
+#endif
diff --git a/arch/sh/include/asm/lboxre2.h b/arch/sh/include/asm/lboxre2.h
new file mode 100644
index 000000000000..e6d160504923
--- /dev/null
+++ b/arch/sh/include/asm/lboxre2.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_SH_LBOXRE2_H
+#define __ASM_SH_LBOXRE2_H
+
+/*
+ * Copyright (C) 2007 Nobuhiro Iwamatsu
+ *
+ * NTT COMWARE L-BOX RE2 support
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#define IRQ_CF1         9       /* CF1 */
+#define IRQ_CF0         10      /* CF0 */
+#define IRQ_INTD        11      /* INTD */
+#define IRQ_ETH1        12      /* Ether1 */
+#define IRQ_ETH0        13      /* Ether0 */
+#define IRQ_INTA        14      /* INTA */
+
+void init_lboxre2_IRQ(void);
+
+#define __IO_PREFIX     lboxre2
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_LBOXRE2_H */
diff --git a/arch/sh/include/asm/linkage.h b/arch/sh/include/asm/linkage.h
new file mode 100644
index 000000000000..3565a4f4009f
--- /dev/null
+++ b/arch/sh/include/asm/linkage.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#define __ALIGN .balign 4
+#define __ALIGN_STR ".balign 4"
+
+#endif
diff --git a/arch/sh/include/asm/local.h b/arch/sh/include/asm/local.h
new file mode 100644
index 000000000000..9ed9b9cb459a
--- /dev/null
+++ b/arch/sh/include/asm/local.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_SH_LOCAL_H
+#define __ASM_SH_LOCAL_H
+
+#include <asm-generic/local.h>
+
+#endif /* __ASM_SH_LOCAL_H */
+
diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h
new file mode 100644
index 000000000000..b2e4124070ae
--- /dev/null
+++ b/arch/sh/include/asm/machvec.h
@@ -0,0 +1,70 @@
+/*
+ * include/asm-sh/machvec.h
+ *
+ * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ */
+
+#ifndef _ASM_SH_MACHVEC_H
+#define _ASM_SH_MACHVEC_H
+
+#include <linux/types.h>
+#include <linux/time.h>
+#include <asm/machtypes.h>
+
+struct device;
+
+struct sh_machine_vector {
+        void (*mv_setup)(char **cmdline_p);
+        const char *mv_name;
+        int mv_nr_irqs;
+
+        u8 (*mv_inb)(unsigned long);
+        u16 (*mv_inw)(unsigned long);
+        u32 (*mv_inl)(unsigned long);
+        void (*mv_outb)(u8, unsigned long);
+        void (*mv_outw)(u16, unsigned long);
+        void (*mv_outl)(u32, unsigned long);
+
+        u8 (*mv_inb_p)(unsigned long);
+        u16 (*mv_inw_p)(unsigned long);
+        u32 (*mv_inl_p)(unsigned long);
+        void (*mv_outb_p)(u8, unsigned long);
+        void (*mv_outw_p)(u16, unsigned long);
+        void (*mv_outl_p)(u32, unsigned long);
+
+        void (*mv_insb)(unsigned long, void *dst, unsigned long count);
+        void (*mv_insw)(unsigned long, void *dst, unsigned long count);
+        void (*mv_insl)(unsigned long, void *dst, unsigned long count);
+        void (*mv_outsb)(unsigned long, const void *src, unsigned long count);
+        void (*mv_outsw)(unsigned long, const void *src, unsigned long count);
+        void (*mv_outsl)(unsigned long, const void *src, unsigned long count);
+
+        u8 (*mv_readb)(void __iomem *);
+        u16 (*mv_readw)(void __iomem *);
+        u32 (*mv_readl)(void __iomem *);
+        void (*mv_writeb)(u8, void __iomem *);
+        void (*mv_writew)(u16, void __iomem *);
+        void (*mv_writel)(u32, void __iomem *);
+
+        int (*mv_irq_demux)(int irq);
+
+        void (*mv_init_irq)(void);
+        void (*mv_init_pci)(void);
+
+        void (*mv_heartbeat)(void);
+
+        void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
+        void (*mv_ioport_unmap)(void __iomem *);
+};
+
+extern struct sh_machine_vector sh_mv;
+
+#define get_system_type()       sh_mv.mv_name
+
+#define __initmv \
+        __used __section(.machvec.init)
+
+#endif /* _ASM_SH_MACHVEC_H */
diff --git a/arch/sh/include/asm/magicpanelr2.h b/arch/sh/include/asm/magicpanelr2.h
new file mode 100644
index 000000000000..c644a77ee357
--- /dev/null
+++ b/arch/sh/include/asm/magicpanelr2.h
@@ -0,0 +1,67 @@
+/*
+ *  include/asm-sh/magicpanelr2.h
+ *
+ *  Copyright (C) 2007  Markus Brunner, Mark Jonas
+ *
+ *  I/O addresses and bitmasks for Magic Panel Release 2 board
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_SH_MAGICPANELR2_H
+#define __ASM_SH_MAGICPANELR2_H
+
+#include <asm/gpio.h>
+
+#define __IO_PREFIX mpr2
+#include <asm/io_generic.h>
+
+
+#define SETBITS_OUTB(mask, reg)   ctrl_outb(ctrl_inb(reg) | mask, reg)
+#define SETBITS_OUTW(mask, reg)   ctrl_outw(ctrl_inw(reg) | mask, reg)
+#define SETBITS_OUTL(mask, reg)   ctrl_outl(ctrl_inl(reg) | mask, reg)
+#define CLRBITS_OUTB(mask, reg)   ctrl_outb(ctrl_inb(reg) & ~mask, reg)
+#define CLRBITS_OUTW(mask, reg)   ctrl_outw(ctrl_inw(reg) & ~mask, reg)
+#define CLRBITS_OUTL(mask, reg)   ctrl_outl(ctrl_inl(reg) & ~mask, reg)
+
+
+#define PA_LED          PORT_PADR      /* LED */
+
+
+/* BSC */
+#define CMNCR           0xA4FD0000UL
+#define CS0BCR          0xA4FD0004UL
+#define CS2BCR          0xA4FD0008UL
+#define CS3BCR          0xA4FD000CUL
+#define CS4BCR          0xA4FD0010UL
+#define CS5ABCR         0xA4FD0014UL
+#define CS5BBCR         0xA4FD0018UL
+#define CS6ABCR         0xA4FD001CUL
+#define CS6BBCR         0xA4FD0020UL
+#define CS0WCR          0xA4FD0024UL
+#define CS2WCR          0xA4FD0028UL
+#define CS3WCR          0xA4FD002CUL
+#define CS4WCR          0xA4FD0030UL
+#define CS5AWCR         0xA4FD0034UL
+#define CS5BWCR         0xA4FD0038UL
+#define CS6AWCR         0xA4FD003CUL
+#define CS6BWCR         0xA4FD0040UL
+
+
+/* usb */
+
+#define PORT_UTRCTL             0xA405012CUL
+#define PORT_UCLKCR_W           0xA40A0008UL
+
+#define INTC_ICR0               0xA414FEE0UL
+#define INTC_ICR1               0xA4140010UL
+#define INTC_ICR2               0xA4140012UL
+
+/* MTD */
+
+#define MPR2_MTD_BOOTLOADER_SIZE        0x00060000UL
+#define MPR2_MTD_KERNEL_SIZE            0x00200000UL
+
+#endif  /* __ASM_SH_MAGICPANELR2_H */
diff --git a/arch/sh/include/asm/mc146818rtc.h b/arch/sh/include/asm/mc146818rtc.h
new file mode 100644
index 000000000000..0aee96a97330
--- /dev/null
+++ b/arch/sh/include/asm/mc146818rtc.h
@@ -0,0 +1,7 @@
+/*
+ * Machine dependent access functions for RTC registers.
+ */
+#ifndef _ASM_MC146818RTC_H
+#define _ASM_MC146818RTC_H
+
+#endif /* _ASM_MC146818RTC_H */
diff --git a/arch/sh/include/asm/microdev.h b/arch/sh/include/asm/microdev.h
new file mode 100644
index 000000000000..1aed15856e11
--- /dev/null
+++ b/arch/sh/include/asm/microdev.h
@@ -0,0 +1,80 @@
+/*
+ * linux/include/asm-sh/microdev.h
+ *
+ * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
+ *
+ * Definitions for the SuperH SH4-202 MicroDev board.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ */
+#ifndef __ASM_SH_MICRODEV_H
+#define __ASM_SH_MICRODEV_H
+
+extern void init_microdev_irq(void);
+extern void microdev_print_fpga_intc_status(void);
+
+/*
+ * The following are useful macros for manipulating the interrupt
+ * controller (INTC) on the CPU-board FPGA.  should be noted that there
+ * is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
+ * these are two different things, both of which need to be prorammed to
+ * correctly route - unfortunately, they have the same name and
+ * abbreviations!
+ */
+#define MICRODEV_FPGA_INTC_BASE         0xa6110000ul                            /* INTC base address on CPU-board FPGA */
+#define MICRODEV_FPGA_INTENB_REG        (MICRODEV_FPGA_INTC_BASE+0ul)           /* Interrupt Enable Register on INTC on CPU-board FPGA */
+#define MICRODEV_FPGA_INTDSB_REG        (MICRODEV_FPGA_INTC_BASE+8ul)           /* Interrupt Disable Register on INTC on CPU-board FPGA */
+#define MICRODEV_FPGA_INTC_MASK(n)      (1ul<<(n))                              /* Interrupt mask to enable/disable INTC in CPU-board FPGA */
+#define MICRODEV_FPGA_INTPRI_REG(n)     (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */
+#define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4))                      /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */
+#define MICRODEV_FPGA_INTPRI_MASK(n)    (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */
+#define MICRODEV_FPGA_INTSRC_REG        (MICRODEV_FPGA_INTC_BASE+0x30ul)        /* Interrupt Source Register on INTC on CPU-board FPGA */
+#define MICRODEV_FPGA_INTREQ_REG        (MICRODEV_FPGA_INTC_BASE+0x38ul)        /* Interrupt Request Register on INTC on CPU-board FPGA */
+
+
+/*
+ * The following are the IRQ numbers for the Linux Kernel for external
+ * interrupts.  i.e. the numbers seen by 'cat /proc/interrupt'.
+ */
+#define MICRODEV_LINUX_IRQ_KEYBOARD      1      /* SuperIO Keyboard */
+#define MICRODEV_LINUX_IRQ_SERIAL1       2      /* SuperIO Serial #1 */
+#define MICRODEV_LINUX_IRQ_ETHERNET      3      /* on-board Ethnernet */
+#define MICRODEV_LINUX_IRQ_SERIAL2       4      /* SuperIO Serial #2 */
+#define MICRODEV_LINUX_IRQ_USB_HC        7      /* on-board USB HC */
+#define MICRODEV_LINUX_IRQ_MOUSE        12      /* SuperIO PS/2 Mouse */
+#define MICRODEV_LINUX_IRQ_IDE2         13      /* SuperIO IDE #2 */
+#define MICRODEV_LINUX_IRQ_IDE1         14      /* SuperIO IDE #1 */
+
+/*
+ * The following are the IRQ numbers for the INTC on the FPGA for
+ * external interrupts.  i.e. the bits in the INTC registers in the
+ * FPGA.
+ */
+#define MICRODEV_FPGA_IRQ_KEYBOARD       1      /* SuperIO Keyboard */
+#define MICRODEV_FPGA_IRQ_SERIAL1        3      /* SuperIO Serial #1 */
+#define MICRODEV_FPGA_IRQ_SERIAL2        4      /* SuperIO Serial #2 */
+#define MICRODEV_FPGA_IRQ_MOUSE         12      /* SuperIO PS/2 Mouse */
+#define MICRODEV_FPGA_IRQ_IDE1          14      /* SuperIO IDE #1 */
+#define MICRODEV_FPGA_IRQ_IDE2          15      /* SuperIO IDE #2 */
+#define MICRODEV_FPGA_IRQ_USB_HC        16      /* on-board USB HC */
+#define MICRODEV_FPGA_IRQ_ETHERNET      18      /* on-board Ethnernet */
+
+#define MICRODEV_IRQ_PCI_INTA            8
+#define MICRODEV_IRQ_PCI_INTB            9
+#define MICRODEV_IRQ_PCI_INTC           10
+#define MICRODEV_IRQ_PCI_INTD           11
+
+#define __IO_PREFIX microdev
+#include <asm/io_generic.h>
+
+#if defined(CONFIG_PCI)
+unsigned char  microdev_pci_inb(unsigned long port);
+unsigned short microdev_pci_inw(unsigned long port);
+unsigned long  microdev_pci_inl(unsigned long port);
+void           microdev_pci_outb(unsigned char  data, unsigned long port);
+void           microdev_pci_outw(unsigned short data, unsigned long port);
+void           microdev_pci_outl(unsigned long  data, unsigned long port);
+#endif
+
+#endif /* __ASM_SH_MICRODEV_H */
diff --git a/arch/sh/include/asm/migor.h b/arch/sh/include/asm/migor.h
new file mode 100644
index 000000000000..10016e0f4a4e
--- /dev/null
+++ b/arch/sh/include/asm/migor.h
@@ -0,0 +1,65 @@
+#ifndef __ASM_SH_MIGOR_H
+#define __ASM_SH_MIGOR_H
+
+/*
+ * linux/include/asm-sh/migor.h
+ *
+ * Copyright (C) 2008 Renesas Solutions
+ *
+ * Portions Copyright (C) 2007 Nobuhiro Iwamatsu
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <asm/addrspace.h>
+
+/* GPIO */
+#define PORT_PACR 0xa4050100
+#define PORT_PDCR 0xa4050106
+#define PORT_PECR 0xa4050108
+#define PORT_PHCR 0xa405010e
+#define PORT_PJCR 0xa4050110
+#define PORT_PKCR 0xa4050112
+#define PORT_PLCR 0xa4050114
+#define PORT_PMCR 0xa4050116
+#define PORT_PRCR 0xa405011c
+#define PORT_PTCR 0xa4050140
+#define PORT_PUCR 0xa4050142
+#define PORT_PVCR 0xa4050144
+#define PORT_PWCR 0xa4050146
+#define PORT_PXCR 0xa4050148
+#define PORT_PYCR 0xa405014a
+#define PORT_PZCR 0xa405014c
+#define PORT_PADR 0xa4050120
+#define PORT_PHDR 0xa405012e
+#define PORT_PTDR 0xa4050160
+#define PORT_PWDR 0xa4050166
+
+#define PORT_HIZCRA 0xa4050158
+#define PORT_HIZCRC 0xa405015c
+
+#define PORT_MSELCRB 0xa4050182
+
+#define MSTPCR1 0xa4150034
+#define MSTPCR2 0xa4150038
+
+#define PORT_PSELA 0xa405014e
+#define PORT_PSELB 0xa4050150
+#define PORT_PSELC 0xa4050152
+#define PORT_PSELD 0xa4050154
+#define PORT_PSELE 0xa4050156
+
+#define PORT_HIZCRA 0xa4050158
+#define PORT_HIZCRB 0xa405015a
+#define PORT_HIZCRC 0xa405015c
+
+#define BSC_CS6ABCR 0xfec1001c
+
+#include <asm/sh_mobile_lcdc.h>
+
+int migor_lcd_qvga_setup(void *board_data, void *sys_ops_handle,
+                         struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
+
+#endif /* __ASM_SH_MIGOR_H */
diff --git a/arch/sh/include/asm/mman.h b/arch/sh/include/asm/mman.h
new file mode 100644
index 000000000000..156eb0225cf6
--- /dev/null
+++ b/arch/sh/include/asm/mman.h
@@ -0,0 +1,17 @@
+#ifndef __ASM_SH_MMAN_H
+#define __ASM_SH_MMAN_H
+
+#include <asm-generic/mman.h>
+
+#define MAP_GROWSDOWN   0x0100          /* stack-like segment */
+#define MAP_DENYWRITE   0x0800          /* ETXTBSY */
+#define MAP_EXECUTABLE  0x1000          /* mark it as an executable */
+#define MAP_LOCKED      0x2000          /* pages are locked */
+#define MAP_NORESERVE   0x4000          /* don't check for reservations */
+#define MAP_POPULATE    0x8000          /* populate (prefault) page tables */
+#define MAP_NONBLOCK    0x10000         /* do not block on IO */
+
+#define MCL_CURRENT     1               /* lock all current mappings */
+#define MCL_FUTURE      2               /* lock all future mappings */
+
+#endif /* __ASM_SH_MMAN_H */
diff --git a/arch/sh/include/asm/mmu.h b/arch/sh/include/asm/mmu.h
new file mode 100644
index 000000000000..fdcb93bc6d11
--- /dev/null
+++ b/arch/sh/include/asm/mmu.h
@@ -0,0 +1,76 @@
+#ifndef __MMU_H
+#define __MMU_H
+
+/* Default "unsigned long" context */
+typedef unsigned long mm_context_id_t[NR_CPUS];
+
+typedef struct {
+#ifdef CONFIG_MMU
+        mm_context_id_t         id;
+        void                    *vdso;
+#else
+        struct vm_list_struct   *vmlist;
+        unsigned long           end_brk;
+#endif
+#ifdef CONFIG_BINFMT_ELF_FDPIC
+        unsigned long           exec_fdpic_loadmap;
+        unsigned long           interp_fdpic_loadmap;
+#endif
+} mm_context_t;
+
+/*
+ * Privileged Space Mapping Buffer (PMB) definitions
+ */
+#define PMB_PASCR               0xff000070
+#define PMB_IRMCR               0xff000078
+
+#define PMB_ADDR                0xf6100000
+#define PMB_DATA                0xf7100000
+#define PMB_ENTRY_MAX           16
+#define PMB_E_MASK              0x0000000f
+#define PMB_E_SHIFT             8
+
+#define PMB_SZ_16M              0x00000000
+#define PMB_SZ_64M              0x00000010
+#define PMB_SZ_128M             0x00000080
+#define PMB_SZ_512M             0x00000090
+#define PMB_SZ_MASK             PMB_SZ_512M
+#define PMB_C                   0x00000008
+#define PMB_WT                  0x00000001
+#define PMB_UB                  0x00000200
+#define PMB_V                   0x00000100
+
+#define PMB_NO_ENTRY            (-1)
+
+struct pmb_entry;
+
+struct pmb_entry {
+        unsigned long vpn;
+        unsigned long ppn;
+        unsigned long flags;
+
+        /*
+         * 0 .. NR_PMB_ENTRIES for specific entry selection, or
+         * PMB_NO_ENTRY to search for a free one
+         */
+        int entry;
+
+        struct pmb_entry *next;
+        /* Adjacent entry link for contiguous multi-entry mappings */
+        struct pmb_entry *link;
+};
+
+/* arch/sh/mm/pmb.c */
+int __set_pmb_entry(unsigned long vpn, unsigned long ppn,
+                    unsigned long flags, int *entry);
+int set_pmb_entry(struct pmb_entry *pmbe);
+void clear_pmb_entry(struct pmb_entry *pmbe);
+struct pmb_entry *pmb_alloc(unsigned long vpn, unsigned long ppn,
+                            unsigned long flags);
+void pmb_free(struct pmb_entry *pmbe);
+long pmb_remap(unsigned long virt, unsigned long phys,
+               unsigned long size, unsigned long flags);
+void pmb_unmap(unsigned long addr);
+
+#endif /* __MMU_H */
+
diff --git a/arch/sh/include/asm/mmu_context.h b/arch/sh/include/asm/mmu_context.h
new file mode 100644
index 000000000000..04c0c9733ad6
--- /dev/null
+++ b/arch/sh/include/asm/mmu_context.h
@@ -0,0 +1,185 @@
+/*
+ * Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2003 - 2007 Paul Mundt
+ *
+ * ASID handling idea taken from MIPS implementation.
+ */
+#ifndef __ASM_SH_MMU_CONTEXT_H
+#define __ASM_SH_MMU_CONTEXT_H
+
+#ifdef __KERNEL__
+#include <cpu/mmu_context.h>
+#include <asm/tlbflush.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm-generic/mm_hooks.h>
+
+/*
+ * The MMU "context" consists of two things:
+ *    (a) TLB cache version (or round, cycle whatever expression you like)
+ *    (b) ASID (Address Space IDentifier)
+ */
+#define MMU_CONTEXT_ASID_MASK           0x000000ff
+#define MMU_CONTEXT_VERSION_MASK        0xffffff00
+#define MMU_CONTEXT_FIRST_VERSION       0x00000100
+#define NO_CONTEXT                      0
+
+/* ASID is 8-bit value, so it can't be 0x100 */
+#define MMU_NO_ASID                     0x100
+
+#define asid_cache(cpu)         (cpu_data[cpu].asid_cache)
+
+#ifdef CONFIG_MMU
+#define cpu_context(cpu, mm)    ((mm)->context.id[cpu])
+
+#define cpu_asid(cpu, mm)       \
+        (cpu_context((cpu), (mm)) & MMU_CONTEXT_ASID_MASK)
+
+/*
+ * Virtual Page Number mask
+ */
+#define MMU_VPN_MASK    0xfffff000
+
+#if defined(CONFIG_SUPERH32)
+#include "mmu_context_32.h"
+#else
+#include "mmu_context_64.h"
+#endif
+
+/*
+ * Get MMU context if needed.
+ */
+static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu)
+{
+        unsigned long asid = asid_cache(cpu);
+
+        /* Check if we have old version of context. */
+        if (((cpu_context(cpu, mm) ^ asid) & MMU_CONTEXT_VERSION_MASK) == 0)
+                /* It's up to date, do nothing */
+                return;
+
+        /* It's old, we need to get new context with new version. */
+        if (!(++asid & MMU_CONTEXT_ASID_MASK)) {
+                /*
+                 * We exhaust ASID of this version.
+                 * Flush all TLB and start new cycle.
+                 */
+                flush_tlb_all();
+
+#ifdef CONFIG_SUPERH64
+                /*
+                 * The SH-5 cache uses the ASIDs, requiring both the I and D
+                 * cache to be flushed when the ASID is exhausted. Weak.
+                 */
+                flush_cache_all();
+#endif
+
+                /*
+                 * Fix version; Note that we avoid version #0
+                 * to distingush NO_CONTEXT.
+                 */
+                if (!asid)
+                        asid = MMU_CONTEXT_FIRST_VERSION;
+        }
+
+        cpu_context(cpu, mm) = asid_cache(cpu) = asid;
+}
+
+/*
+ * Initialize the context related info for a new mm_struct
+ * instance.
+ */
+static inline int init_new_context(struct task_struct *tsk,
+                                   struct mm_struct *mm)
+{
+        int i;
+
+        for (i = 0; i < num_online_cpus(); i++)
+                cpu_context(i, mm) = NO_CONTEXT;
+
+        return 0;
+}
+
+/*
+ * After we have set current->mm to a new value, this activates
+ * the context for the new mm so we see the new mappings.
+ */
+static inline void activate_context(struct mm_struct *mm, unsigned int cpu)
+{
+        get_mmu_context(mm, cpu);
+        set_asid(cpu_asid(cpu, mm));
+}
+
+static inline void switch_mm(struct mm_struct *prev,
+                             struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+        unsigned int cpu = smp_processor_id();
+
+        if (likely(prev != next)) {
+                cpu_set(cpu, next->cpu_vm_mask);
+                set_TTB(next->pgd);
+                activate_context(next, cpu);
+        } else
+                if (!cpu_test_and_set(cpu, next->cpu_vm_mask))
+                        activate_context(next, cpu);
+}
+#else
+#define get_mmu_context(mm)             do { } while (0)
+#define init_new_context(tsk,mm)        (0)
+#define destroy_context(mm)             do { } while (0)
+#define set_asid(asid)                  do { } while (0)
+#define get_asid()                      (0)
+#define cpu_asid(cpu, mm)               ({ (void)cpu; 0; })
+#define switch_and_save_asid(asid)      (0)
+#define set_TTB(pgd)                    do { } while (0)
+#define get_TTB()                       (0)
+#define activate_context(mm,cpu)        do { } while (0)
+#define switch_mm(prev,next,tsk)        do { } while (0)
+#endif /* CONFIG_MMU */
+
+#define activate_mm(prev, next)         switch_mm((prev),(next),NULL)
+#define deactivate_mm(tsk,mm)           do { } while (0)
+#define enter_lazy_tlb(mm,tsk)          do { } while (0)
+
+#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4)
+/*
+ * If this processor has an MMU, we need methods to turn it off/on ..
+ * paging_init() will also have to be updated for the processor in
+ * question.
+ */
+static inline void enable_mmu(void)
+{
+        unsigned int cpu = smp_processor_id();
+
+        /* Enable MMU */
+        ctrl_outl(MMU_CONTROL_INIT, MMUCR);
+        ctrl_barrier();
+
+        if (asid_cache(cpu) == NO_CONTEXT)
+                asid_cache(cpu) = MMU_CONTEXT_FIRST_VERSION;
+
+        set_asid(asid_cache(cpu) & MMU_CONTEXT_ASID_MASK);
+}
+
+static inline void disable_mmu(void)
+{
+        unsigned long cr;
+
+        cr = ctrl_inl(MMUCR);
+        cr &= ~MMU_CONTROL_INIT;
+        ctrl_outl(cr, MMUCR);
+
+        ctrl_barrier();
+}
+#else
+/*
+ * MMU control handlers for processors lacking memory
+ * management hardware.
+ */
+#define enable_mmu()    do { } while (0)
+#define disable_mmu()   do { } while (0)
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_MMU_CONTEXT_H */
diff --git a/arch/sh/include/asm/mmu_context_32.h b/arch/sh/include/asm/mmu_context_32.h
new file mode 100644
index 000000000000..f4f9aebd68b7
--- /dev/null
+++ b/arch/sh/include/asm/mmu_context_32.h
@@ -0,0 +1,47 @@
+#ifndef __ASM_SH_MMU_CONTEXT_32_H
+#define __ASM_SH_MMU_CONTEXT_32_H
+
+/*
+ * Destroy context related info for an mm_struct that is about
+ * to be put to rest.
+ */
+static inline void destroy_context(struct mm_struct *mm)
+{
+        /* Do nothing */
+}
+
+static inline void set_asid(unsigned long asid)
+{
+        unsigned long __dummy;
+
+        __asm__ __volatile__ ("mov.l    %2, %0\n\t"
+                              "and      %3, %0\n\t"
+                              "or       %1, %0\n\t"
+                              "mov.l    %0, %2"
+                              : "=&r" (__dummy)
+                              : "r" (asid), "m" (__m(MMU_PTEH)),
+                                "r" (0xffffff00));
+}
+
+static inline unsigned long get_asid(void)
+{
+        unsigned long asid;
+
+        __asm__ __volatile__ ("mov.l    %1, %0"
+                              : "=r" (asid)
+                              : "m" (__m(MMU_PTEH)));
+        asid &= MMU_CONTEXT_ASID_MASK;
+        return asid;
+}
+
+/* MMU_TTB is used for optimizing the fault handling. */
+static inline void set_TTB(pgd_t *pgd)
+{
+        ctrl_outl((unsigned long)pgd, MMU_TTB);
+}
+
+static inline pgd_t *get_TTB(void)
+{
+        return (pgd_t *)ctrl_inl(MMU_TTB);
+}
+#endif /* __ASM_SH_MMU_CONTEXT_32_H */
diff --git a/arch/sh/include/asm/mmu_context_64.h b/arch/sh/include/asm/mmu_context_64.h
new file mode 100644
index 000000000000..de121025d87f
--- /dev/null
+++ b/arch/sh/include/asm/mmu_context_64.h
@@ -0,0 +1,78 @@
+#ifndef __ASM_SH_MMU_CONTEXT_64_H
+#define __ASM_SH_MMU_CONTEXT_64_H
+
+/*
+ * sh64-specific mmu_context interface.
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003 - 2007  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <cpu/registers.h>
+#include <asm/cacheflush.h>
+
+#define SR_ASID_MASK            0xffffffffff00ffffULL
+#define SR_ASID_SHIFT           16
+
+/*
+ * Destroy context related info for an mm_struct that is about
+ * to be put to rest.
+ */
+static inline void destroy_context(struct mm_struct *mm)
+{
+        /* Well, at least free TLB entries */
+        flush_tlb_mm(mm);
+}
+
+static inline unsigned long get_asid(void)
+{
+        unsigned long long sr;
+
+        asm volatile ("getcon   " __SR ", %0\n\t"
+                      : "=r" (sr));
+
+        sr = (sr >> SR_ASID_SHIFT) & MMU_CONTEXT_ASID_MASK;
+        return (unsigned long) sr;
+}
+
+/* Set ASID into SR */
+static inline void set_asid(unsigned long asid)
+{
+        unsigned long long sr, pc;
+
+        asm volatile ("getcon   " __SR ", %0" : "=r" (sr));
+
+        sr = (sr & SR_ASID_MASK) | (asid << SR_ASID_SHIFT);
+
+        /*
+         * It is possible that this function may be inlined and so to avoid
+         * the assembler reporting duplicate symbols we make use of the
+         * gas trick of generating symbols using numerics and forward
+         * reference.
+         */
+        asm volatile ("movi     1, %1\n\t"
+                      "shlli    %1, 28, %1\n\t"
+                      "or       %0, %1, %1\n\t"
+                      "putcon   %1, " __SR "\n\t"
+                      "putcon   %0, " __SSR "\n\t"
+                      "movi     1f, %1\n\t"
+                      "ori      %1, 1 , %1\n\t"
+                      "putcon   %1, " __SPC "\n\t"
+                      "rte\n"
+                      "1:\n\t"
+                      : "=r" (sr), "=r" (pc) : "0" (sr));
+}
+
+/* arch/sh/kernel/cpu/sh5/entry.S */
+extern unsigned long switch_and_save_asid(unsigned long new_asid);
+
+/* No spare register to twiddle, so use a software cache */
+extern pgd_t *mmu_pdtp_cache;
+
+#define set_TTB(pgd)    (mmu_pdtp_cache = (pgd))
+#define get_TTB()       (mmu_pdtp_cache)
+
+#endif /* __ASM_SH_MMU_CONTEXT_64_H */
diff --git a/arch/sh/include/asm/mmzone.h b/arch/sh/include/asm/mmzone.h
new file mode 100644
index 000000000000..2969253c4042
--- /dev/null
+++ b/arch/sh/include/asm/mmzone.h
@@ -0,0 +1,48 @@
+#ifndef __ASM_SH_MMZONE_H
+#define __ASM_SH_MMZONE_H
+
+#ifdef __KERNEL__
+
+#ifdef CONFIG_NEED_MULTIPLE_NODES
+extern struct pglist_data *node_data[];
+#define NODE_DATA(nid)          (node_data[nid])
+
+#define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
+#define node_end_pfn(nid)       (NODE_DATA(nid)->node_start_pfn + \
+                                 NODE_DATA(nid)->node_spanned_pages)
+
+static inline int pfn_to_nid(unsigned long pfn)
+{
+        int nid;
+
+        for (nid = 0; nid < MAX_NUMNODES; nid++)
+                if (pfn >= node_start_pfn(nid) && pfn <= node_end_pfn(nid))
+                        break;
+
+        return nid;
+}
+
+static inline struct pglist_data *pfn_to_pgdat(unsigned long pfn)
+{
+        return NODE_DATA(pfn_to_nid(pfn));
+}
+
+/* arch/sh/mm/numa.c */
+void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end);
+#else
+static inline void
+setup_bootmem_node(int nid, unsigned long start, unsigned long end)
+{
+}
+#endif /* CONFIG_NEED_MULTIPLE_NODES */
+
+/* Platform specific mem init */
+void __init plat_mem_setup(void);
+
+/* arch/sh/kernel/setup.c */
+void __init setup_bootmem_allocator(unsigned long start_pfn);
+void __init __add_active_range(unsigned int nid, unsigned long start_pfn,
+                               unsigned long end_pfn);
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_MMZONE_H */
diff --git a/arch/sh/include/asm/module.h b/arch/sh/include/asm/module.h
new file mode 100644
index 000000000000..46eccd331660
--- /dev/null
+++ b/arch/sh/include/asm/module.h
@@ -0,0 +1,44 @@
+#ifndef _ASM_SH_MODULE_H
+#define _ASM_SH_MODULE_H
+
+/*
+ * This file contains the SH architecture specific module code.
+ */
+
+struct mod_arch_specific {
+        /* Nothing to see here .. */
+};
+
+#define Elf_Shdr                Elf32_Shdr
+#define Elf_Sym                 Elf32_Sym
+#define Elf_Ehdr                Elf32_Ehdr
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+# ifdef CONFIG_CPU_SH2
+#  define MODULE_PROC_FAMILY "SH2LE "
+# elif defined  CONFIG_CPU_SH3
+#  define MODULE_PROC_FAMILY "SH3LE "
+# elif defined  CONFIG_CPU_SH4
+#  define MODULE_PROC_FAMILY "SH4LE "
+# elif defined  CONFIG_CPU_SH5
+#  define MODULE_PROC_FAMILY "SH5LE "
+# else
+#  error unknown processor family
+# endif
+#else
+# ifdef CONFIG_CPU_SH2
+#  define MODULE_PROC_FAMILY "SH2BE "
+# elif defined  CONFIG_CPU_SH3
+#  define MODULE_PROC_FAMILY "SH3BE "
+# elif defined  CONFIG_CPU_SH4
+#  define MODULE_PROC_FAMILY "SH4BE "
+# elif defined  CONFIG_CPU_SH5
+#  define MODULE_PROC_FAMILY "SH5BE "
+# else
+#  error unknown processor family
+# endif
+#endif
+
+#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY
+
+#endif /* _ASM_SH_MODULE_H */
diff --git a/arch/sh/include/asm/msgbuf.h b/arch/sh/include/asm/msgbuf.h
new file mode 100644
index 000000000000..517432343fb5
--- /dev/null
+++ b/arch/sh/include/asm/msgbuf.h
@@ -0,0 +1,31 @@
+#ifndef __ASM_SH_MSGBUF_H
+#define __ASM_SH_MSGBUF_H
+
+/* 
+ * The msqid64_ds structure for i386 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+        __kernel_time_t msg_stime;      /* last msgsnd time */
+        unsigned long   __unused1;
+        __kernel_time_t msg_rtime;      /* last msgrcv time */
+        unsigned long   __unused2;
+        __kernel_time_t msg_ctime;      /* last change time */
+        unsigned long   __unused3;
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+#endif /* __ASM_SH_MSGBUF_H */
diff --git a/arch/sh/include/asm/mutex.h b/arch/sh/include/asm/mutex.h
new file mode 100644
index 000000000000..458c1f7fbc18
--- /dev/null
+++ b/arch/sh/include/asm/mutex.h
@@ -0,0 +1,9 @@
+/*
+ * Pull in the generic implementation for the mutex fastpath.
+ *
+ * TODO: implement optimized primitives instead, or leave the generic
+ * implementation in place, or pick the atomic_xchg() based generic
+ * implementation. (see asm-generic/mutex-xchg.h for details)
+ */
+
+#include <asm-generic/mutex-dec.h>
diff --git a/arch/sh/include/asm/page.h b/arch/sh/include/asm/page.h
new file mode 100644
index 000000000000..77fb8bf02e4e
--- /dev/null
+++ b/arch/sh/include/asm/page.h
@@ -0,0 +1,183 @@
+#ifndef __ASM_SH_PAGE_H
+#define __ASM_SH_PAGE_H
+
+/*
+ * Copyright (C) 1999  Niibe Yutaka
+ */
+
+#include <linux/const.h>
+
+/* PAGE_SHIFT determines the page size */
+#if defined(CONFIG_PAGE_SIZE_4KB)
+# define PAGE_SHIFT     12
+#elif defined(CONFIG_PAGE_SIZE_8KB)
+# define PAGE_SHIFT     13
+#elif defined(CONFIG_PAGE_SIZE_16KB)
+# define PAGE_SHIFT     14
+#elif defined(CONFIG_PAGE_SIZE_64KB)
+# define PAGE_SHIFT     16
+#else
+# error "Bogus kernel page size?"
+#endif
+
+#define PAGE_SIZE       (_AC(1, UL) << PAGE_SHIFT)
+#define PAGE_MASK       (~(PAGE_SIZE-1))
+#define PTE_MASK        PAGE_MASK
+
+#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#define HPAGE_SHIFT     16
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
+#define HPAGE_SHIFT     18
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
+#define HPAGE_SHIFT     20
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
+#define HPAGE_SHIFT     22
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
+#define HPAGE_SHIFT     26
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512MB)
+#define HPAGE_SHIFT     29
+#endif
+
+#ifdef CONFIG_HUGETLB_PAGE
+#define HPAGE_SIZE              (1UL << HPAGE_SHIFT)
+#define HPAGE_MASK              (~(HPAGE_SIZE-1))
+#define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT-PAGE_SHIFT)
+#endif
+
+#ifndef __ASSEMBLY__
+
+extern unsigned long shm_align_mask;
+extern unsigned long max_low_pfn, min_low_pfn;
+extern unsigned long memory_start, memory_end;
+
+extern void clear_page(void *to);
+extern void copy_page(void *to, void *from);
+
+#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \
+        (defined(CONFIG_CPU_SH5) || defined(CONFIG_CPU_SH4) || \
+         defined(CONFIG_SH7705_CACHE_32KB))
+struct page;
+struct vm_area_struct;
+extern void clear_user_page(void *to, unsigned long address, struct page *page);
+extern void copy_user_page(void *to, void *from, unsigned long address,
+                           struct page *page);
+#if defined(CONFIG_CPU_SH4)
+extern void copy_user_highpage(struct page *to, struct page *from,
+                               unsigned long vaddr, struct vm_area_struct *vma);
+#define __HAVE_ARCH_COPY_USER_HIGHPAGE
+#endif
+#else
+#define clear_user_page(page, vaddr, pg)        clear_page(page)
+#define copy_user_page(to, from, vaddr, pg)     copy_page(to, from)
+#endif
+
+/*
+ * These are used to make use of C type-checking..
+ */
+#ifdef CONFIG_X2TLB
+typedef struct { unsigned long pte_low, pte_high; } pte_t;
+typedef struct { unsigned long long pgprot; } pgprot_t;
+typedef struct { unsigned long long pgd; } pgd_t;
+#define pte_val(x) \
+        ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
+#define __pte(x) \
+        ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
+#elif defined(CONFIG_SUPERH32)
+typedef struct { unsigned long pte_low; } pte_t;
+typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct { unsigned long pgd; } pgd_t;
+#define pte_val(x)      ((x).pte_low)
+#define __pte(x)        ((pte_t) { (x) } )
+#else
+typedef struct { unsigned long long pte_low; } pte_t;
+typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct { unsigned long pgd; } pgd_t;
+#define pte_val(x)      ((x).pte_low)
+#define __pte(x)        ((pte_t) { (x) } )
+#endif
+
+#define pgd_val(x)      ((x).pgd)
+#define pgprot_val(x)   ((x).pgprot)
+
+#define __pgd(x) ((pgd_t) { (x) } )
+#define __pgprot(x)     ((pgprot_t) { (x) } )
+
+typedef struct page *pgtable_t;
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * __MEMORY_START and SIZE are the physical addresses and size of RAM.
+ */
+#define __MEMORY_START          CONFIG_MEMORY_START
+#define __MEMORY_SIZE           CONFIG_MEMORY_SIZE
+
+/*
+ * PAGE_OFFSET is the virtual address of the start of kernel address
+ * space.
+ */
+#define PAGE_OFFSET             CONFIG_PAGE_OFFSET
+
+/*
+ * Virtual to physical RAM address translation.
+ *
+ * In 29 bit mode, the physical offset of RAM from address 0 is visible in
+ * the kernel virtual address space, and thus we don't have to take
+ * this into account when translating. However in 32 bit mode this offset
+ * is not visible (it is part of the PMB mapping) and so needs to be
+ * added or subtracted as required.
+ */
+#ifdef CONFIG_32BIT
+#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET+__MEMORY_START)
+#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET-__MEMORY_START))
+#else
+#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET)
+#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET))
+#endif
+
+#define pfn_to_kaddr(pfn)       __va((pfn) << PAGE_SHIFT)
+#define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
+
+/*
+ * PFN = physical frame number (ie PFN 0 == physical address 0)
+ * PFN_START is the PFN of the first page of RAM. By defining this we
+ * don't have struct page entries for the portion of address space
+ * between physical address 0 and the start of RAM.
+ */
+#define PFN_START               (__MEMORY_START >> PAGE_SHIFT)
+#define ARCH_PFN_OFFSET         (PFN_START)
+#define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
+#ifdef CONFIG_FLATMEM
+#define pfn_valid(pfn)          ((pfn) >= min_low_pfn && (pfn) < max_low_pfn)
+#endif
+#define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
+
+#define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
+                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#include <asm-generic/memory_model.h>
+#include <asm-generic/page.h>
+
+/* vDSO support */
+#ifdef CONFIG_VSYSCALL
+#define __HAVE_ARCH_GATE_AREA
+#endif
+
+/*
+ * Some drivers need to perform DMA into kmalloc'ed buffers
+ * and so we have to increase the kmalloc minalign for this.
+ */
+#define ARCH_KMALLOC_MINALIGN   L1_CACHE_BYTES
+
+#ifdef CONFIG_SUPERH64
+/*
+ * While BYTES_PER_WORD == 4 on the current sh64 ABI, GCC will still
+ * happily generate {ld/st}.q pairs, requiring us to have 8-byte
+ * alignment to avoid traps. The kmalloc alignment is gauranteed by
+ * virtue of L1_CACHE_BYTES, requiring this to only be special cased
+ * for slab caches.
+ */
+#define ARCH_SLAB_MINALIGN      8
+#endif
+
+#endif /* __ASM_SH_PAGE_H */
diff --git a/arch/sh/include/asm/param.h b/arch/sh/include/asm/param.h
new file mode 100644
index 000000000000..ae245afdfd6a
--- /dev/null
+++ b/arch/sh/include/asm/param.h
@@ -0,0 +1,22 @@
+#ifndef __ASM_SH_PARAM_H
+#define __ASM_SH_PARAM_H
+
+#ifdef __KERNEL__
+# define HZ             CONFIG_HZ
+# define USER_HZ        100             /* User interfaces are in "ticks" */
+# define CLOCKS_PER_SEC (USER_HZ)       /* frequency at which times() counts */
+#endif
+
+#ifndef HZ
+#define HZ 100
+#endif
+
+#define EXEC_PAGESIZE   4096
+
+#ifndef NOGROUP
+#define NOGROUP         (-1)
+#endif
+
+#define MAXHOSTNAMELEN  64      /* max length of hostname */
+
+#endif /* __ASM_SH_PARAM_H */
diff --git a/arch/sh/include/asm/parport.h b/arch/sh/include/asm/parport.h
new file mode 100644
index 000000000000..f67ba60a2acd
--- /dev/null
+++ b/arch/sh/include/asm/parport.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
+ *
+ * This file should only be included by drivers/parport/parport_pc.c.
+ */
+#ifndef __ASM_SH_PARPORT_H
+#define __ASM_SH_PARPORT_H
+
+static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
+
+static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
+{
+        return parport_pc_find_isa_ports(autoirq, autodma);
+}
+
+#endif /* __ASM_SH_PARPORT_H */
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
new file mode 100644
index 000000000000..df1d383e18a5
--- /dev/null
+++ b/arch/sh/include/asm/pci.h
@@ -0,0 +1,144 @@
+#ifndef __ASM_SH_PCI_H
+#define __ASM_SH_PCI_H
+
+#ifdef __KERNEL__
+
+#include <linux/dma-mapping.h>
+
+/* Can be used to override the logic in pci_scan_bus for skipping
+   already-configured bus numbers - to be used for buggy BIOSes
+   or architectures with incomplete PCI setup by the loader */
+
+#define pcibios_assign_all_busses()     1
+#define pcibios_scan_all_fns(a, b)      0
+
+/*
+ * A board can define one or more PCI channels that represent built-in (or
+ * external) PCI controllers.
+ */
+struct pci_channel {
+        struct pci_ops *pci_ops;
+        struct resource *io_resource;
+        struct resource *mem_resource;
+        int first_devfn;
+        int last_devfn;
+};
+
+/*
+ * Each board initializes this array and terminates it with a NULL entry.
+ */
+extern struct pci_channel board_pci_channels[];
+
+#define PCIBIOS_MIN_IO          board_pci_channels->io_resource->start
+#define PCIBIOS_MIN_MEM         board_pci_channels->mem_resource->start
+
+/*
+ * I/O routine helpers
+ */
+#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
+#define PCI_IO_AREA             0xFE400000
+#define PCI_IO_SIZE             0x00400000
+#elif defined(CONFIG_CPU_SH5)
+extern unsigned long PCI_IO_AREA;
+#define PCI_IO_SIZE             0x00010000
+#else
+#define PCI_IO_AREA             0xFE240000
+#define PCI_IO_SIZE             0x00040000
+#endif
+
+#define PCI_MEM_SIZE            0x01000000
+
+#define SH4_PCIIOBR_MASK        0xFFFC0000
+#define pci_ioaddr(addr)        (PCI_IO_AREA + (addr & ~SH4_PCIIOBR_MASK))
+
+#if defined(CONFIG_PCI)
+#define is_pci_ioaddr(port)             \
+        (((port) >= PCIBIOS_MIN_IO) &&  \
+         ((port) < (PCIBIOS_MIN_IO + PCI_IO_SIZE)))
+#define is_pci_memaddr(port)            \
+        (((port) >= PCIBIOS_MIN_MEM) && \
+         ((port) < (PCIBIOS_MIN_MEM + PCI_MEM_SIZE)))
+#else
+#define is_pci_ioaddr(port)     (0)
+#define is_pci_memaddr(port)    (0)
+#endif
+
+struct pci_dev;
+
+extern void pcibios_set_master(struct pci_dev *dev);
+
+static inline void pcibios_penalize_isa_irq(int irq, int active)
+{
+        /* We don't do dynamic PCI IRQ allocation */
+}
+
+/* Dynamic DMA mapping stuff.
+ * SuperH has everything mapped statically like x86.
+ */
+
+/* The PCI address space does equal the physical memory
+ * address space.  The networking and block device layers use
+ * this boolean for bounce buffer decisions.
+ */
+#define PCI_DMA_BUS_IS_PHYS     (1)
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/scatterlist.h>
+#include <linux/string.h>
+#include <asm/io.h>
+
+/* pci_unmap_{single,page} being a nop depends upon the
+ * configuration.
+ */
+#ifdef CONFIG_SH_PCIDMA_NONCOHERENT
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
+        dma_addr_t ADDR_NAME;
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
+        __u32 LEN_NAME;
+#define pci_unmap_addr(PTR, ADDR_NAME)                  \
+        ((PTR)->ADDR_NAME)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
+        (((PTR)->ADDR_NAME) = (VAL))
+#define pci_unmap_len(PTR, LEN_NAME)                    \
+        ((PTR)->LEN_NAME)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
+        (((PTR)->LEN_NAME) = (VAL))
+#else
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
+#define pci_unmap_addr(PTR, ADDR_NAME)          (0)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
+#define pci_unmap_len(PTR, LEN_NAME)            (0)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
+#endif
+
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        *strat = PCI_DMA_BURST_INFINITY;
+        *strategy_parameter = ~0UL;
+}
+#endif
+
+/* Board-specific fixup routines. */
+void pcibios_fixup(void);
+int pcibios_init_platform(void);
+int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
+
+#ifdef CONFIG_PCI_AUTO
+int pciauto_assign_resources(int busno, struct pci_channel *hose);
+#endif
+
+#endif /* __KERNEL__ */
+
+/* generic pci stuff */
+#include <asm-generic/pci.h>
+
+/* generic DMA-mapping stuff */
+#include <asm-generic/pci-dma-compat.h>
+
+#endif /* __ASM_SH_PCI_H */
+
diff --git a/arch/sh/include/asm/percpu.h b/arch/sh/include/asm/percpu.h
new file mode 100644
index 000000000000..4db4b39a4399
--- /dev/null
+++ b/arch/sh/include/asm/percpu.h
@@ -0,0 +1,6 @@
+#ifndef __ARCH_SH_PERCPU
+#define __ARCH_SH_PERCPU
+
+#include <asm-generic/percpu.h>
+
+#endif /* __ARCH_SH_PERCPU */
diff --git a/arch/sh/include/asm/pgalloc.h b/arch/sh/include/asm/pgalloc.h
new file mode 100644
index 000000000000..84dd2db7104c
--- /dev/null
+++ b/arch/sh/include/asm/pgalloc.h
@@ -0,0 +1,96 @@
+#ifndef __ASM_SH_PGALLOC_H
+#define __ASM_SH_PGALLOC_H
+
+#include <linux/quicklist.h>
+#include <asm/page.h>
+
+#define QUICK_PGD 0     /* We preserve special mappings over free */
+#define QUICK_PT 1      /* Other page table pages that are zero on free */
+
+static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
+                                       pte_t *pte)
+{
+        set_pmd(pmd, __pmd((unsigned long)pte));
+}
+
+static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
+                                pgtable_t pte)
+{
+        set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
+}
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
+static inline void pgd_ctor(void *x)
+{
+        pgd_t *pgd = x;
+
+        memcpy(pgd + USER_PTRS_PER_PGD,
+               swapper_pg_dir + USER_PTRS_PER_PGD,
+               (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+}
+
+/*
+ * Allocate and free page tables.
+ */
+static inline pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+        return quicklist_alloc(QUICK_PGD, GFP_KERNEL | __GFP_REPEAT, pgd_ctor);
+}
+
+static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
+{
+        quicklist_free(QUICK_PGD, NULL, pgd);
+}
+
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+                                          unsigned long address)
+{
+        return quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
+}
+
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
+                                        unsigned long address)
+{
+        struct page *page;
+        void *pg;
+
+        pg = quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
+        if (!pg)
+                return NULL;
+        page = virt_to_page(pg);
+        pgtable_page_ctor(page);
+        return page;
+}
+
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+        quicklist_free(QUICK_PT, NULL, pte);
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
+{
+        pgtable_page_dtor(pte);
+        quicklist_free_page(QUICK_PT, NULL, pte);
+}
+
+#define __pte_free_tlb(tlb,pte)                         \
+do {                                                    \
+        pgtable_page_dtor(pte);                         \
+        tlb_remove_page((tlb), (pte));                  \
+} while (0)
+
+/*
+ * allocating and freeing a pmd is trivial: the 1-entry pmd is
+ * inside the pgd, so has no extra memory associated with it.
+ */
+
+#define pmd_free(mm, x)                 do { } while (0)
+#define __pmd_free_tlb(tlb,x)           do { } while (0)
+
+static inline void check_pgt_cache(void)
+{
+        quicklist_trim(QUICK_PGD, NULL, 25, 16);
+        quicklist_trim(QUICK_PT, NULL, 25, 16);
+}
+
+#endif /* __ASM_SH_PGALLOC_H */
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
new file mode 100644
index 000000000000..a4a8f8b93463
--- /dev/null
+++ b/arch/sh/include/asm/pgtable.h
@@ -0,0 +1,152 @@
+/*
+ * This file contains the functions and defines necessary to modify and
+ * use the SuperH page table tree.
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2002 - 2007 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of this
+ * archive for more details.
+ */
+#ifndef __ASM_SH_PGTABLE_H
+#define __ASM_SH_PGTABLE_H
+
+#include <asm-generic/pgtable-nopmd.h>
+#include <asm/page.h>
+
+#ifndef __ASSEMBLY__
+#include <asm/addrspace.h>
+#include <asm/fixmap.h>
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
+#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Effective and physical address definitions, to aid with sign
+ * extension.
+ */
+#define NEFF            32
+#define NEFF_SIGN       (1LL << (NEFF - 1))
+#define NEFF_MASK       (-1LL << NEFF)
+
+#ifdef CONFIG_29BIT
+#define NPHYS           29
+#else
+#define NPHYS           32
+#endif
+
+#define NPHYS_SIGN      (1LL << (NPHYS - 1))
+#define NPHYS_MASK      (-1LL << NPHYS)
+
+/*
+ * traditional two-level paging structure
+ */
+/* PTE bits */
+#if defined(CONFIG_X2TLB) || defined(CONFIG_SUPERH64)
+# define PTE_MAGNITUDE  3       /* 64-bit PTEs on extended mode SH-X2 TLB */
+#else
+# define PTE_MAGNITUDE  2       /* 32-bit PTEs */
+#endif
+#define PTE_SHIFT       PAGE_SHIFT
+#define PTE_BITS        (PTE_SHIFT - PTE_MAGNITUDE)
+
+/* PGD bits */
+#define PGDIR_SHIFT     (PTE_SHIFT + PTE_BITS)
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+
+/* Entries per level */
+#define PTRS_PER_PTE    (PAGE_SIZE / (1 << PTE_MAGNITUDE))
+#define PTRS_PER_PGD    (PAGE_SIZE / sizeof(pgd_t))
+
+#define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
+#define FIRST_USER_ADDRESS      0
+
+#ifdef CONFIG_32BIT
+#define PHYS_ADDR_MASK          0xffffffff
+#else
+#define PHYS_ADDR_MASK          0x1fffffff
+#endif
+
+#define PTE_PHYS_MASK           (PHYS_ADDR_MASK & PAGE_MASK)
+
+#ifdef CONFIG_SUPERH32
+#define VMALLOC_START   (P3SEG)
+#else
+#define VMALLOC_START   (0xf0000000)
+#endif
+#define VMALLOC_END     (FIXADDR_START-2*PAGE_SIZE)
+
+#if defined(CONFIG_SUPERH32)
+#include <asm/pgtable_32.h>
+#else
+#include <asm/pgtable_64.h>
+#endif
+
+/*
+ * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
+ * protection for execute, and considers it the same as a read. Also, write
+ * permission implies read permission. This is the closest we can get..
+ *
+ * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
+ * not only supporting separate execute, read, and write bits, but having
+ * completely separate permission bits for user and kernel space.
+ */
+         /*xwr*/
+#define __P000  PAGE_NONE
+#define __P001  PAGE_READONLY
+#define __P010  PAGE_COPY
+#define __P011  PAGE_COPY
+#define __P100  PAGE_EXECREAD
+#define __P101  PAGE_EXECREAD
+#define __P110  PAGE_COPY
+#define __P111  PAGE_COPY
+
+#define __S000  PAGE_NONE
+#define __S001  PAGE_READONLY
+#define __S010  PAGE_WRITEONLY
+#define __S011  PAGE_SHARED
+#define __S100  PAGE_EXECREAD
+#define __S101  PAGE_EXECREAD
+#define __S110  PAGE_RWX
+#define __S111  PAGE_RWX
+
+typedef pte_t *pte_addr_t;
+
+#define kern_addr_valid(addr)   (1)
+
+#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
+                remap_pfn_range(vma, vaddr, pfn, size, prot)
+
+#define pte_pfn(x)              ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
+
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init()    do { } while (0)
+
+#if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \
+        defined(CONFIG_SH7705_CACHE_32KB))
+struct mm_struct;
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
+#endif
+
+struct vm_area_struct;
+extern void update_mmu_cache(struct vm_area_struct * vma,
+                             unsigned long address, pte_t pte);
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+extern void paging_init(void);
+extern void page_table_range_init(unsigned long start, unsigned long end,
+                                  pgd_t *pgd);
+
+#include <asm-generic/pgtable.h>
+
+#endif /* __ASM_SH_PGTABLE_H */
diff --git a/arch/sh/include/asm/pgtable_32.h b/arch/sh/include/asm/pgtable_32.h
new file mode 100644
index 000000000000..72ea209195bd
--- /dev/null
+++ b/arch/sh/include/asm/pgtable_32.h
@@ -0,0 +1,479 @@
+#ifndef __ASM_SH_PGTABLE_32_H
+#define __ASM_SH_PGTABLE_32_H
+
+/*
+ * Linux PTEL encoding.
+ *
+ * Hardware and software bit definitions for the PTEL value (see below for
+ * notes on SH-X2 MMUs and 64-bit PTEs):
+ *
+ * - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4).
+ *
+ * - Bit 1 is the SH-bit, but is unused on SH-3 due to an MMU bug (the
+ *   hardware PTEL value can't have the SH-bit set when MMUCR.IX is set,
+ *   which is the default in cpu-sh3/mmu_context.h:MMU_CONTROL_INIT).
+ *
+ *   In order to keep this relatively clean, do not use these for defining
+ *   SH-3 specific flags until all of the other unused bits have been
+ *   exhausted.
+ *
+ * - Bit 9 is reserved by everyone and used by _PAGE_PROTNONE.
+ *
+ * - Bits 10 and 11 are low bits of the PPN that are reserved on >= 4K pages.
+ *   Bit 10 is used for _PAGE_ACCESSED, bit 11 remains unused.
+ *
+ * - On 29 bit platforms, bits 31 to 29 are used for the space attributes
+ *   and timing control which (together with bit 0) are moved into the
+ *   old-style PTEA on the parts that support it.
+ *
+ * XXX: Leave the _PAGE_FILE and _PAGE_WT overhaul for a rainy day.
+ *
+ * SH-X2 MMUs and extended PTEs
+ *
+ * SH-X2 supports an extended mode TLB with split data arrays due to the
+ * number of bits needed for PR and SZ (now EPR and ESZ) encodings. The PR and
+ * SZ bit placeholders still exist in data array 1, but are implemented as
+ * reserved bits, with the real logic existing in data array 2.
+ *
+ * The downside to this is that we can no longer fit everything in to a 32-bit
+ * PTE encoding, so a 64-bit pte_t is necessary for these parts. On the plus
+ * side, this gives us quite a few spare bits to play with for future usage.
+ */
+/* Legacy and compat mode bits */
+#define _PAGE_WT        0x001           /* WT-bit on SH-4, 0 on SH-3 */
+#define _PAGE_HW_SHARED 0x002           /* SH-bit  : shared among processes */
+#define _PAGE_DIRTY     0x004           /* D-bit   : page changed */
+#define _PAGE_CACHABLE  0x008           /* C-bit   : cachable */
+#define _PAGE_SZ0       0x010           /* SZ0-bit : Size of page */
+#define _PAGE_RW        0x020           /* PR0-bit : write access allowed */
+#define _PAGE_USER      0x040           /* PR1-bit : user space access allowed*/
+#define _PAGE_SZ1       0x080           /* SZ1-bit : Size of page (on SH-4) */
+#define _PAGE_PRESENT   0x100           /* V-bit   : page is valid */
+#define _PAGE_PROTNONE  0x200           /* software: if not present  */
+#define _PAGE_ACCESSED  0x400           /* software: page referenced */
+#define _PAGE_FILE      _PAGE_WT        /* software: pagecache or swap? */
+
+#define _PAGE_SZ_MASK   (_PAGE_SZ0 | _PAGE_SZ1)
+#define _PAGE_PR_MASK   (_PAGE_RW | _PAGE_USER)
+
+/* Extended mode bits */
+#define _PAGE_EXT_ESZ0          0x0010  /* ESZ0-bit: Size of page */
+#define _PAGE_EXT_ESZ1          0x0020  /* ESZ1-bit: Size of page */
+#define _PAGE_EXT_ESZ2          0x0040  /* ESZ2-bit: Size of page */
+#define _PAGE_EXT_ESZ3          0x0080  /* ESZ3-bit: Size of page */
+
+#define _PAGE_EXT_USER_EXEC     0x0100  /* EPR0-bit: User space executable */
+#define _PAGE_EXT_USER_WRITE    0x0200  /* EPR1-bit: User space writable */
+#define _PAGE_EXT_USER_READ     0x0400  /* EPR2-bit: User space readable */
+
+#define _PAGE_EXT_KERN_EXEC     0x0800  /* EPR3-bit: Kernel space executable */
+#define _PAGE_EXT_KERN_WRITE    0x1000  /* EPR4-bit: Kernel space writable */
+#define _PAGE_EXT_KERN_READ     0x2000  /* EPR5-bit: Kernel space readable */
+
+/* Wrapper for extended mode pgprot twiddling */
+#define _PAGE_EXT(x)            ((unsigned long long)(x) << 32)
+
+/* software: moves to PTEA.TC (Timing Control) */
+#define _PAGE_PCC_AREA5 0x00000000      /* use BSC registers for area5 */
+#define _PAGE_PCC_AREA6 0x80000000      /* use BSC registers for area6 */
+
+/* software: moves to PTEA.SA[2:0] (Space Attributes) */
+#define _PAGE_PCC_IODYN 0x00000001      /* IO space, dynamically sized bus */
+#define _PAGE_PCC_IO8   0x20000000      /* IO space, 8 bit bus */
+#define _PAGE_PCC_IO16  0x20000001      /* IO space, 16 bit bus */
+#define _PAGE_PCC_COM8  0x40000000      /* Common Memory space, 8 bit bus */
+#define _PAGE_PCC_COM16 0x40000001      /* Common Memory space, 16 bit bus */
+#define _PAGE_PCC_ATR8  0x60000000      /* Attribute Memory space, 8 bit bus */
+#define _PAGE_PCC_ATR16 0x60000001      /* Attribute Memory space, 6 bit bus */
+
+/* Mask which drops unused bits from the PTEL value */
+#if defined(CONFIG_CPU_SH3)
+#define _PAGE_CLEAR_FLAGS       (_PAGE_PROTNONE | _PAGE_ACCESSED| \
+                                 _PAGE_FILE     | _PAGE_SZ1     | \
+                                 _PAGE_HW_SHARED)
+#elif defined(CONFIG_X2TLB)
+/* Get rid of the legacy PR/SZ bits when using extended mode */
+#define _PAGE_CLEAR_FLAGS       (_PAGE_PROTNONE | _PAGE_ACCESSED | \
+                                 _PAGE_FILE | _PAGE_PR_MASK | _PAGE_SZ_MASK)
+#else
+#define _PAGE_CLEAR_FLAGS       (_PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_FILE)
+#endif
+
+#define _PAGE_FLAGS_HARDWARE_MASK       (PHYS_ADDR_MASK & ~(_PAGE_CLEAR_FLAGS))
+
+/* Hardware flags, page size encoding */
+#if !defined(CONFIG_MMU)
+# define _PAGE_FLAGS_HARD       0ULL
+#elif defined(CONFIG_X2TLB)
+# if defined(CONFIG_PAGE_SIZE_4KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_EXT(_PAGE_EXT_ESZ0)
+# elif defined(CONFIG_PAGE_SIZE_8KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_EXT(_PAGE_EXT_ESZ1)
+# elif defined(CONFIG_PAGE_SIZE_64KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_EXT(_PAGE_EXT_ESZ2)
+# endif
+#else
+# if defined(CONFIG_PAGE_SIZE_4KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_SZ0
+# elif defined(CONFIG_PAGE_SIZE_64KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_SZ1
+# endif
+#endif
+
+#if defined(CONFIG_X2TLB)
+# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ2)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ2)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ1 | _PAGE_EXT_ESZ2)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ3)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ2 | _PAGE_EXT_ESZ3)
+# endif
+#else
+# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#  define _PAGE_SZHUGE  (_PAGE_SZ1)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
+#  define _PAGE_SZHUGE  (_PAGE_SZ0 | _PAGE_SZ1)
+# endif
+#endif
+
+/*
+ * Stub out _PAGE_SZHUGE if we don't have a good definition for it,
+ * to make pte_mkhuge() happy.
+ */
+#ifndef _PAGE_SZHUGE
+# define _PAGE_SZHUGE   (_PAGE_FLAGS_HARD)
+#endif
+
+#define _PAGE_CHG_MASK \
+        (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY)
+
+#ifndef __ASSEMBLY__
+
+#if defined(CONFIG_X2TLB) /* SH-X2 TLB */
+#define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ  | \
+                                           _PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_USER_READ  | \
+                                           _PAGE_EXT_USER_WRITE))
+
+#define PAGE_EXECREAD   __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_EXEC | \
+                                           _PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_USER_EXEC | \
+                                           _PAGE_EXT_USER_READ))
+
+#define PAGE_COPY       PAGE_EXECREAD
+
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_USER_READ))
+
+#define PAGE_WRITEONLY  __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_USER_WRITE))
+
+#define PAGE_RWX        __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_KERN_READ  | \
+                                           _PAGE_EXT_KERN_EXEC  | \
+                                           _PAGE_EXT_USER_WRITE | \
+                                           _PAGE_EXT_USER_READ  | \
+                                           _PAGE_EXT_USER_EXEC))
+
+#define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | \
+                                 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_KERN_EXEC))
+
+#define PAGE_KERNEL_NOCACHE \
+                        __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
+                                 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
+                                 _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_KERN_EXEC))
+
+#define PAGE_KERNEL_RO  __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | \
+                                 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_KERN_EXEC))
+
+#define PAGE_KERNEL_PCC(slot, type) \
+                        __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_KERN_EXEC) \
+                                 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
+                                 (type))
+
+#elif defined(CONFIG_MMU) /* SH-X TLB */
+#define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
+                                 _PAGE_CACHABLE | _PAGE_ACCESSED | \
+                                 _PAGE_FLAGS_HARD)
+
+#define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+
+#define PAGE_EXECREAD   PAGE_READONLY
+#define PAGE_RWX        PAGE_SHARED
+#define PAGE_WRITEONLY  PAGE_SHARED
+
+#define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | \
+                                 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
+
+#define PAGE_KERNEL_NOCACHE \
+                        __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
+                                 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
+                                 _PAGE_FLAGS_HARD)
+
+#define PAGE_KERNEL_RO  __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | \
+                                 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
+
+#define PAGE_KERNEL_PCC(slot, type) \
+                        __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
+                                 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
+                                 (type))
+#else /* no mmu */
+#define PAGE_NONE               __pgprot(0)
+#define PAGE_SHARED             __pgprot(0)
+#define PAGE_COPY               __pgprot(0)
+#define PAGE_EXECREAD           __pgprot(0)
+#define PAGE_RWX                __pgprot(0)
+#define PAGE_READONLY           __pgprot(0)
+#define PAGE_WRITEONLY          __pgprot(0)
+#define PAGE_KERNEL             __pgprot(0)
+#define PAGE_KERNEL_NOCACHE     __pgprot(0)
+#define PAGE_KERNEL_RO          __pgprot(0)
+
+#define PAGE_KERNEL_PCC(slot, type) \
+                                __pgprot(0)
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Certain architectures need to do special things when PTEs
+ * within a page table are directly modified.  Thus, the following
+ * hook is made available.
+ */
+#ifdef CONFIG_X2TLB
+static inline void set_pte(pte_t *ptep, pte_t pte)
+{
+        ptep->pte_high = pte.pte_high;
+        smp_wmb();
+        ptep->pte_low = pte.pte_low;
+}
+#else
+#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
+#endif
+
+#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+
+/*
+ * (pmds are folded into pgds so this doesn't get actually called,
+ * but the define is needed for a generic inline function.)
+ */
+#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
+
+#define pfn_pte(pfn, prot) \
+        __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#define pfn_pmd(pfn, prot) \
+        __pmd(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
+
+#define pte_none(x)             (!pte_val(x))
+#define pte_present(x)          ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
+
+#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
+
+#define pmd_none(x)     (!pmd_val(x))
+#define pmd_present(x)  (pmd_val(x))
+#define pmd_clear(xp)   do { set_pmd(xp, __pmd(0)); } while (0)
+#define pmd_bad(x)      (pmd_val(x) & ~PAGE_MASK)
+
+#define pages_to_mb(x)  ((x) >> (20-PAGE_SHIFT))
+#define pte_page(x)     pfn_to_page(pte_pfn(x))
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+#define pte_not_present(pte)    (!((pte).pte_low & _PAGE_PRESENT))
+#define pte_dirty(pte)          ((pte).pte_low & _PAGE_DIRTY)
+#define pte_young(pte)          ((pte).pte_low & _PAGE_ACCESSED)
+#define pte_file(pte)           ((pte).pte_low & _PAGE_FILE)
+#define pte_special(pte)        (0)
+
+#ifdef CONFIG_X2TLB
+#define pte_write(pte)          ((pte).pte_high & _PAGE_EXT_USER_WRITE)
+#else
+#define pte_write(pte)          ((pte).pte_low & _PAGE_RW)
+#endif
+
+#define PTE_BIT_FUNC(h,fn,op) \
+static inline pte_t pte_##fn(pte_t pte) { pte.pte_##h op; return pte; }
+
+#ifdef CONFIG_X2TLB
+/*
+ * We cheat a bit in the SH-X2 TLB case. As the permission bits are
+ * individually toggled (and user permissions are entirely decoupled from
+ * kernel permissions), we attempt to couple them a bit more sanely here.
+ */
+PTE_BIT_FUNC(high, wrprotect, &= ~_PAGE_EXT_USER_WRITE);
+PTE_BIT_FUNC(high, mkwrite, |= _PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE);
+PTE_BIT_FUNC(high, mkhuge, |= _PAGE_SZHUGE);
+#else
+PTE_BIT_FUNC(low, wrprotect, &= ~_PAGE_RW);
+PTE_BIT_FUNC(low, mkwrite, |= _PAGE_RW);
+PTE_BIT_FUNC(low, mkhuge, |= _PAGE_SZHUGE);
+#endif
+
+PTE_BIT_FUNC(low, mkclean, &= ~_PAGE_DIRTY);
+PTE_BIT_FUNC(low, mkdirty, |= _PAGE_DIRTY);
+PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED);
+PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
+
+static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
+
+/*
+ * Macro and implementation to make a page protection as uncachable.
+ */
+#define pgprot_writecombine(prot) \
+        __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
+
+#define pgprot_noncached         pgprot_writecombine
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ *
+ * extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
+ */
+#define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        pte.pte_low &= _PAGE_CHG_MASK;
+        pte.pte_low |= pgprot_val(newprot);
+
+#ifdef CONFIG_X2TLB
+        pte.pte_high |= pgprot_val(newprot) >> 32;
+#endif
+
+        return pte;
+}
+
+#define pmd_page_vaddr(pmd)     ((unsigned long)pmd_val(pmd))
+#define pmd_page(pmd)           (virt_to_page(pmd_val(pmd)))
+
+/* to find an entry in a page-table-directory. */
+#define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
+#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(address)   pgd_offset(&init_mm, address)
+
+/* Find an entry in the third-level page table.. */
+#define pte_index(address)      ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset_kernel(dir, address) \
+        ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address))
+#define pte_offset_map(dir, address)            pte_offset_kernel(dir, address)
+#define pte_offset_map_nested(dir, address)     pte_offset_kernel(dir, address)
+
+#define pte_unmap(pte)          do { } while (0)
+#define pte_unmap_nested(pte)   do { } while (0)
+
+#ifdef CONFIG_X2TLB
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \
+               &(e), (e).pte_high, (e).pte_low)
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
+#else
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+#endif
+
+/*
+ * Encode and de-code a swap entry
+ *
+ * Constraints:
+ *      _PAGE_FILE at bit 0
+ *      _PAGE_PRESENT at bit 8
+ *      _PAGE_PROTNONE at bit 9
+ *
+ * For the normal case, we encode the swap type into bits 0:7 and the
+ * swap offset into bits 10:30. For the 64-bit PTE case, we keep the
+ * preserved bits in the low 32-bits and use the upper 32 as the swap
+ * offset (along with a 5-bit type), following the same approach as x86
+ * PAE. This keeps the logic quite simple, and allows for a full 32
+ * PTE_FILE_MAX_BITS, as opposed to the 29-bits we're constrained with
+ * in the pte_low case.
+ *
+ * As is evident by the Alpha code, if we ever get a 64-bit unsigned
+ * long (swp_entry_t) to match up with the 64-bit PTEs, this all becomes
+ * much cleaner..
+ *
+ * NOTE: We should set ZEROs at the position of _PAGE_PRESENT
+ *       and _PAGE_PROTNONE bits
+ */
+#ifdef CONFIG_X2TLB
+#define __swp_type(x)                   ((x).val & 0x1f)
+#define __swp_offset(x)                 ((x).val >> 5)
+#define __swp_entry(type, offset)       ((swp_entry_t){ (type) | (offset) << 5})
+#define __pte_to_swp_entry(pte)         ((swp_entry_t){ (pte).pte_high })
+#define __swp_entry_to_pte(x)           ((pte_t){ 0, (x).val })
+
+/*
+ * Encode and decode a nonlinear file mapping entry
+ */
+#define pte_to_pgoff(pte)               ((pte).pte_high)
+#define pgoff_to_pte(off)               ((pte_t) { _PAGE_FILE, (off) })
+
+#define PTE_FILE_MAX_BITS               32
+#else
+#define __swp_type(x)                   ((x).val & 0xff)
+#define __swp_offset(x)                 ((x).val >> 10)
+#define __swp_entry(type, offset)       ((swp_entry_t){(type) | (offset) <<10})
+
+#define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) >> 1 })
+#define __swp_entry_to_pte(x)           ((pte_t) { (x).val << 1 })
+
+/*
+ * Encode and decode a nonlinear file mapping entry
+ */
+#define PTE_FILE_MAX_BITS       29
+#define pte_to_pgoff(pte)       (pte_val(pte) >> 1)
+#define pgoff_to_pte(off)       ((pte_t) { ((off) << 1) | _PAGE_FILE })
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_SH_PGTABLE_32_H */
diff --git a/arch/sh/include/asm/pgtable_64.h b/arch/sh/include/asm/pgtable_64.h
new file mode 100644
index 000000000000..c78990cda557
--- /dev/null
+++ b/arch/sh/include/asm/pgtable_64.h
@@ -0,0 +1,314 @@
+#ifndef __ASM_SH_PGTABLE_64_H
+#define __ASM_SH_PGTABLE_64_H
+
+/*
+ * include/asm-sh/pgtable_64.h
+ *
+ * This file contains the functions and defines necessary to modify and use
+ * the SuperH page table tree.
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003, 2004  Paul Mundt
+ * Copyright (C) 2003, 2004  Richard Curnow
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/threads.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+
+/*
+ * Error outputs.
+ */
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+/*
+ * Table setting routines. Used within arch/mm only.
+ */
+#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
+
+static __inline__ void set_pte(pte_t *pteptr, pte_t pteval)
+{
+        unsigned long long x = ((unsigned long long) pteval.pte_low);
+        unsigned long long *xp = (unsigned long long *) pteptr;
+        /*
+         * Sign-extend based on NPHYS.
+         */
+        *(xp) = (x & NPHYS_SIGN) ? (x | NPHYS_MASK) : x;
+}
+#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+
+static __inline__ void pmd_set(pmd_t *pmdp,pte_t *ptep)
+{
+        pmd_val(*pmdp) = (unsigned long) ptep;
+}
+
+/*
+ * PGD defines. Top level.
+ */
+
+/* To find an entry in a generic PGD. */
+#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
+#define __pgd_offset(address) pgd_index(address)
+#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
+
+/* To find an entry in a kernel PGD. */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/*
+ * PMD level access routines. Same notes as above.
+ */
+#define _PMD_EMPTY              0x0
+/* Either the PMD is empty or present, it's not paged out */
+#define pmd_present(pmd_entry)  (pmd_val(pmd_entry) & _PAGE_PRESENT)
+#define pmd_clear(pmd_entry_p)  (set_pmd((pmd_entry_p), __pmd(_PMD_EMPTY)))
+#define pmd_none(pmd_entry)     (pmd_val((pmd_entry)) == _PMD_EMPTY)
+#define pmd_bad(pmd_entry)      ((pmd_val(pmd_entry) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
+
+#define pmd_page_vaddr(pmd_entry) \
+        ((unsigned long) __va(pmd_val(pmd_entry) & PAGE_MASK))
+
+#define pmd_page(pmd) \
+        (virt_to_page(pmd_val(pmd)))
+
+/* PMD to PTE dereferencing */
+#define pte_index(address) \
+                ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+
+#define pte_offset_kernel(dir, addr) \
+                ((pte_t *) ((pmd_val(*(dir))) & PAGE_MASK) + pte_index((addr)))
+
+#define pte_offset_map(dir,addr)        pte_offset_kernel(dir, addr)
+#define pte_offset_map_nested(dir,addr) pte_offset_kernel(dir, addr)
+#define pte_unmap(pte)          do { } while (0)
+#define pte_unmap_nested(pte)   do { } while (0)
+
+#ifndef __ASSEMBLY__
+#define IOBASE_VADDR    0xff000000
+#define IOBASE_END      0xffffffff
+
+/*
+ * PTEL coherent flags.
+ * See Chapter 17 ST50 CPU Core Volume 1, Architecture.
+ */
+/* The bits that are required in the SH-5 TLB are placed in the h/w-defined
+   positions, to avoid expensive bit shuffling on every refill.  The remaining
+   bits are used for s/w purposes and masked out on each refill.
+
+   Note, the PTE slots are used to hold data of type swp_entry_t when a page is
+   swapped out.  Only the _PAGE_PRESENT flag is significant when the page is
+   swapped out, and it must be placed so that it doesn't overlap either the
+   type or offset fields of swp_entry_t.  For x86, offset is at [31:8] and type
+   at [6:1], with _PAGE_PRESENT at bit 0 for both pte_t and swp_entry_t.  This
+   scheme doesn't map to SH-5 because bit [0] controls cacheability.  So bit
+   [2] is used for _PAGE_PRESENT and the type field of swp_entry_t is split
+   into 2 pieces.  That is handled by SWP_ENTRY and SWP_TYPE below. */
+#define _PAGE_WT        0x001  /* CB0: if cacheable, 1->write-thru, 0->write-back */
+#define _PAGE_DEVICE    0x001  /* CB0: if uncacheable, 1->device (i.e. no write-combining or reordering at bus level) */
+#define _PAGE_CACHABLE  0x002  /* CB1: uncachable/cachable */
+#define _PAGE_PRESENT   0x004  /* software: page referenced */
+#define _PAGE_FILE      0x004  /* software: only when !present */
+#define _PAGE_SIZE0     0x008  /* SZ0-bit : size of page */
+#define _PAGE_SIZE1     0x010  /* SZ1-bit : size of page */
+#define _PAGE_SHARED    0x020  /* software: reflects PTEH's SH */
+#define _PAGE_READ      0x040  /* PR0-bit : read access allowed */
+#define _PAGE_EXECUTE   0x080  /* PR1-bit : execute access allowed */
+#define _PAGE_WRITE     0x100  /* PR2-bit : write access allowed */
+#define _PAGE_USER      0x200  /* PR3-bit : user space access allowed */
+#define _PAGE_DIRTY     0x400  /* software: page accessed in write */
+#define _PAGE_ACCESSED  0x800  /* software: page referenced */
+
+/* Mask which drops software flags */
+#define _PAGE_FLAGS_HARDWARE_MASK       0xfffffffffffff3dbLL
+
+/*
+ * HugeTLB support
+ */
+#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#define _PAGE_SZHUGE    (_PAGE_SIZE0)
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
+#define _PAGE_SZHUGE    (_PAGE_SIZE1)
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512MB)
+#define _PAGE_SZHUGE    (_PAGE_SIZE0 | _PAGE_SIZE1)
+#endif
+
+/*
+ * Stub out _PAGE_SZHUGE if we don't have a good definition for it,
+ * to make pte_mkhuge() happy.
+ */
+#ifndef _PAGE_SZHUGE
+# define _PAGE_SZHUGE   (0)
+#endif
+
+/*
+ * Default flags for a Kernel page.
+ * This is fundametally also SHARED because the main use of this define
+ * (other than for PGD/PMD entries) is for the VMALLOC pool which is
+ * contextless.
+ *
+ * _PAGE_EXECUTE is required for modules
+ *
+ */
+#define _KERNPG_TABLE   (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
+                         _PAGE_EXECUTE | \
+                         _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_DIRTY | \
+                         _PAGE_SHARED)
+
+/* Default flags for a User page */
+#define _PAGE_TABLE     (_KERNPG_TABLE | _PAGE_USER)
+
+#define _PAGE_CHG_MASK  (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
+
+/*
+ * We have full permissions (Read/Write/Execute/Shared).
+ */
+#define _PAGE_COMMON    (_PAGE_PRESENT | _PAGE_USER | \
+                         _PAGE_CACHABLE | _PAGE_ACCESSED)
+
+#define PAGE_NONE       __pgprot(_PAGE_CACHABLE | _PAGE_ACCESSED)
+#define PAGE_SHARED     __pgprot(_PAGE_COMMON | _PAGE_READ | _PAGE_WRITE | \
+                                 _PAGE_SHARED)
+#define PAGE_EXECREAD   __pgprot(_PAGE_COMMON | _PAGE_READ | _PAGE_EXECUTE)
+
+/*
+ * We need to include PAGE_EXECUTE in PAGE_COPY because it is the default
+ * protection mode for the stack.
+ */
+#define PAGE_COPY       PAGE_EXECREAD
+
+#define PAGE_READONLY   __pgprot(_PAGE_COMMON | _PAGE_READ)
+#define PAGE_WRITEONLY  __pgprot(_PAGE_COMMON | _PAGE_WRITE)
+#define PAGE_RWX        __pgprot(_PAGE_COMMON | _PAGE_READ | \
+                                 _PAGE_WRITE | _PAGE_EXECUTE)
+#define PAGE_KERNEL     __pgprot(_KERNPG_TABLE)
+
+#define PAGE_KERNEL_NOCACHE \
+                        __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
+                                 _PAGE_EXECUTE | _PAGE_ACCESSED | \
+                                 _PAGE_DIRTY | _PAGE_SHARED)
+
+/* Make it a device mapping for maximum safety (e.g. for mapping device
+   registers into user-space via /dev/map).  */
+#define pgprot_noncached(x) __pgprot(((x).pgprot & ~(_PAGE_CACHABLE)) | _PAGE_DEVICE)
+#define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
+
+/*
+ * Handling allocation failures during page table setup.
+ */
+extern void __handle_bad_pmd_kernel(pmd_t * pmd);
+#define __handle_bad_pmd(x)     __handle_bad_pmd_kernel(x)
+
+/*
+ * PTE level access routines.
+ *
+ * Note1:
+ * It's the tree walk leaf. This is physical address to be stored.
+ *
+ * Note 2:
+ * Regarding the choice of _PTE_EMPTY:
+
+   We must choose a bit pattern that cannot be valid, whether or not the page
+   is present.  bit[2]==1 => present, bit[2]==0 => swapped out.  If swapped
+   out, bits [31:8], [6:3], [1:0] are under swapper control, so only bit[7] is
+   left for us to select.  If we force bit[7]==0 when swapped out, we could use
+   the combination bit[7,2]=2'b10 to indicate an empty PTE.  Alternatively, if
+   we force bit[7]==1 when swapped out, we can use all zeroes to indicate
+   empty.  This is convenient, because the page tables get cleared to zero
+   when they are allocated.
+
+ */
+#define _PTE_EMPTY      0x0
+#define pte_present(x)  (pte_val(x) & _PAGE_PRESENT)
+#define pte_clear(mm,addr,xp)   (set_pte_at(mm, addr, xp, __pte(_PTE_EMPTY)))
+#define pte_none(x)     (pte_val(x) == _PTE_EMPTY)
+
+/*
+ * Some definitions to translate between mem_map, PTEs, and page
+ * addresses:
+ */
+
+/*
+ * Given a PTE, return the index of the mem_map[] entry corresponding
+ * to the page frame the PTE. Get the absolute physical address, make
+ * a relative physical address and translate it to an index.
+ */
+#define pte_pagenr(x)           (((unsigned long) (pte_val(x)) - \
+                                 __MEMORY_START) >> PAGE_SHIFT)
+
+/*
+ * Given a PTE, return the "struct page *".
+ */
+#define pte_page(x)             (mem_map + pte_pagenr(x))
+
+/*
+ * Return number of (down rounded) MB corresponding to x pages.
+ */
+#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
+
+
+/*
+ * The following have defined behavior only work if pte_present() is true.
+ */
+static inline int pte_dirty(pte_t pte)  { return pte_val(pte) & _PAGE_DIRTY; }
+static inline int pte_young(pte_t pte)  { return pte_val(pte) & _PAGE_ACCESSED; }
+static inline int pte_file(pte_t pte)   { return pte_val(pte) & _PAGE_FILE; }
+static inline int pte_write(pte_t pte)  { return pte_val(pte) & _PAGE_WRITE; }
+static inline int pte_special(pte_t pte){ return 0; }
+
+static inline pte_t pte_wrprotect(pte_t pte)    { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_WRITE)); return pte; }
+static inline pte_t pte_mkclean(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; }
+static inline pte_t pte_mkold(pte_t pte)        { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; }
+static inline pte_t pte_mkwrite(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_WRITE)); return pte; }
+static inline pte_t pte_mkdirty(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
+static inline pte_t pte_mkyoung(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
+static inline pte_t pte_mkhuge(pte_t pte)       { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SZHUGE)); return pte; }
+static inline pte_t pte_mkspecial(pte_t pte)    { return pte; }
+
+
+/*
+ * Conversion functions: convert a page and protection to a page entry.
+ *
+ * extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
+ */
+#define mk_pte(page,pgprot)                                                     \
+({                                                                              \
+        pte_t __pte;                                                            \
+                                                                                \
+        set_pte(&__pte, __pte((((page)-mem_map) << PAGE_SHIFT) |                \
+                __MEMORY_START | pgprot_val((pgprot))));                        \
+        __pte;                                                                  \
+})
+
+/*
+ * This takes a (absolute) physical page address that is used
+ * by the remapping functions
+ */
+#define mk_pte_phys(physpage, pgprot) \
+({ pte_t __pte; set_pte(&__pte, __pte(physpage | pgprot_val(pgprot))); __pte; })
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{ set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; }
+
+/* Encode and decode a swap entry */
+#define __swp_type(x)                   (((x).val & 3) + (((x).val >> 1) & 0x3c))
+#define __swp_offset(x)                 ((x).val >> 8)
+#define __swp_entry(type, offset)       ((swp_entry_t) { ((offset << 8) + ((type & 0x3c) << 1) + (type & 3)) })
+#define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
+
+/* Encode and decode a nonlinear file mapping entry */
+#define PTE_FILE_MAX_BITS               29
+#define pte_to_pgoff(pte)               (pte_val(pte))
+#define pgoff_to_pte(off)               ((pte_t) { (off) | _PAGE_FILE })
+
+#endif /* !__ASSEMBLY__ */
+
+#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#define pfn_pmd(pfn, prot)      __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+
+#endif /* __ASM_SH_PGTABLE_64_H */
diff --git a/arch/sh/include/asm/pm.h b/arch/sh/include/asm/pm.h
new file mode 100644
index 000000000000..56fdbd6b1c94
--- /dev/null
+++ b/arch/sh/include/asm/pm.h
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright 2006 (c) Andriy Skulysh <askulysh@gmail.com>
+ *
+ */
+#ifndef __ASM_SH_PM_H
+#define __ASM_SH_PM_H
+
+extern u8 wakeup_start;
+extern u8 wakeup_end;
+
+void pm_enter(void);
+
+#endif
diff --git a/arch/sh/include/asm/poll.h b/arch/sh/include/asm/poll.h
new file mode 100644
index 000000000000..c98509d3149e
--- /dev/null
+++ b/arch/sh/include/asm/poll.h
@@ -0,0 +1 @@
+#include <asm-generic/poll.h>
diff --git a/arch/sh/include/asm/posix_types.h b/arch/sh/include/asm/posix_types.h
new file mode 100644
index 000000000000..4eeb723aee7e
--- /dev/null
+++ b/arch/sh/include/asm/posix_types.h
@@ -0,0 +1,13 @@
+#ifdef __KERNEL__
+# ifdef CONFIG_SUPERH32
+#  include "posix_types_32.h"
+# else
+#  include "posix_types_64.h"
+# endif
+#else
+# ifdef __SH5__
+#  include "posix_types_64.h"
+# else
+#  include "posix_types_32.h"
+# endif
+#endif /* __KERNEL__ */
diff --git a/arch/sh/include/asm/posix_types_32.h b/arch/sh/include/asm/posix_types_32.h
new file mode 100644
index 000000000000..0a3d2f54ab27
--- /dev/null
+++ b/arch/sh/include/asm/posix_types_32.h
@@ -0,0 +1,122 @@
+#ifndef __ASM_SH_POSIX_TYPES_H
+#define __ASM_SH_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long   __kernel_ino_t;
+typedef unsigned short  __kernel_mode_t;
+typedef unsigned short  __kernel_nlink_t;
+typedef long            __kernel_off_t;
+typedef int             __kernel_pid_t;
+typedef unsigned short  __kernel_ipc_pid_t;
+typedef unsigned short  __kernel_uid_t;
+typedef unsigned short  __kernel_gid_t;
+typedef unsigned int    __kernel_size_t;
+typedef int             __kernel_ssize_t;
+typedef int             __kernel_ptrdiff_t;
+typedef long            __kernel_time_t;
+typedef long            __kernel_suseconds_t;
+typedef long            __kernel_clock_t;
+typedef int             __kernel_timer_t;
+typedef int             __kernel_clockid_t;
+typedef int             __kernel_daddr_t;
+typedef char *          __kernel_caddr_t;
+typedef unsigned short  __kernel_uid16_t;
+typedef unsigned short  __kernel_gid16_t;
+typedef unsigned int    __kernel_uid32_t;
+typedef unsigned int    __kernel_gid32_t;
+
+typedef unsigned short  __kernel_old_uid_t;
+typedef unsigned short  __kernel_old_gid_t;
+typedef unsigned short  __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long       __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+        int     val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+        int     __val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef  __FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef  __FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+
+#undef  __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{ 
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef  __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+        unsigned long *__tmp = __p->fds_bits;
+        int __i;
+
+        if (__builtin_constant_p(__FDSET_LONGS)) {
+                switch (__FDSET_LONGS) {
+                case 16:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        __tmp[ 4] = 0; __tmp[ 5] = 0;
+                        __tmp[ 6] = 0; __tmp[ 7] = 0;
+                        __tmp[ 8] = 0; __tmp[ 9] = 0;
+                        __tmp[10] = 0; __tmp[11] = 0;
+                        __tmp[12] = 0; __tmp[13] = 0;
+                        __tmp[14] = 0; __tmp[15] = 0;
+                        return;
+
+                case 8:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        __tmp[ 4] = 0; __tmp[ 5] = 0;
+                        __tmp[ 6] = 0; __tmp[ 7] = 0;
+                        return;
+
+                case 4:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        return;
+                }
+        }
+        __i = __FDSET_LONGS;
+        while (__i) {
+                __i--;
+                *__tmp = 0;
+                __tmp++;
+        }
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* __ASM_SH_POSIX_TYPES_H */
diff --git a/arch/sh/include/asm/posix_types_64.h b/arch/sh/include/asm/posix_types_64.h
new file mode 100644
index 000000000000..0620317a6f0f
--- /dev/null
+++ b/arch/sh/include/asm/posix_types_64.h
@@ -0,0 +1,131 @@
+#ifndef __ASM_SH64_POSIX_TYPES_H
+#define __ASM_SH64_POSIX_TYPES_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * include/asm-sh64/posix_types.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003  Paul Mundt
+ *
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long   __kernel_ino_t;
+typedef unsigned short  __kernel_mode_t;
+typedef unsigned short  __kernel_nlink_t;
+typedef long            __kernel_off_t;
+typedef int             __kernel_pid_t;
+typedef unsigned short  __kernel_ipc_pid_t;
+typedef unsigned short  __kernel_uid_t;
+typedef unsigned short  __kernel_gid_t;
+typedef long unsigned int       __kernel_size_t;
+typedef int             __kernel_ssize_t;
+typedef int             __kernel_ptrdiff_t;
+typedef long            __kernel_time_t;
+typedef long            __kernel_suseconds_t;
+typedef long            __kernel_clock_t;
+typedef int             __kernel_timer_t;
+typedef int             __kernel_clockid_t;
+typedef int             __kernel_daddr_t;
+typedef char *          __kernel_caddr_t;
+typedef unsigned short  __kernel_uid16_t;
+typedef unsigned short  __kernel_gid16_t;
+typedef unsigned int    __kernel_uid32_t;
+typedef unsigned int    __kernel_gid32_t;
+
+typedef unsigned short  __kernel_old_uid_t;
+typedef unsigned short  __kernel_old_gid_t;
+typedef unsigned short  __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long       __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+        int     val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+        int     __val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef  __FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef  __FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+
+#undef  __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef  __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+        unsigned long *__tmp = __p->fds_bits;
+        int __i;
+
+        if (__builtin_constant_p(__FDSET_LONGS)) {
+                switch (__FDSET_LONGS) {
+                case 16:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        __tmp[ 4] = 0; __tmp[ 5] = 0;
+                        __tmp[ 6] = 0; __tmp[ 7] = 0;
+                        __tmp[ 8] = 0; __tmp[ 9] = 0;
+                        __tmp[10] = 0; __tmp[11] = 0;
+                        __tmp[12] = 0; __tmp[13] = 0;
+                        __tmp[14] = 0; __tmp[15] = 0;
+                        return;
+
+                case 8:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        __tmp[ 4] = 0; __tmp[ 5] = 0;
+                        __tmp[ 6] = 0; __tmp[ 7] = 0;
+                        return;
+
+                case 4:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        return;
+                }
+        }
+        __i = __FDSET_LONGS;
+        while (__i) {
+                __i--;
+                *__tmp = 0;
+                __tmp++;
+        }
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* __ASM_SH64_POSIX_TYPES_H */
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
new file mode 100644
index 000000000000..15d9f92ca383
--- /dev/null
+++ b/arch/sh/include/asm/processor.h
@@ -0,0 +1,66 @@
+#ifndef __ASM_SH_PROCESSOR_H
+#define __ASM_SH_PROCESSOR_H
+
+#include <asm/cpu-features.h>
+#include <asm/segment.h>
+
+#ifndef __ASSEMBLY__
+/*
+ *  CPU type and hardware bug flags. Kept separately for each CPU.
+ *
+ *  Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry
+ *  in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c
+ *  for parsing the subtype in get_cpu_subtype().
+ */
+enum cpu_type {
+        /* SH-2 types */
+        CPU_SH7619,
+
+        /* SH-2A types */
+        CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
+
+        /* SH-3 types */
+        CPU_SH7705, CPU_SH7706, CPU_SH7707,
+        CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
+        CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
+        CPU_SH7720, CPU_SH7721, CPU_SH7729,
+
+        /* SH-4 types */
+        CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
+        CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
+
+        /* SH-4A types */
+        CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
+        CPU_SH7723, CPU_SHX3,
+
+        /* SH4AL-DSP types */
+        CPU_SH7343, CPU_SH7722, CPU_SH7366,
+
+        /* SH-5 types */
+        CPU_SH5_101, CPU_SH5_103,
+
+        /* Unknown subtype */
+        CPU_SH_NONE
+};
+
+/* Forward decl */
+struct sh_cpuinfo;
+
+/* arch/sh/kernel/setup.c */
+const char *get_cpu_subtype(struct sh_cpuinfo *c);
+
+#ifdef CONFIG_VSYSCALL
+int vsyscall_init(void);
+#else
+#define vsyscall_init() do { } while (0)
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_SUPERH32
+# include "processor_32.h"
+#else
+# include "processor_64.h"
+#endif
+
+#endif /* __ASM_SH_PROCESSOR_H */
diff --git a/arch/sh/include/asm/processor_32.h b/arch/sh/include/asm/processor_32.h
new file mode 100644
index 000000000000..0dadd75bd93c
--- /dev/null
+++ b/arch/sh/include/asm/processor_32.h
@@ -0,0 +1,216 @@
+/*
+ * include/asm-sh/processor.h
+ *
+ * Copyright (C) 1999, 2000  Niibe Yutaka
+ * Copyright (C) 2002, 2003  Paul Mundt
+ */
+
+#ifndef __ASM_SH_PROCESSOR_32_H
+#define __ASM_SH_PROCESSOR_32_H
+#ifdef __KERNEL__
+
+#include <linux/compiler.h>
+#include <asm/page.h>
+#include <asm/types.h>
+#include <asm/cache.h>
+#include <asm/ptrace.h>
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ void *pc; __asm__("mova  1f, %0\n.align 2\n1:":"=z" (pc)); pc; })
+
+/* Core Processor Version Register */
+#define CCN_PVR         0xff000030
+#define CCN_CVR         0xff000040
+#define CCN_PRR         0xff000044
+
+struct sh_cpuinfo {
+        unsigned int type;
+        int cut_major, cut_minor;
+        unsigned long loops_per_jiffy;
+        unsigned long asid_cache;
+
+        struct cache_info icache;       /* Primary I-cache */
+        struct cache_info dcache;       /* Primary D-cache */
+        struct cache_info scache;       /* Secondary cache */
+
+        unsigned long flags;
+} __attribute__ ((aligned(L1_CACHE_BYTES)));
+
+extern struct sh_cpuinfo cpu_data[];
+#define boot_cpu_data cpu_data[0]
+#define current_cpu_data cpu_data[smp_processor_id()]
+#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
+
+/*
+ * User space process size: 2GB.
+ *
+ * Since SH7709 and SH7750 have "area 7", we can't use 0x7c000000--0x7fffffff
+ */
+#define TASK_SIZE       0x7c000000UL
+
+#define STACK_TOP       TASK_SIZE
+#define STACK_TOP_MAX   STACK_TOP
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE      (TASK_SIZE / 3)
+
+/*
+ * Bit of SR register
+ *
+ * FD-bit:
+ *     When it's set, it means the processor doesn't have right to use FPU,
+ *     and it results exception when the floating operation is executed.
+ *
+ * IMASK-bit:
+ *     Interrupt level mask
+ */
+#define SR_DSP          0x00001000
+#define SR_IMASK        0x000000f0
+#define SR_FD           0x00008000
+
+/*
+ * FPU structure and data
+ */
+
+struct sh_fpu_hard_struct {
+        unsigned long fp_regs[16];
+        unsigned long xfp_regs[16];
+        unsigned long fpscr;
+        unsigned long fpul;
+
+        long status; /* software status information */
+};
+
+/* Dummy fpu emulator  */
+struct sh_fpu_soft_struct {
+        unsigned long fp_regs[16];
+        unsigned long xfp_regs[16];
+        unsigned long fpscr;
+        unsigned long fpul;
+
+        unsigned char lookahead;
+        unsigned long entry_pc;
+};
+
+union sh_fpu_union {
+        struct sh_fpu_hard_struct hard;
+        struct sh_fpu_soft_struct soft;
+};
+
+struct thread_struct {
+        /* Saved registers when thread is descheduled */
+        unsigned long sp;
+        unsigned long pc;
+
+        /* Hardware debugging registers */
+        unsigned long ubc_pc;
+
+        /* floating point info */
+        union sh_fpu_union fpu;
+};
+
+/* Count of active tasks with UBC settings */
+extern int ubc_usercnt;
+
+#define INIT_THREAD  {                                          \
+        .sp = sizeof(init_stack) + (long) &init_stack,          \
+}
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ */
+#define start_thread(regs, new_pc, new_sp)       \
+        set_fs(USER_DS);                         \
+        regs->pr = 0;                            \
+        regs->sr = SR_FD;       /* User mode. */ \
+        regs->pc = new_pc;                       \
+        regs->regs[15] = new_sp
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+struct mm_struct;
+
+/* Free all resources held by a thread. */
+extern void release_thread(struct task_struct *);
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)    do { } while (0)
+
+/*
+ * create a kernel thread without removing it from tasklists
+ */
+extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
+
+/* Copy and release all segment info associated with a VM */
+#define copy_segments(p, mm)    do { } while(0)
+#define release_segments(mm)    do { } while(0)
+
+/*
+ * FPU lazy state save handling.
+ */
+
+static __inline__ void disable_fpu(void)
+{
+        unsigned long __dummy;
+
+        /* Set FD flag in SR */
+        __asm__ __volatile__("stc       sr, %0\n\t"
+                             "or        %1, %0\n\t"
+                             "ldc       %0, sr"
+                             : "=&r" (__dummy)
+                             : "r" (SR_FD));
+}
+
+static __inline__ void enable_fpu(void)
+{
+        unsigned long __dummy;
+
+        /* Clear out FD flag in SR */
+        __asm__ __volatile__("stc       sr, %0\n\t"
+                             "and       %1, %0\n\t"
+                             "ldc       %0, sr"
+                             : "=&r" (__dummy)
+                             : "r" (~SR_FD));
+}
+
+/* Double presision, NANS as NANS, rounding to nearest, no exceptions */
+#define FPSCR_INIT  0x00080000
+
+#define FPSCR_CAUSE_MASK        0x0001f000      /* Cause bits */
+#define FPSCR_FLAG_MASK         0x0000007c      /* Flag bits */
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+#define thread_saved_pc(tsk)    (tsk->thread.pc)
+
+void show_trace(struct task_struct *tsk, unsigned long *sp,
+                struct pt_regs *regs);
+extern unsigned long get_wchan(struct task_struct *p);
+
+#define KSTK_EIP(tsk)  (task_pt_regs(tsk)->pc)
+#define KSTK_ESP(tsk)  (task_pt_regs(tsk)->regs[15])
+
+#define cpu_sleep()     __asm__ __volatile__ ("sleep" : : : "memory")
+#define cpu_relax()     barrier()
+
+#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH3) || \
+    defined(CONFIG_CPU_SH4)
+#define PREFETCH_STRIDE         L1_CACHE_BYTES
+#define ARCH_HAS_PREFETCH
+#define ARCH_HAS_PREFETCHW
+static inline void prefetch(void *x)
+{
+        __asm__ __volatile__ ("pref @%0\n\t" : : "r" (x) : "memory");
+}
+
+#define prefetchw(x)    prefetch(x)
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_PROCESSOR_32_H */
diff --git a/arch/sh/include/asm/processor_64.h b/arch/sh/include/asm/processor_64.h
new file mode 100644
index 000000000000..770d5169983b
--- /dev/null
+++ b/arch/sh/include/asm/processor_64.h
@@ -0,0 +1,275 @@
+#ifndef __ASM_SH_PROCESSOR_64_H
+#define __ASM_SH_PROCESSOR_64_H
+
+/*
+ * include/asm-sh/processor_64.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003  Paul Mundt
+ * Copyright (C) 2004  Richard Curnow
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASSEMBLY__
+
+#include <linux/compiler.h>
+#include <asm/page.h>
+#include <asm/types.h>
+#include <asm/cache.h>
+#include <asm/ptrace.h>
+#include <cpu/registers.h>
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ \
+void *pc; \
+unsigned long long __dummy = 0; \
+__asm__("gettr  tr0, %1\n\t" \
+        "pta    4, tr0\n\t" \
+        "gettr  tr0, %0\n\t" \
+        "ptabs  %1, tr0\n\t"    \
+        :"=r" (pc), "=r" (__dummy) \
+        : "1" (__dummy)); \
+pc; })
+
+/*
+ * TLB information structure
+ *
+ * Defined for both I and D tlb, per-processor.
+ */
+struct tlb_info {
+        unsigned long long next;
+        unsigned long long first;
+        unsigned long long last;
+
+        unsigned int entries;
+        unsigned int step;
+
+        unsigned long flags;
+};
+
+struct sh_cpuinfo {
+        enum cpu_type type;
+        unsigned long loops_per_jiffy;
+        unsigned long asid_cache;
+
+        unsigned int cpu_clock, master_clock, bus_clock, module_clock;
+
+        /* Cache info */
+        struct cache_info icache;
+        struct cache_info dcache;
+        struct cache_info scache;
+
+        /* TLB info */
+        struct tlb_info itlb;
+        struct tlb_info dtlb;
+
+        unsigned long flags;
+};
+
+extern struct sh_cpuinfo cpu_data[];
+#define boot_cpu_data cpu_data[0]
+#define current_cpu_data cpu_data[smp_processor_id()]
+#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
+
+#endif
+
+/*
+ * User space process size: 2GB - 4k.
+ */
+#define TASK_SIZE       0x7ffff000UL
+
+#define STACK_TOP       TASK_SIZE
+#define STACK_TOP_MAX   STACK_TOP
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE      (TASK_SIZE / 3)
+
+/*
+ * Bit of SR register
+ *
+ * FD-bit:
+ *     When it's set, it means the processor doesn't have right to use FPU,
+ *     and it results exception when the floating operation is executed.
+ *
+ * IMASK-bit:
+ *     Interrupt level mask
+ *
+ * STEP-bit:
+ *     Single step bit
+ *
+ */
+#if defined(CONFIG_SH64_SR_WATCH)
+#define SR_MMU   0x84000000
+#else
+#define SR_MMU   0x80000000
+#endif
+
+#define SR_IMASK 0x000000f0
+#define SR_FD    0x00008000
+#define SR_SSTEP 0x08000000
+
+#ifndef __ASSEMBLY__
+
+/*
+ * FPU structure and data : require 8-byte alignment as we need to access it
+   with fld.p, fst.p
+ */
+
+struct sh_fpu_hard_struct {
+        unsigned long fp_regs[64];
+        unsigned int fpscr;
+        /* long status; * software status information */
+};
+
+#if 0
+/* Dummy fpu emulator  */
+struct sh_fpu_soft_struct {
+        unsigned long long fp_regs[32];
+        unsigned int fpscr;
+        unsigned char lookahead;
+        unsigned long entry_pc;
+};
+#endif
+
+union sh_fpu_union {
+        struct sh_fpu_hard_struct hard;
+        /* 'hard' itself only produces 32 bit alignment, yet we need
+           to access it using 64 bit load/store as well. */
+        unsigned long long alignment_dummy;
+};
+
+struct thread_struct {
+        unsigned long sp;
+        unsigned long pc;
+        /* This stores the address of the pt_regs built during a context
+           switch, or of the register save area built for a kernel mode
+           exception.  It is used for backtracing the stack of a sleeping task
+           or one that traps in kernel mode. */
+        struct pt_regs *kregs;
+        /* This stores the address of the pt_regs constructed on entry from
+           user mode.  It is a fixed value over the lifetime of a process, or
+           NULL for a kernel thread. */
+        struct pt_regs *uregs;
+
+        unsigned long trap_no, error_code;
+        unsigned long address;
+        /* Hardware debugging registers may come here */
+
+        /* floating point info */
+        union sh_fpu_union fpu;
+};
+
+#define INIT_MMAP \
+{ &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
+
+extern  struct pt_regs fake_swapper_regs;
+
+#define INIT_THREAD  {                          \
+        .sp             = sizeof(init_stack) +  \
+                          (long) &init_stack,   \
+        .pc             = 0,                    \
+        .kregs          = &fake_swapper_regs,   \
+        .uregs          = NULL,                 \
+        .trap_no        = 0,                    \
+        .error_code     = 0,                    \
+        .address        = 0,                    \
+        .fpu            = { { { 0, } }, }       \
+}
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ */
+#define SR_USER (SR_MMU | SR_FD)
+
+#define start_thread(regs, new_pc, new_sp)                      \
+        set_fs(USER_DS);                                        \
+        regs->sr = SR_USER;     /* User mode. */                \
+        regs->pc = new_pc - 4;  /* Compensate syscall exit */   \
+        regs->pc |= 1;          /* Set SHmedia ! */             \
+        regs->regs[18] = 0;                                     \
+        regs->regs[15] = new_sp
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+struct mm_struct;
+
+/* Free all resources held by a thread. */
+extern void release_thread(struct task_struct *);
+/*
+ * create a kernel thread without removing it from tasklists
+ */
+extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
+
+
+/* Copy and release all segment info associated with a VM */
+#define copy_segments(p, mm)    do { } while (0)
+#define release_segments(mm)    do { } while (0)
+#define forget_segments()       do { } while (0)
+#define prepare_to_copy(tsk)    do { } while (0)
+/*
+ * FPU lazy state save handling.
+ */
+
+static inline void disable_fpu(void)
+{
+        unsigned long long __dummy;
+
+        /* Set FD flag in SR */
+        __asm__ __volatile__("getcon    " __SR ", %0\n\t"
+                             "or        %0, %1, %0\n\t"
+                             "putcon    %0, " __SR "\n\t"
+                             : "=&r" (__dummy)
+                             : "r" (SR_FD));
+}
+
+static inline void enable_fpu(void)
+{
+        unsigned long long __dummy;
+
+        /* Clear out FD flag in SR */
+        __asm__ __volatile__("getcon    " __SR ", %0\n\t"
+                             "and       %0, %1, %0\n\t"
+                             "putcon    %0, " __SR "\n\t"
+                             : "=&r" (__dummy)
+                             : "r" (~SR_FD));
+}
+
+/* Round to nearest, no exceptions on inexact, overflow, underflow,
+   zero-divide, invalid.  Configure option for whether to flush denorms to
+   zero, or except if a denorm is encountered.  */
+#if defined(CONFIG_SH64_FPU_DENORM_FLUSH)
+#define FPSCR_INIT  0x00040000
+#else
+#define FPSCR_INIT  0x00000000
+#endif
+
+#ifdef CONFIG_SH_FPU
+/* Initialise the FP state of a task */
+void fpinit(struct sh_fpu_hard_struct *fpregs);
+#else
+#define fpinit(fpregs)  do { } while (0)
+#endif
+
+extern struct task_struct *last_task_used_math;
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+#define thread_saved_pc(tsk)    (tsk->thread.pc)
+
+extern unsigned long get_wchan(struct task_struct *p);
+
+#define KSTK_EIP(tsk)  ((tsk)->thread.pc)
+#define KSTK_ESP(tsk)  ((tsk)->thread.sp)
+
+#define cpu_relax()     barrier()
+
+#endif  /* __ASSEMBLY__ */
+#endif /* __ASM_SH_PROCESSOR_64_H */
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
new file mode 100644
index 000000000000..643ab5a7cf3b
--- /dev/null
+++ b/arch/sh/include/asm/ptrace.h
@@ -0,0 +1,130 @@
+#ifndef __ASM_SH_PTRACE_H
+#define __ASM_SH_PTRACE_H
+
+/*
+ * Copyright (C) 1999, 2000  Niibe Yutaka
+ *
+ */
+#if defined(__SH5__)
+struct pt_regs {
+        unsigned long long pc;
+        unsigned long long sr;
+        unsigned long long syscall_nr;
+        unsigned long long regs[63];
+        unsigned long long tregs[8];
+        unsigned long long pad[2];
+};
+#else
+/*
+ * GCC defines register number like this:
+ * -----------------------------
+ *       0 - 15 are integer registers
+ *      17 - 22 are control/special registers
+ *      24 - 39 fp registers
+ *      40 - 47 xd registers
+ *      48 -    fpscr register
+ * -----------------------------
+ *
+ * We follows above, except:
+ *      16 --- program counter (PC)
+ *      22 --- syscall #
+ *      23 --- floating point communication register
+ */
+#define REG_REG0         0
+#define REG_REG15       15
+
+#define REG_PC          16
+
+#define REG_PR          17
+#define REG_SR          18
+#define REG_GBR         19
+#define REG_MACH        20
+#define REG_MACL        21
+
+#define REG_SYSCALL     22
+
+#define REG_FPREG0      23
+#define REG_FPREG15     38
+#define REG_XFREG0      39
+#define REG_XFREG15     54
+
+#define REG_FPSCR       55
+#define REG_FPUL        56
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_regs {
+        unsigned long regs[16];
+        unsigned long pc;
+        unsigned long pr;
+        unsigned long sr;
+        unsigned long gbr;
+        unsigned long mach;
+        unsigned long macl;
+        long tra;
+};
+
+/*
+ * This struct defines the way the DSP registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_dspregs {
+        unsigned long   a1;
+        unsigned long   a0g;
+        unsigned long   a1g;
+        unsigned long   m0;
+        unsigned long   m1;
+        unsigned long   a0;
+        unsigned long   x0;
+        unsigned long   x1;
+        unsigned long   y0;
+        unsigned long   y1;
+        unsigned long   dsr;
+        unsigned long   rs;
+        unsigned long   re;
+        unsigned long   mod;
+};
+
+#define PTRACE_GETFDPIC         31      /* get the ELF fdpic loadmap address */
+
+#define PTRACE_GETFDPIC_EXEC    0       /* [addr] request the executable loadmap */
+#define PTRACE_GETFDPIC_INTERP  1       /* [addr] request the interpreter loadmap */
+
+#define PTRACE_GETDSPREGS       55
+#define PTRACE_SETDSPREGS       56
+#endif
+
+#ifdef __KERNEL__
+#include <asm/addrspace.h>
+
+#define user_mode(regs)                 (((regs)->sr & 0x40000000)==0)
+#define instruction_pointer(regs)       ((unsigned long)(regs)->pc)
+
+extern void show_regs(struct pt_regs *);
+
+#ifdef CONFIG_SH_DSP
+#define task_pt_regs(task) \
+        ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+                 - sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1)
+#else
+#define task_pt_regs(task) \
+        ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+                 - sizeof(unsigned long)) - 1)
+#endif
+
+static inline unsigned long profile_pc(struct pt_regs *regs)
+{
+        unsigned long pc = instruction_pointer(regs);
+
+#ifdef P2SEG
+        if (pc >= P2SEG && pc < P3SEG)
+                pc -= 0x20000000;
+#endif
+
+        return pc;
+}
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_PTRACE_H */
diff --git a/arch/sh/include/asm/push-switch.h b/arch/sh/include/asm/push-switch.h
new file mode 100644
index 000000000000..4903f9e52dd8
--- /dev/null
+++ b/arch/sh/include/asm/push-switch.h
@@ -0,0 +1,31 @@
+#ifndef __ASM_SH_PUSH_SWITCH_H
+#define __ASM_SH_PUSH_SWITCH_H
+
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/platform_device.h>
+
+struct push_switch {
+        /* switch state */
+        unsigned int            state:1;
+        /* debounce timer */
+        struct timer_list       debounce;
+        /* workqueue */
+        struct work_struct      work;
+        /* platform device, for workqueue handler */
+        struct platform_device  *pdev;
+};
+
+struct push_switch_platform_info {
+        /* IRQ handler */
+        irqreturn_t             (*irq_handler)(int irq, void *data);
+        /* Special IRQ flags */
+        unsigned int            irq_flags;
+        /* Bit location of switch */
+        unsigned int            bit;
+        /* Symbolic switch name */
+        const char              *name;
+};
+
+#endif /* __ASM_SH_PUSH_SWITCH_H */
diff --git a/arch/sh/include/asm/r7780rp.h b/arch/sh/include/asm/r7780rp.h
new file mode 100644
index 000000000000..306f7359f7d4
--- /dev/null
+++ b/arch/sh/include/asm/r7780rp.h
@@ -0,0 +1,198 @@
+#ifndef __ASM_SH_RENESAS_R7780RP_H
+#define __ASM_SH_RENESAS_R7780RP_H
+
+/* Box specific addresses.  */
+#if defined(CONFIG_SH_R7780MP)
+#define PA_BCR          0xa4000000      /* FPGA */
+#define PA_SDPOW        (-1)
+
+#define PA_IRLMSK       (PA_BCR+0x0000) /* Interrupt Mask control */
+#define PA_IRLMON       (PA_BCR+0x0002) /* Interrupt Status control */
+#define PA_IRLPRI1      (PA_BCR+0x0004) /* Interrupt Priorty 1 */
+#define PA_IRLPRI2      (PA_BCR+0x0006) /* Interrupt Priorty 2 */
+#define PA_IRLPRI3      (PA_BCR+0x0008) /* Interrupt Priorty 3 */
+#define PA_IRLPRI4      (PA_BCR+0x000a) /* Interrupt Priorty 4 */
+#define PA_RSTCTL       (PA_BCR+0x000c) /* Reset Control */
+#define PA_PCIBD        (PA_BCR+0x000e) /* PCI Board detect control */
+#define PA_PCICD        (PA_BCR+0x0010) /* PCI Conector detect control */
+#define PA_EXTGIO       (PA_BCR+0x0016) /* Extension GPIO Control */
+#define PA_IVDRMON      (PA_BCR+0x0018) /* iVDR Moniter control */
+#define PA_IVDRCTL      (PA_BCR+0x001a) /* iVDR control */
+#define PA_OBLED        (PA_BCR+0x001c) /* On Board LED control */
+#define PA_OBSW         (PA_BCR+0x001e) /* On Board Switch control */
+#define PA_AUDIOSEL     (PA_BCR+0x0020) /* Sound Interface Select control */
+#define PA_EXTPLR       (PA_BCR+0x001e) /* Extention Pin Polarity control */
+#define PA_TPCTL        (PA_BCR+0x0100) /* Touch Panel Access control */
+#define PA_TPDCKCTL     (PA_BCR+0x0102) /* Touch Panel Access data control */
+#define PA_TPCTLCLR     (PA_BCR+0x0104) /* Touch Panel Access control */
+#define PA_TPXPOS       (PA_BCR+0x0106) /* Touch Panel X position control */
+#define PA_TPYPOS       (PA_BCR+0x0108) /* Touch Panel Y position control */
+#define PA_DBSW         (PA_BCR+0x0200) /* Debug Board Switch control */
+#define PA_CFCTL        (PA_BCR+0x0300) /* CF Timing control */
+#define PA_CFPOW        (PA_BCR+0x0302) /* CF Power control */
+#define PA_CFCDINTCLR   (PA_BCR+0x0304) /* CF Insert Interrupt clear */
+#define PA_SCSMR0       (PA_BCR+0x0400) /* SCIF0 Serial mode control */
+#define PA_SCBRR0       (PA_BCR+0x0404) /* SCIF0 Bit rate control */
+#define PA_SCSCR0       (PA_BCR+0x0408) /* SCIF0 Serial control */
+#define PA_SCFTDR0      (PA_BCR+0x040c) /* SCIF0 Send FIFO control */
+#define PA_SCFSR0       (PA_BCR+0x0410) /* SCIF0 Serial status control */
+#define PA_SCFRDR0      (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */
+#define PA_SCFCR0       (PA_BCR+0x0418) /* SCIF0 FIFO control */
+#define PA_SCTFDR0      (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */
+#define PA_SCRFDR0      (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */
+#define PA_SCSPTR0      (PA_BCR+0x0424) /* SCIF0 Serial Port control */
+#define PA_SCLSR0       (PA_BCR+0x0428) /* SCIF0 Line Status control */
+#define PA_SCRER0       (PA_BCR+0x042c) /* SCIF0 Serial Error control */
+#define PA_SCSMR1       (PA_BCR+0x0500) /* SCIF1 Serial mode control */
+#define PA_SCBRR1       (PA_BCR+0x0504) /* SCIF1 Bit rate control */
+#define PA_SCSCR1       (PA_BCR+0x0508) /* SCIF1 Serial control */
+#define PA_SCFTDR1      (PA_BCR+0x050c) /* SCIF1 Send FIFO control */
+#define PA_SCFSR1       (PA_BCR+0x0510) /* SCIF1 Serial status control */
+#define PA_SCFRDR1      (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */
+#define PA_SCFCR1       (PA_BCR+0x0518) /* SCIF1 FIFO control */
+#define PA_SCTFDR1      (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */
+#define PA_SCRFDR1      (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */
+#define PA_SCSPTR1      (PA_BCR+0x0524) /* SCIF1 Serial Port control */
+#define PA_SCLSR1       (PA_BCR+0x0528) /* SCIF1 Line Status control */
+#define PA_SCRER1       (PA_BCR+0x052c) /* SCIF1 Serial Error control */
+#define PA_SMCR         (PA_BCR+0x0600) /* 2-wire Serial control */
+#define PA_SMSMADR      (PA_BCR+0x0602) /* 2-wire Serial Slave control */
+#define PA_SMMR         (PA_BCR+0x0604) /* 2-wire Serial Mode control */
+#define PA_SMSADR1      (PA_BCR+0x0606) /* 2-wire Serial Address1 control */
+#define PA_SMTRDR1      (PA_BCR+0x0646) /* 2-wire Serial Data1 control */
+#define PA_VERREG       (PA_BCR+0x0700) /* FPGA Version Register */
+#define PA_POFF         (PA_BCR+0x0800) /* System Power Off control */
+#define PA_PMR          (PA_BCR+0x0900) /*  */
+
+#define IRLCNTR1        (PA_BCR + 0)    /* Interrupt Control Register1 */
+#define IVDR_CK_ON      8               /* iVDR Clock ON */
+
+#elif defined(CONFIG_SH_R7780RP)
+#define PA_POFF         (-1)
+
+#define PA_BCR          0xa5000000      /* FPGA */
+#define PA_IRLMSK       (PA_BCR+0x0000) /* Interrupt Mask control */
+#define PA_IRLMON       (PA_BCR+0x0002) /* Interrupt Status control */
+#define PA_SDPOW        (PA_BCR+0x0004) /* SD Power control */
+#define PA_RSTCTL       (PA_BCR+0x0006) /* Device Reset control */
+#define PA_PCIBD        (PA_BCR+0x0008) /* PCI Board detect control */
+#define PA_PCICD        (PA_BCR+0x000a) /* PCI Conector detect control */
+#define PA_ZIGIO1       (PA_BCR+0x000c) /* Zigbee IO control 1 */
+#define PA_ZIGIO2       (PA_BCR+0x000e) /* Zigbee IO control 2 */
+#define PA_ZIGIO3       (PA_BCR+0x0010) /* Zigbee IO control 3 */
+#define PA_ZIGIO4       (PA_BCR+0x0012) /* Zigbee IO control 4 */
+#define PA_IVDRMON      (PA_BCR+0x0014) /* iVDR Moniter control */
+#define PA_IVDRCTL      (PA_BCR+0x0016) /* iVDR control */
+#define PA_OBLED        (PA_BCR+0x0018) /* On Board LED control */
+#define PA_OBSW         (PA_BCR+0x001a) /* On Board Switch control */
+#define PA_AUDIOSEL     (PA_BCR+0x001c) /* Sound Interface Select control */
+#define PA_EXTPLR       (PA_BCR+0x001e) /* Extention Pin Polarity control */
+#define PA_TPCTL        (PA_BCR+0x0100) /* Touch Panel Access control */
+#define PA_TPDCKCTL     (PA_BCR+0x0102) /* Touch Panel Access data control */
+#define PA_TPCTLCLR     (PA_BCR+0x0104) /* Touch Panel Access control */
+#define PA_TPXPOS       (PA_BCR+0x0106) /* Touch Panel X position control */
+#define PA_TPYPOS       (PA_BCR+0x0108) /* Touch Panel Y position control */
+#define PA_DBDET        (PA_BCR+0x0200) /* Debug Board detect control */
+#define PA_DBDISPCTL    (PA_BCR+0x0202) /* Debug Board Dot timing control */
+#define PA_DBSW         (PA_BCR+0x0204) /* Debug Board Switch control */
+#define PA_CFCTL        (PA_BCR+0x0300) /* CF Timing control */
+#define PA_CFPOW        (PA_BCR+0x0302) /* CF Power control */
+#define PA_CFCDINTCLR   (PA_BCR+0x0304) /* CF Insert Interrupt clear */
+#define PA_SCSMR        (PA_BCR+0x0400) /* SCIF Serial mode control */
+#define PA_SCBRR        (PA_BCR+0x0402) /* SCIF Bit rate control */
+#define PA_SCSCR        (PA_BCR+0x0404) /* SCIF Serial control */
+#define PA_SCFDTR       (PA_BCR+0x0406) /* SCIF Send FIFO control */
+#define PA_SCFSR        (PA_BCR+0x0408) /* SCIF Serial status control */
+#define PA_SCFRDR       (PA_BCR+0x040a) /* SCIF Receive FIFO control */
+#define PA_SCFCR        (PA_BCR+0x040c) /* SCIF FIFO control */
+#define PA_SCFDR        (PA_BCR+0x040e) /* SCIF FIFO data control */
+#define PA_SCLSR        (PA_BCR+0x0412) /* SCIF Line Status control */
+#define PA_SMCR         (PA_BCR+0x0500) /* 2-wire Serial control */
+#define PA_SMSMADR      (PA_BCR+0x0502) /* 2-wire Serial Slave control */
+#define PA_SMMR         (PA_BCR+0x0504) /* 2-wire Serial Mode control */
+#define PA_SMSADR1      (PA_BCR+0x0506) /* 2-wire Serial Address1 control */
+#define PA_SMTRDR1      (PA_BCR+0x0546) /* 2-wire Serial Data1 control */
+#define PA_VERREG       (PA_BCR+0x0600) /* FPGA Version Register */
+
+#define PA_AX88796L     0xa5800400      /* AX88796L Area */
+#define PA_SC1602BSLB   0xa6000000      /* SC1602BSLB Area */
+#define PA_IDE_OFFSET   0x1f0           /* CF IDE Offset */
+#define AX88796L_IO_BASE        0x1000  /* AX88796L IO Base Address */
+
+#define IRLCNTR1        (PA_BCR + 0)    /* Interrupt Control Register1 */
+
+#define IVDR_CK_ON      8               /* iVDR Clock ON */
+
+#elif defined(CONFIG_SH_R7785RP)
+#define PA_BCR          0xa4000000      /* FPGA */
+#define PA_SDPOW        (-1)
+
+#define PA_PCISCR       (PA_BCR+0x0000)
+#define PA_IRLPRA       (PA_BCR+0x0002)
+#define PA_IRLPRB       (PA_BCR+0x0004)
+#define PA_IRLPRC       (PA_BCR+0x0006)
+#define PA_IRLPRD       (PA_BCR+0x0008)
+#define IRLCNTR1        (PA_BCR+0x0010)
+#define PA_IRLPRE       (PA_BCR+0x000a)
+#define PA_IRLPRF       (PA_BCR+0x000c)
+#define PA_EXIRLCR      (PA_BCR+0x000e)
+#define PA_IRLMCR1      (PA_BCR+0x0010)
+#define PA_IRLMCR2      (PA_BCR+0x0012)
+#define PA_IRLSSR1      (PA_BCR+0x0014)
+#define PA_IRLSSR2      (PA_BCR+0x0016)
+#define PA_CFTCR        (PA_BCR+0x0100)
+#define PA_CFPCR        (PA_BCR+0x0102)
+#define PA_PCICR        (PA_BCR+0x0110)
+#define PA_IVDRCTL      (PA_BCR+0x0112)
+#define PA_IVDRSR       (PA_BCR+0x0114)
+#define PA_PDRSTCR      (PA_BCR+0x0116)
+#define PA_POFF         (PA_BCR+0x0120)
+#define PA_LCDCR        (PA_BCR+0x0130)
+#define PA_TPCR         (PA_BCR+0x0140)
+#define PA_TPCKCR       (PA_BCR+0x0142)
+#define PA_TPRSTR       (PA_BCR+0x0144)
+#define PA_TPXPDR       (PA_BCR+0x0146)
+#define PA_TPYPDR       (PA_BCR+0x0148)
+#define PA_GPIOPFR      (PA_BCR+0x0150)
+#define PA_GPIODR       (PA_BCR+0x0152)
+#define PA_OBLED        (PA_BCR+0x0154)
+#define PA_SWSR         (PA_BCR+0x0156)
+#define PA_VERREG       (PA_BCR+0x0158)
+#define PA_SMCR         (PA_BCR+0x0200)
+#define PA_SMSMADR      (PA_BCR+0x0202)
+#define PA_SMMR         (PA_BCR+0x0204)
+#define PA_SMSADR1      (PA_BCR+0x0206)
+#define PA_SMSADR32     (PA_BCR+0x0244)
+#define PA_SMTRDR1      (PA_BCR+0x0246)
+#define PA_SMTRDR16     (PA_BCR+0x0264)
+#define PA_CU3MDR       (PA_BCR+0x0300)
+#define PA_CU5MDR       (PA_BCR+0x0302)
+#define PA_MMSR         (PA_BCR+0x0400)
+
+#define IVDR_CK_ON      4               /* iVDR Clock ON */
+#endif
+
+#define HL_FPGA_IRQ_BASE        200
+#define HL_NR_IRL               15
+
+#define IRQ_AX88796             (HL_FPGA_IRQ_BASE + 0)
+#define IRQ_CF                  (HL_FPGA_IRQ_BASE + 1)
+#define IRQ_PSW                 (HL_FPGA_IRQ_BASE + 2)
+#define IRQ_EXT0                (HL_FPGA_IRQ_BASE + 3)
+#define IRQ_EXT1                (HL_FPGA_IRQ_BASE + 4)
+#define IRQ_EXT2                (HL_FPGA_IRQ_BASE + 5)
+#define IRQ_EXT3                (HL_FPGA_IRQ_BASE + 6)
+#define IRQ_EXT4                (HL_FPGA_IRQ_BASE + 7)
+#define IRQ_EXT5                (HL_FPGA_IRQ_BASE + 8)
+#define IRQ_EXT6                (HL_FPGA_IRQ_BASE + 9)
+#define IRQ_EXT7                (HL_FPGA_IRQ_BASE + 10)
+#define IRQ_SMBUS               (HL_FPGA_IRQ_BASE + 11)
+#define IRQ_TP                  (HL_FPGA_IRQ_BASE + 12)
+#define IRQ_RTC                 (HL_FPGA_IRQ_BASE + 13)
+#define IRQ_TH_ALERT            (HL_FPGA_IRQ_BASE + 14)
+#define IRQ_SCIF0               (HL_FPGA_IRQ_BASE + 15)
+#define IRQ_SCIF1               (HL_FPGA_IRQ_BASE + 16)
+
+unsigned char *highlander_plat_irq_setup(void);
+
+#endif  /* __ASM_SH_RENESAS_R7780RP */
diff --git a/arch/sh/include/asm/resource.h b/arch/sh/include/asm/resource.h
new file mode 100644
index 000000000000..9c2499a86ec0
--- /dev/null
+++ b/arch/sh/include/asm/resource.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SH_RESOURCE_H
+#define __ASM_SH_RESOURCE_H
+
+#include <asm-generic/resource.h>
+
+#endif /* __ASM_SH_RESOURCE_H */
diff --git a/arch/sh/include/asm/rtc.h b/arch/sh/include/asm/rtc.h
new file mode 100644
index 000000000000..1813f4202a24
--- /dev/null
+++ b/arch/sh/include/asm/rtc.h
@@ -0,0 +1,16 @@
+#ifndef _ASM_RTC_H
+#define _ASM_RTC_H
+
+extern void (*board_time_init)(void);
+extern void (*rtc_sh_get_time)(struct timespec *);
+extern int (*rtc_sh_set_time)(const time_t);
+
+#define RTC_CAP_4_DIGIT_YEAR    (1 << 0)
+
+struct sh_rtc_platform_info {
+        unsigned long capabilities;
+};
+
+#include <cpu/rtc.h>
+
+#endif /* _ASM_RTC_H */
diff --git a/arch/sh/include/asm/rts7751r2d.h b/arch/sh/include/asm/rts7751r2d.h
new file mode 100644
index 000000000000..0a800157b826
--- /dev/null
+++ b/arch/sh/include/asm/rts7751r2d.h
@@ -0,0 +1,70 @@
+#ifndef __ASM_SH_RENESAS_RTS7751R2D_H
+#define __ASM_SH_RENESAS_RTS7751R2D_H
+
+/*
+ * linux/include/asm-sh/renesas_rts7751r2d.h
+ *
+ * Copyright (C) 2000  Atom Create Engineering Co., Ltd.
+ *
+ * Renesas Technology Sales RTS7751R2D support
+ */
+
+/* Board specific addresses.  */
+
+#define PA_BCR          0xa4000000      /* FPGA */
+#define PA_IRLMON       0xa4000002      /* Interrupt Status control */
+#define PA_CFCTL        0xa4000004      /* CF Timing control */
+#define PA_CFPOW        0xa4000006      /* CF Power control */
+#define PA_DISPCTL      0xa4000008      /* Display Timing control */
+#define PA_SDMPOW       0xa400000a      /* SD Power control */
+#define PA_RTCCE        0xa400000c      /* RTC(9701) Enable control */
+#define PA_PCICD        0xa400000e      /* PCI Extention detect control */
+#define PA_VOYAGERRTS   0xa4000020      /* VOYAGER Reset control */
+
+#define PA_R2D1_AXRST           0xa4000022      /* AX_LAN Reset control */
+#define PA_R2D1_CFRST           0xa4000024      /* CF Reset control */
+#define PA_R2D1_ADMRTS          0xa4000026      /* SD Reset control */
+#define PA_R2D1_EXTRST          0xa4000028      /* Extention Reset control */
+#define PA_R2D1_CFCDINTCLR      0xa400002a      /* CF Insert Interrupt clear */
+
+#define PA_R2DPLUS_CFRST        0xa4000022      /* CF Reset control */
+#define PA_R2DPLUS_ADMRTS       0xa4000024      /* SD Reset control */
+#define PA_R2DPLUS_EXTRST       0xa4000026      /* Extention Reset control */
+#define PA_R2DPLUS_CFCDINTCLR   0xa4000028      /* CF Insert Interrupt clear */
+#define PA_R2DPLUS_KEYCTLCLR    0xa400002a      /* Key Interrupt clear */
+
+#define PA_POWOFF       0xa4000030      /* Board Power OFF control */
+#define PA_VERREG       0xa4000032      /* FPGA Version Register */
+#define PA_INPORT       0xa4000034      /* KEY Input Port control */
+#define PA_OUTPORT      0xa4000036      /* LED control */
+#define PA_BVERREG      0xa4000038      /* Board Revision Register */
+
+#define PA_AX88796L     0xaa000400      /* AX88796L Area */
+#define PA_VOYAGER      0xab000000      /* VOYAGER GX Area */
+#define PA_IDE_OFFSET   0x1f0           /* CF IDE Offset */
+#define AX88796L_IO_BASE        0x1000  /* AX88796L IO Base Address */
+
+#define IRLCNTR1        (PA_BCR + 0)    /* Interrupt Control Register1 */
+
+#define R2D_FPGA_IRQ_BASE       100
+
+#define IRQ_VOYAGER             (R2D_FPGA_IRQ_BASE + 0)
+#define IRQ_EXT                 (R2D_FPGA_IRQ_BASE + 1)
+#define IRQ_TP                  (R2D_FPGA_IRQ_BASE + 2)
+#define IRQ_RTC_T               (R2D_FPGA_IRQ_BASE + 3)
+#define IRQ_RTC_A               (R2D_FPGA_IRQ_BASE + 4)
+#define IRQ_SDCARD              (R2D_FPGA_IRQ_BASE + 5)
+#define IRQ_CF_CD               (R2D_FPGA_IRQ_BASE + 6)
+#define IRQ_CF_IDE              (R2D_FPGA_IRQ_BASE + 7)
+#define IRQ_AX88796             (R2D_FPGA_IRQ_BASE + 8)
+#define IRQ_KEY                 (R2D_FPGA_IRQ_BASE + 9)
+#define IRQ_PCI_INTA            (R2D_FPGA_IRQ_BASE + 10)
+#define IRQ_PCI_INTB            (R2D_FPGA_IRQ_BASE + 11)
+#define IRQ_PCI_INTC            (R2D_FPGA_IRQ_BASE + 12)
+#define IRQ_PCI_INTD            (R2D_FPGA_IRQ_BASE + 13)
+
+/* arch/sh/boards/renesas/rts7751r2d/irq.c */
+void init_rts7751r2d_IRQ(void);
+int rts7751r2d_irq_demux(int);
+
+#endif  /* __ASM_SH_RENESAS_RTS7751R2D */
diff --git a/arch/sh/include/asm/rwsem.h b/arch/sh/include/asm/rwsem.h
new file mode 100644
index 000000000000..1987f3ea7f1b
--- /dev/null
+++ b/arch/sh/include/asm/rwsem.h
@@ -0,0 +1,188 @@
+/*
+ * include/asm-sh/rwsem.h: R/W semaphores for SH using the stuff
+ * in lib/rwsem.c.
+ */
+
+#ifndef _ASM_SH_RWSEM_H
+#define _ASM_SH_RWSEM_H
+
+#ifndef _LINUX_RWSEM_H
+#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
+#endif
+
+#ifdef __KERNEL__
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <asm/atomic.h>
+#include <asm/system.h>
+
+/*
+ * the semaphore definition
+ */
+struct rw_semaphore {
+        long            count;
+#define RWSEM_UNLOCKED_VALUE            0x00000000
+#define RWSEM_ACTIVE_BIAS               0x00000001
+#define RWSEM_ACTIVE_MASK               0x0000ffff
+#define RWSEM_WAITING_BIAS              (-0x00010000)
+#define RWSEM_ACTIVE_READ_BIAS          RWSEM_ACTIVE_BIAS
+#define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
+        spinlock_t              wait_lock;
+        struct list_head        wait_list;
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+        struct lockdep_map      dep_map;
+#endif
+};
+
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
+#else
+# define __RWSEM_DEP_MAP_INIT(lockname)
+#endif
+
+#define __RWSEM_INITIALIZER(name) \
+        { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
+          LIST_HEAD_INIT((name).wait_list) \
+          __RWSEM_DEP_MAP_INIT(name) }
+
+#define DECLARE_RWSEM(name)             \
+        struct rw_semaphore name = __RWSEM_INITIALIZER(name)
+
+extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
+
+extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
+                         struct lock_class_key *key);
+
+#define init_rwsem(sem)                         \
+do {                                            \
+        static struct lock_class_key __key;     \
+                                                \
+        __init_rwsem((sem), #sem, &__key);      \
+} while (0)
+
+static inline void init_rwsem(struct rw_semaphore *sem)
+{
+        sem->count = RWSEM_UNLOCKED_VALUE;
+        spin_lock_init(&sem->wait_lock);
+        INIT_LIST_HEAD(&sem->wait_list);
+}
+
+/*
+ * lock for reading
+ */
+static inline void __down_read(struct rw_semaphore *sem)
+{
+        if (atomic_inc_return((atomic_t *)(&sem->count)) > 0)
+                smp_wmb();
+        else
+                rwsem_down_read_failed(sem);
+}
+
+static inline int __down_read_trylock(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        while ((tmp = sem->count) >= 0) {
+                if (tmp == cmpxchg(&sem->count, tmp,
+                                   tmp + RWSEM_ACTIVE_READ_BIAS)) {
+                        smp_wmb();
+                        return 1;
+                }
+        }
+        return 0;
+}
+
+/*
+ * lock for writing
+ */
+static inline void __down_write(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS,
+                                (atomic_t *)(&sem->count));
+        if (tmp == RWSEM_ACTIVE_WRITE_BIAS)
+                smp_wmb();
+        else
+                rwsem_down_write_failed(sem);
+}
+
+static inline int __down_write_trylock(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
+                      RWSEM_ACTIVE_WRITE_BIAS);
+        smp_wmb();
+        return tmp == RWSEM_UNLOCKED_VALUE;
+}
+
+/*
+ * unlock after reading
+ */
+static inline void __up_read(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        smp_wmb();
+        tmp = atomic_dec_return((atomic_t *)(&sem->count));
+        if (tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0)
+                rwsem_wake(sem);
+}
+
+/*
+ * unlock after writing
+ */
+static inline void __up_write(struct rw_semaphore *sem)
+{
+        smp_wmb();
+        if (atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
+                              (atomic_t *)(&sem->count)) < 0)
+                rwsem_wake(sem);
+}
+
+/*
+ * implement atomic add functionality
+ */
+static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
+{
+        atomic_add(delta, (atomic_t *)(&sem->count));
+}
+
+/*
+ * downgrade write lock to read lock
+ */
+static inline void __downgrade_write(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        smp_wmb();
+        tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count));
+        if (tmp < 0)
+                rwsem_downgrade_wake(sem);
+}
+
+static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
+{
+        __down_write(sem);
+}
+
+/*
+ * implement exchange and add functionality
+ */
+static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
+{
+        smp_mb();
+        return atomic_add_return(delta, (atomic_t *)(&sem->count));
+}
+
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_SH_RWSEM_H */
diff --git a/arch/sh/include/asm/scatterlist.h b/arch/sh/include/asm/scatterlist.h
new file mode 100644
index 000000000000..2084d0373693
--- /dev/null
+++ b/arch/sh/include/asm/scatterlist.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_SH_SCATTERLIST_H
+#define __ASM_SH_SCATTERLIST_H
+
+#include <asm/types.h>
+
+struct scatterlist {
+#ifdef CONFIG_DEBUG_SG
+    unsigned long sg_magic;
+#endif
+    unsigned long page_link;
+    unsigned int offset;/* for highmem, page offset */
+    dma_addr_t dma_address;
+    unsigned int length;
+};
+
+#define ISA_DMA_THRESHOLD       PHYS_ADDR_MASK
+
+/* These macros should be used after a pci_map_sg call has been done
+ * to get bus addresses of each of the SG entries and their lengths.
+ * You should only work with the number of sg entries pci_map_sg
+ * returns, or alternatively stop on the first sg_dma_len(sg) which
+ * is 0.
+ */
+#define sg_dma_address(sg)      ((sg)->dma_address)
+#define sg_dma_len(sg)          ((sg)->length)
+
+#endif /* !(__ASM_SH_SCATTERLIST_H) */
diff --git a/arch/sh/include/asm/sdk7780.h b/arch/sh/include/asm/sdk7780.h
new file mode 100644
index 000000000000..697dc865f21b
--- /dev/null
+++ b/arch/sh/include/asm/sdk7780.h
@@ -0,0 +1,81 @@
+#ifndef __ASM_SH_RENESAS_SDK7780_H
+#define __ASM_SH_RENESAS_SDK7780_H
+
+/*
+ * linux/include/asm-sh/sdk7780.h
+ *
+ * Renesas Solutions SH7780 SDK Support
+ * Copyright (C) 2008 Nicholas Beck <nbeck@mpc-data.co.uk>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <asm/addrspace.h>
+
+/* Box specific addresses.  */
+#define SE_AREA0_WIDTH  4               /* Area0: 32bit */
+#define PA_ROM                  0xa0000000      /* EPROM */
+#define PA_ROM_SIZE             0x00400000      /* EPROM size 4M byte */
+#define PA_FROM                 0xa0800000      /* Flash-ROM */
+#define PA_FROM_SIZE    0x00400000      /* Flash-ROM size 4M byte */
+#define PA_EXT1                 0xa4000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_SDRAM                0xa8000000      /* DDR-SDRAM(Area2/3) 128MB */
+#define PA_SDRAM_SIZE   0x08000000
+
+#define PA_EXT4                 0xb0000000
+#define PA_EXT4_SIZE    0x04000000
+#define PA_EXT_USER             PA_EXT4         /* User Expansion Space */
+
+#define PA_PERIPHERAL   PA_AREA5_IO
+
+/* SRAM/Reserved */
+#define PA_RESERVED     (PA_PERIPHERAL + 0)
+/* FPGA base address */
+#define PA_FPGA         (PA_PERIPHERAL + 0x01000000)
+/* SMC LAN91C111 */
+#define PA_LAN          (PA_PERIPHERAL + 0x01800000)
+
+
+#define FPGA_SRSTR      (PA_FPGA + 0x000)       /* System reset */
+#define FPGA_IRQ0SR     (PA_FPGA + 0x010)       /* IRQ0 status */
+#define FPGA_IRQ0MR     (PA_FPGA + 0x020)       /* IRQ0 mask */
+#define FPGA_BDMR       (PA_FPGA + 0x030)       /* Board operating mode */
+#define FPGA_INTT0PRTR  (PA_FPGA + 0x040)       /* Interrupt test mode0 port */
+#define FPGA_INTT0SELR  (PA_FPGA + 0x050)       /* Int. test mode0 select */
+#define FPGA_INTT1POLR  (PA_FPGA + 0x060)       /* Int. test mode0 polarity */
+#define FPGA_NMIR       (PA_FPGA + 0x070)       /* NMI source */
+#define FPGA_NMIMR      (PA_FPGA + 0x080)       /* NMI mask */
+#define FPGA_IRQR       (PA_FPGA + 0x090)       /* IRQX source */
+#define FPGA_IRQMR      (PA_FPGA + 0x0A0)       /* IRQX mask */
+#define FPGA_SLEDR      (PA_FPGA + 0x0B0)       /* LED control */
+#define PA_LED                  FPGA_SLEDR
+#define FPGA_MAPSWR     (PA_FPGA + 0x0C0)       /* Map switch */
+#define FPGA_FPVERR     (PA_FPGA + 0x0D0)       /* FPGA version */
+#define FPGA_FPDATER    (PA_FPGA + 0x0E0)       /* FPGA date */
+#define FPGA_RSE        (PA_FPGA + 0x100)       /* Reset source */
+#define FPGA_EASR       (PA_FPGA + 0x110)       /* External area select */
+#define FPGA_SPER       (PA_FPGA + 0x120)       /* Serial port enable */
+#define FPGA_IMSR       (PA_FPGA + 0x130)       /* Interrupt mode select */
+#define FPGA_PCIMR      (PA_FPGA + 0x140)       /* PCI Mode */
+#define FPGA_DIPSWMR    (PA_FPGA + 0x150)       /* DIPSW monitor */
+#define FPGA_FPODR      (PA_FPGA + 0x160)       /* Output port data */
+#define FPGA_ATAESR     (PA_FPGA + 0x170)       /* ATA extended bus status */
+#define FPGA_IRQPOLR    (PA_FPGA + 0x180)       /* IRQx polarity */
+
+
+#define SDK7780_NR_IRL                  15
+/* IDE/ATA interrupt */
+#define IRQ_CFCARD                              14
+/* SMC interrupt */
+#define IRQ_ETHERNET                    6
+
+
+/* arch/sh/boards/renesas/sdk7780/irq.c */
+void init_sdk7780_IRQ(void);
+
+#define __IO_PREFIX             sdk7780
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_RENESAS_SDK7780_H */
diff --git a/arch/sh/include/asm/sections.h b/arch/sh/include/asm/sections.h
new file mode 100644
index 000000000000..8f8f4ad400df
--- /dev/null
+++ b/arch/sh/include/asm/sections.h
@@ -0,0 +1,11 @@
+#ifndef __ASM_SH_SECTIONS_H
+#define __ASM_SH_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+extern long __machvec_start, __machvec_end;
+extern char __uncached_start, __uncached_end;
+extern char _ebss[];
+
+#endif /* __ASM_SH_SECTIONS_H */
+
diff --git a/arch/sh/include/asm/segment.h b/arch/sh/include/asm/segment.h
new file mode 100644
index 000000000000..5e2725f4ac49
--- /dev/null
+++ b/arch/sh/include/asm/segment.h
@@ -0,0 +1,34 @@
+#ifndef __ASM_SH_SEGMENT_H
+#define __ASM_SH_SEGMENT_H
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+        unsigned long seg;
+} mm_segment_t;
+
+#define MAKE_MM_SEG(s)  ((mm_segment_t) { (s) })
+
+/*
+ * The fs value determines whether argument validity checking should be
+ * performed or not.  If get_fs() == USER_DS, checking is performed, with
+ * get_fs() == KERNEL_DS, checking is bypassed.
+ *
+ * For historical reasons, these macros are grossly misnamed.
+ */
+#define KERNEL_DS       MAKE_MM_SEG(0xFFFFFFFFUL)
+#ifdef CONFIG_MMU
+#define USER_DS         MAKE_MM_SEG(PAGE_OFFSET)
+#else
+#define USER_DS         KERNEL_DS
+#endif
+
+#define segment_eq(a,b) ((a).seg == (b).seg)
+
+#define get_ds()        (KERNEL_DS)
+
+#define get_fs()        (current_thread_info()->addr_limit)
+#define set_fs(x)       (current_thread_info()->addr_limit = (x))
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_SH_SEGMENT_H */
diff --git a/arch/sh/include/asm/sembuf.h b/arch/sh/include/asm/sembuf.h
new file mode 100644
index 000000000000..d79f3bd570b2
--- /dev/null
+++ b/arch/sh/include/asm/sembuf.h
@@ -0,0 +1,25 @@
+#ifndef __ASM_SH_SEMBUF_H
+#define __ASM_SH_SEMBUF_H
+
+/* 
+ * The semid64_ds structure for i386 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct semid64_ds {
+        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
+        __kernel_time_t sem_otime;              /* last semop time */
+        unsigned long   __unused1;
+        __kernel_time_t sem_ctime;              /* last change time */
+        unsigned long   __unused2;
+        unsigned long   sem_nsems;              /* no. of semaphores in array */
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* __ASM_SH_SEMBUF_H */
diff --git a/arch/sh/include/asm/serial.h b/arch/sh/include/asm/serial.h
new file mode 100644
index 000000000000..e13cc948ee60
--- /dev/null
+++ b/arch/sh/include/asm/serial.h
@@ -0,0 +1,36 @@
+/*
+ * include/asm-sh/serial.h
+ *
+ * Configuration details for 8250, 16450, 16550, etc. serial ports
+ */
+
+#ifndef _ASM_SERIAL_H
+#define _ASM_SERIAL_H
+
+#include <linux/kernel.h>
+
+/*
+ * This assumes you have a 1.8432 MHz clock for your UART.
+ *
+ * It'd be nice if someone built a serial card with a 24.576 MHz
+ * clock, since the 16550A is capable of handling a top speed of 1.5
+ * megabits/second; but this requires the faster clock.
+ */
+#define BASE_BAUD ( 1843200 / 16 )
+
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+
+#ifdef CONFIG_HD64465
+#include <asm/hd64465/hd64465.h>
+
+#define SERIAL_PORT_DFNS                   \
+        /* UART CLK   PORT IRQ     FLAGS        */                      \
+        { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS }  /* ttyS0 */
+
+#else
+
+#define SERIAL_PORT_DFNS
+
+#endif
+
+#endif /* _ASM_SERIAL_H */
diff --git a/arch/sh/include/asm/setup.h b/arch/sh/include/asm/setup.h
new file mode 100644
index 000000000000..55a2bd328d99
--- /dev/null
+++ b/arch/sh/include/asm/setup.h
@@ -0,0 +1,27 @@
+#ifndef _SH_SETUP_H
+#define _SH_SETUP_H
+
+#define COMMAND_LINE_SIZE 256
+
+#ifdef __KERNEL__
+
+/*
+ * This is set up by the setup-routine at boot-time
+ */
+#define PARAM   ((unsigned char *)empty_zero_page)
+
+#define MOUNT_ROOT_RDONLY (*(unsigned long *) (PARAM+0x000))
+#define RAMDISK_FLAGS (*(unsigned long *) (PARAM+0x004))
+#define ORIG_ROOT_DEV (*(unsigned long *) (PARAM+0x008))
+#define LOADER_TYPE (*(unsigned long *) (PARAM+0x00c))
+#define INITRD_START (*(unsigned long *) (PARAM+0x010))
+#define INITRD_SIZE (*(unsigned long *) (PARAM+0x014))
+/* ... */
+#define COMMAND_LINE ((char *) (PARAM+0x100))
+
+int setup_early_printk(char *);
+void sh_mv_setup(void);
+
+#endif /* __KERNEL__ */
+
+#endif /* _SH_SETUP_H */
diff --git a/arch/sh/include/asm/sfp-machine.h b/arch/sh/include/asm/sfp-machine.h
new file mode 100644
index 000000000000..d3c548443f2a
--- /dev/null
+++ b/arch/sh/include/asm/sfp-machine.h
@@ -0,0 +1,84 @@
+/* Machine-dependent software floating-point definitions.
+   SuperH kernel version.
+   Copyright (C) 1997,1998,1999 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Richard Henderson (rth@cygnus.com),
+                  Jakub Jelinek (jj@ultra.linux.cz),
+                  David S. Miller (davem@redhat.com) and
+                  Peter Maydell (pmaydell@chiark.greenend.org.uk).
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Library General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Library General Public License for more details.
+
+   You should have received a copy of the GNU Library General Public
+   License along with the GNU C Library; see the file COPYING.LIB.  If
+   not, write to the Free Software Foundation, Inc.,
+   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef _SFP_MACHINE_H
+#define _SFP_MACHINE_H
+
+#define _FP_W_TYPE_SIZE         32
+#define _FP_W_TYPE              unsigned long
+#define _FP_WS_TYPE             signed long
+#define _FP_I_TYPE              long
+
+#define _FP_MUL_MEAT_S(R,X,Y)                                   \
+  _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_D(R,X,Y)                                   \
+  _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_Q(R,X,Y)                                   \
+  _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
+
+#define _FP_DIV_MEAT_S(R,X,Y)   _FP_DIV_MEAT_1_udiv(S,R,X,Y)
+#define _FP_DIV_MEAT_D(R,X,Y)   _FP_DIV_MEAT_2_udiv(D,R,X,Y)
+#define _FP_DIV_MEAT_Q(R,X,Y)   _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
+
+#define _FP_NANFRAC_S           ((_FP_QNANBIT_S << 1) - 1)
+#define _FP_NANFRAC_D           ((_FP_QNANBIT_D << 1) - 1), -1
+#define _FP_NANFRAC_Q           ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
+#define _FP_NANSIGN_S           0
+#define _FP_NANSIGN_D           0
+#define _FP_NANSIGN_Q           0
+
+#define _FP_KEEPNANFRACP 1
+
+/*
+ * If one NaN is signaling and the other is not,
+ * we choose that one, otherwise we choose X.
+ */
+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP)                      \
+  do {                                                          \
+    if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs)          \
+        && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs))     \
+      {                                                         \
+        R##_s = Y##_s;                                          \
+        _FP_FRAC_COPY_##wc(R,Y);                                \
+      }                                                         \
+    else                                                        \
+      {                                                         \
+        R##_s = X##_s;                                          \
+        _FP_FRAC_COPY_##wc(R,X);                                \
+      }                                                         \
+    R##_c = FP_CLS_NAN;                                         \
+  } while (0)
+
+//#define FP_ROUNDMODE          FPSCR_RM
+#define FP_DENORM_ZERO          1/*FPSCR_DN*/
+
+/* Exception flags. */
+#define FP_EX_INVALID           (1<<4)
+#define FP_EX_DIVZERO           (1<<3)
+#define FP_EX_OVERFLOW          (1<<2)
+#define FP_EX_UNDERFLOW         (1<<1)
+#define FP_EX_INEXACT           (1<<0)
+
+#endif
+
diff --git a/arch/sh/include/asm/sh7760fb.h b/arch/sh/include/asm/sh7760fb.h
new file mode 100644
index 000000000000..8767f61aceca
--- /dev/null
+++ b/arch/sh/include/asm/sh7760fb.h
@@ -0,0 +1,197 @@
+/*
+ * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
+ *
+ * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
+ *                      Manuel Lauss <mano@roarinelk.homelinux.net>
+ * (c) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ */
+
+#ifndef _ASM_SH_SH7760FB_H
+#define _ASM_SH_SH7760FB_H
+
+/*
+ * some bits of the colormap registers should be written as zero.
+ * create a mask for that.
+ */
+#define SH7760FB_PALETTE_MASK 0x00f8fcf8
+
+/* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
+#define SH7760FB_DMA_MASK 0x0C000000
+
+/* palette */
+#define LDPR(x) (((x) << 2))
+
+/* framebuffer registers and bits */
+#define LDICKR 0x400
+#define LDMTR 0x402
+/* see sh7760fb.h for LDMTR bits */
+#define LDDFR 0x404
+#define LDDFR_PABD (1 << 8)
+#define LDDFR_COLOR_MASK 0x7F
+#define LDSMR 0x406
+#define LDSMR_ROT (1 << 13)
+#define LDSARU 0x408
+#define LDSARL 0x40c
+#define LDLAOR 0x410
+#define LDPALCR 0x412
+#define LDPALCR_PALS (1 << 4)
+#define LDPALCR_PALEN (1 << 0)
+#define LDHCNR 0x414
+#define LDHSYNR 0x416
+#define LDVDLNR 0x418
+#define LDVTLNR 0x41a
+#define LDVSYNR 0x41c
+#define LDACLNR 0x41e
+#define LDINTR 0x420
+#define LDPMMR 0x424
+#define LDPSPR 0x426
+#define LDCNTR 0x428
+#define LDCNTR_DON (1 << 0)
+#define LDCNTR_DON2 (1 << 4)
+
+#ifdef CONFIG_CPU_SUBTYPE_SH7763
+# define LDLIRNR       0x440
+/* LDINTR bit */
+# define LDINTR_MINTEN (1 << 15)
+# define LDINTR_FINTEN (1 << 14)
+# define LDINTR_VSINTEN (1 << 13)
+# define LDINTR_VEINTEN (1 << 12)
+# define LDINTR_MINTS (1 << 11)
+# define LDINTR_FINTS (1 << 10)
+# define LDINTR_VSINTS (1 << 9)
+# define LDINTR_VEINTS (1 << 8)
+# define VINT_START (LDINTR_VSINTEN)
+# define VINT_CHECK (LDINTR_VSINTS)
+#else
+/* LDINTR bit */
+# define LDINTR_VINTSEL (1 << 12)
+# define LDINTR_VINTE (1 << 8)
+# define LDINTR_VINTS (1 << 0)
+# define VINT_START (LDINTR_VINTSEL)
+# define VINT_CHECK (LDINTR_VINTS)
+#endif
+
+/* HSYNC polarity inversion */
+#define LDMTR_FLMPOL (1 << 15)
+
+/* VSYNC polarity inversion */
+#define LDMTR_CL1POL (1 << 14)
+
+/* DISPLAY-ENABLE polarity inversion */
+#define LDMTR_DISPEN_LOWACT (1 << 13)
+
+/* DISPLAY DATA BUS polarity inversion */
+#define LDMTR_DPOL_LOWACT (1 << 12)
+
+/* AC modulation signal enable */
+#define LDMTR_MCNT (1 << 10)
+
+/* Disable output of HSYNC during VSYNC period */
+#define LDMTR_CL1CNT (1 << 9)
+
+/* Disable output of VSYNC during VSYNC period */
+#define LDMTR_CL2CNT (1 << 8)
+
+/* Display types supported by the LCDC */
+#define LDMTR_STN_MONO_4       0x00
+#define LDMTR_STN_MONO_8       0x01
+#define LDMTR_STN_COLOR_4      0x08
+#define LDMTR_STN_COLOR_8      0x09
+#define LDMTR_STN_COLOR_12     0x0A
+#define LDMTR_STN_COLOR_16     0x0B
+#define LDMTR_DSTN_MONO_8      0x11
+#define LDMTR_DSTN_MONO_16     0x13
+#define LDMTR_DSTN_COLOR_8     0x19
+#define LDMTR_DSTN_COLOR_12    0x1A
+#define LDMTR_DSTN_COLOR_16    0x1B
+#define LDMTR_TFT_COLOR_16     0x2B
+
+/* framebuffer color layout */
+#define LDDFR_1BPP_MONO 0x00
+#define LDDFR_2BPP_MONO 0x01
+#define LDDFR_4BPP_MONO 0x02
+#define LDDFR_6BPP_MONO 0x04
+#define LDDFR_4BPP 0x0A
+#define LDDFR_8BPP 0x0C
+#define LDDFR_16BPP_RGB555 0x1D
+#define LDDFR_16BPP_RGB565 0x2D
+
+/* LCDC Pixclock sources */
+#define LCDC_CLKSRC_BUSCLOCK 0
+#define LCDC_CLKSRC_PERIPHERAL 1
+#define LCDC_CLKSRC_EXTERNAL 2
+
+#define LDICKR_CLKSRC(x) \
+       (((x) & 3) << 12)
+
+/* LCDC pixclock input divider. Set to 1 at a minimum! */
+#define LDICKR_CLKDIV(x) \
+       ((x) & 0x1f)
+
+struct sh7760fb_platdata {
+
+        /* Set this member to a valid fb_videmode for the display you
+         * wish to use.  The following members must be initialized:
+         * xres, yres, hsync_len, vsync_len, sync,
+         * {left,right,upper,lower}_margin.
+         * The driver uses the above members to calculate register values
+         * and memory requirements. Other members are ignored but may
+         * be used by other framebuffer layer components.
+         */
+        struct fb_videomode *def_mode;
+
+        /* LDMTR includes display type and signal polarity.  The
+         * HSYNC/VSYNC polarities are derived from the fb_var_screeninfo
+         * data above; however the polarities of the following signals
+         * must be encoded in the ldmtr member:
+         * Display Enable signal (default high-active)  DISPEN_LOWACT
+         * Display Data signals (default high-active)   DPOL_LOWACT
+         * AC Modulation signal (default off)           MCNT
+         * Hsync-During-Vsync suppression (default off) CL1CNT
+         * Vsync-during-vsync suppression (default off) CL2CNT
+         * NOTE: also set a display type!
+         * (one of LDMTR_{STN,DSTN,TFT}_{MONO,COLOR}_{4,8,12,16})
+         */
+        u16 ldmtr;
+
+        /* LDDFR controls framebuffer image format (depth, organization)
+         * Use ONE of the LDDFR_?BPP_* macros!
+         */
+        u16 lddfr;
+
+        /* LDPMMR and LDPSPR control the timing of the power signals
+         * for the display. Please read the SH7760 Hardware Manual,
+         * Chapters 30.3.17, 30.3.18 and 30.4.6!
+         */
+        u16 ldpmmr;
+        u16 ldpspr;
+
+        /* LDACLNR contains the line numbers after which the AC modulation
+         * signal is to toggle. Set to ZERO for TFTs or displays which
+         * do not need it. (Chapter 30.3.15 in SH7760 Hardware Manual).
+         */
+        u16 ldaclnr;
+
+        /* LDICKR contains information on pixelclock source and config.
+         * Please use the LDICKR_CLKSRC() and LDICKR_CLKDIV() macros.
+         * minimal value for CLKDIV() must be 1!.
+         */
+        u16 ldickr;
+
+        /* set this member to 1 if you wish to use the LCDC's hardware
+         * rotation function.  This is limited to displays <= 320x200
+         * pixels resolution!
+         */
+        int rotate;             /* set to 1 to rotate 90 CCW */
+
+        /* set this to 1 to suppress vsync irq use. */
+        int novsync;
+
+        /* blanking hook for platform. Set this if your platform can do
+         * more than the LCDC in terms of blanking (e.g. disable clock
+         * generator / backlight power supply / etc.
+         */
+        void (*blank) (int);
+};
+
+#endif /* _ASM_SH_SH7760FB_H */
diff --git a/arch/sh/include/asm/sh7763rdp.h b/arch/sh/include/asm/sh7763rdp.h
new file mode 100644
index 000000000000..8750cc852977
--- /dev/null
+++ b/arch/sh/include/asm/sh7763rdp.h
@@ -0,0 +1,54 @@
+#ifndef __ASM_SH_SH7763RDP_H
+#define __ASM_SH_SH7763RDP_H
+
+/*
+ * linux/include/asm-sh/sh7763drp.h
+ *
+ * Copyright (C) 2008 Renesas Solutions
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <asm/addrspace.h>
+
+/* clock control */
+#define MSTPCR1 0xFFC80038
+
+/* PORT */
+#define PORT_PSEL0      0xFFEF0070
+#define PORT_PSEL1      0xFFEF0072
+#define PORT_PSEL2      0xFFEF0074
+#define PORT_PSEL3      0xFFEF0076
+#define PORT_PSEL4      0xFFEF0078
+
+#define PORT_PACR       0xFFEF0000
+#define PORT_PCCR       0xFFEF0004
+#define PORT_PFCR       0xFFEF000A
+#define PORT_PGCR       0xFFEF000C
+#define PORT_PHCR       0xFFEF000E
+#define PORT_PICR       0xFFEF0010
+#define PORT_PJCR       0xFFEF0012
+#define PORT_PKCR       0xFFEF0014
+#define PORT_PLCR       0xFFEF0016
+#define PORT_PMCR       0xFFEF0018
+#define PORT_PNCR       0xFFEF001A
+
+/* FPGA */
+#define CPLD_BOARD_ID_ERV_REG   0xB1000000
+#define CPLD_CPLD_CMD_REG               0xB1000006
+
+/*
+ * USB SH7763RDP board can use Host only.
+ */
+#define USB_USBHSC      0xFFEC80f0
+
+/* arch/sh/boards/renesas/sh7763rdp/irq.c */
+void init_sh7763rdp_IRQ(void);
+int sh7763rdp_irq_demux(int irq);
+#define __IO_PREFIX     sh7763rdp
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_SH7763RDP_H */
diff --git a/arch/sh/include/asm/sh7785lcr.h b/arch/sh/include/asm/sh7785lcr.h
new file mode 100644
index 000000000000..1ce27d5c7491
--- /dev/null
+++ b/arch/sh/include/asm/sh7785lcr.h
@@ -0,0 +1,55 @@
+#ifndef __ASM_SH_RENESAS_SH7785LCR_H
+#define __ASM_SH_RENESAS_SH7785LCR_H
+
+/*
+ * This board has 2 physical memory maps.
+ * It can be changed with DIP switch(S2-5).
+ *
+ * phys address                 | S2-5 = OFF    | S2-5 = ON
+ * -----------------------------+---------------+---------------
+ * 0x00000000 - 0x03ffffff(CS0) | NOR Flash     | NOR Flash
+ * 0x04000000 - 0x05ffffff(CS1) | PLD           | PLD
+ * 0x06000000 - 0x07ffffff(CS1) | reserved      | I2C
+ * 0x08000000 - 0x0bffffff(CS2) | USB           | DDR SDRAM
+ * 0x0c000000 - 0x0fffffff(CS3) | SD            | DDR SDRAM
+ * 0x10000000 - 0x13ffffff(CS4) | SM107         | SM107
+ * 0x14000000 - 0x17ffffff(CS5) | I2C           | USB
+ * 0x18000000 - 0x1bffffff(CS6) | reserved      | SD
+ * 0x40000000 - 0x5fffffff      | DDR SDRAM     | (cannot use)
+ *
+ */
+
+#define NOR_FLASH_ADDR          0x00000000
+#define NOR_FLASH_SIZE          0x04000000
+
+#define PLD_BASE_ADDR           0x04000000
+#define PLD_PCICR               (PLD_BASE_ADDR + 0x00)
+#define PLD_LCD_BK_CONTR        (PLD_BASE_ADDR + 0x02)
+#define PLD_LOCALCR             (PLD_BASE_ADDR + 0x04)
+#define PLD_POFCR               (PLD_BASE_ADDR + 0x06)
+#define PLD_LEDCR               (PLD_BASE_ADDR + 0x08)
+#define PLD_SWSR                (PLD_BASE_ADDR + 0x0a)
+#define PLD_VERSR               (PLD_BASE_ADDR + 0x0c)
+#define PLD_MMSR                (PLD_BASE_ADDR + 0x0e)
+
+#define SM107_MEM_ADDR          0x10000000
+#define SM107_MEM_SIZE          0x00e00000
+#define SM107_REG_ADDR          0x13e00000
+#define SM107_REG_SIZE          0x00200000
+
+#if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS)
+#define R8A66597_ADDR           0x14000000      /* USB */
+#define CG200_ADDR              0x18000000      /* SD */
+#define PCA9564_ADDR            0x06000000      /* I2C */
+#else
+#define R8A66597_ADDR           0x08000000
+#define CG200_ADDR              0x0c000000
+#define PCA9564_ADDR            0x14000000
+#endif
+
+#define R8A66597_SIZE           0x00000100
+#define CG200_SIZE              0x00010000
+#define PCA9564_SIZE            0x00000100
+
+#endif  /* __ASM_SH_RENESAS_SH7785LCR_H */
+
diff --git a/arch/sh/include/asm/sh_bios.h b/arch/sh/include/asm/sh_bios.h
new file mode 100644
index 000000000000..0ca261956e3d
--- /dev/null
+++ b/arch/sh/include/asm/sh_bios.h
@@ -0,0 +1,19 @@
+#ifndef __ASM_SH_BIOS_H
+#define __ASM_SH_BIOS_H
+
+/*
+ * Copyright (C) 2000 Greg Banks, Mitch Davis
+ * C API to interface to the standard LinuxSH BIOS
+ * usually from within the early stages of kernel boot.
+ */
+
+
+extern void sh_bios_console_write(const char *buf, unsigned int len);
+extern void sh_bios_char_out(char ch);
+extern int sh_bios_in_gdb_mode(void);
+extern void sh_bios_gdb_detach(void);
+
+extern void sh_bios_get_node_addr(unsigned char *node_addr);
+extern void sh_bios_shutdown(unsigned int how);
+
+#endif /* __ASM_SH_BIOS_H */
diff --git a/arch/sh/include/asm/sh_keysc.h b/arch/sh/include/asm/sh_keysc.h
new file mode 100644
index 000000000000..b5a4dd5a9729
--- /dev/null
+++ b/arch/sh/include/asm/sh_keysc.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_KEYSC_H__
+#define __ASM_KEYSC_H__
+
+#define SH_KEYSC_MAXKEYS 30
+
+struct sh_keysc_info {
+        enum { SH_KEYSC_MODE_1, SH_KEYSC_MODE_2, SH_KEYSC_MODE_3 } mode;
+        int scan_timing; /* 0 -> 7, see KYCR1, SCN[2:0] */
+        int delay;
+        int keycodes[SH_KEYSC_MAXKEYS];
+};
+
+#endif /* __ASM_KEYSC_H__ */
diff --git a/arch/sh/include/asm/sh_mobile_lcdc.h b/arch/sh/include/asm/sh_mobile_lcdc.h
new file mode 100644
index 000000000000..27677727df4d
--- /dev/null
+++ b/arch/sh/include/asm/sh_mobile_lcdc.h
@@ -0,0 +1,66 @@
+#ifndef __ASM_SH_MOBILE_LCDC_H__
+#define __ASM_SH_MOBILE_LCDC_H__
+
+#include <linux/fb.h>
+
+enum { RGB8,   /* 24bpp, 8:8:8 */
+       RGB9,   /* 18bpp, 9:9 */
+       RGB12A, /* 24bpp, 12:12 */
+       RGB12B, /* 12bpp */
+       RGB16,  /* 16bpp */
+       RGB18,  /* 18bpp */
+       RGB24,  /* 24bpp */
+       SYS8A,  /* 24bpp, 8:8:8 */
+       SYS8B,  /* 18bpp, 8:8:2 */
+       SYS8C,  /* 18bpp, 2:8:8 */
+       SYS8D,  /* 16bpp, 8:8 */
+       SYS9,   /* 18bpp, 9:9 */
+       SYS12,  /* 24bpp, 12:12 */
+       SYS16A, /* 16bpp */
+       SYS16B, /* 18bpp, 16:2 */
+       SYS16C, /* 18bpp, 2:16 */
+       SYS18,  /* 18bpp */
+       SYS24 };/* 24bpp */
+
+enum { LCDC_CHAN_DISABLED = 0,
+       LCDC_CHAN_MAINLCD,
+       LCDC_CHAN_SUBLCD };
+
+enum { LCDC_CLK_BUS, LCDC_CLK_PERIPHERAL, LCDC_CLK_EXTERNAL };
+
+struct sh_mobile_lcdc_sys_bus_cfg {
+        unsigned long ldmt2r;
+        unsigned long ldmt3r;
+};
+
+struct sh_mobile_lcdc_sys_bus_ops {
+        void (*write_index)(void *handle, unsigned long data);
+        void (*write_data)(void *handle, unsigned long data);
+        unsigned long (*read_data)(void *handle);
+};
+
+struct sh_mobile_lcdc_board_cfg {
+        void *board_data;
+        int (*setup_sys)(void *board_data, void *sys_ops_handle,
+                         struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
+        void (*display_on)(void *board_data);
+        void (*display_off)(void *board_data);
+};
+
+struct sh_mobile_lcdc_chan_cfg {
+        int chan;
+        int bpp;
+        int interface_type; /* selects RGBn or SYSn I/F, see above */
+        int clock_divider;
+        struct fb_videomode lcd_cfg;
+        struct sh_mobile_lcdc_board_cfg board_cfg;
+        struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */
+};
+
+struct sh_mobile_lcdc_info {
+        unsigned long lddckr;
+        int clock_source;
+        struct sh_mobile_lcdc_chan_cfg ch[2];
+};
+
+#endif /* __ASM_SH_MOBILE_LCDC_H__ */
diff --git a/arch/sh/include/asm/shmbuf.h b/arch/sh/include/asm/shmbuf.h
new file mode 100644
index 000000000000..b2101f490521
--- /dev/null
+++ b/arch/sh/include/asm/shmbuf.h
@@ -0,0 +1,42 @@
+#ifndef __ASM_SH_SHMBUF_H
+#define __ASM_SH_SHMBUF_H
+
+/* 
+ * The shmid64_ds structure for i386 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct shmid64_ds {
+        struct ipc64_perm       shm_perm;       /* operation perms */
+        size_t                  shm_segsz;      /* size of segment (bytes) */
+        __kernel_time_t         shm_atime;      /* last attach time */
+        unsigned long           __unused1;
+        __kernel_time_t         shm_dtime;      /* last detach time */
+        unsigned long           __unused2;
+        __kernel_time_t         shm_ctime;      /* last change time */
+        unsigned long           __unused3;
+        __kernel_pid_t          shm_cpid;       /* pid of creator */
+        __kernel_pid_t          shm_lpid;       /* pid of last operator */
+        unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned long           __unused4;
+        unsigned long           __unused5;
+};
+
+struct shminfo64 {
+        unsigned long   shmmax;
+        unsigned long   shmmin;
+        unsigned long   shmmni;
+        unsigned long   shmseg;
+        unsigned long   shmall;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* __ASM_SH_SHMBUF_H */
diff --git a/arch/sh/include/asm/shmin.h b/arch/sh/include/asm/shmin.h
new file mode 100644
index 000000000000..36ba138a81fb
--- /dev/null
+++ b/arch/sh/include/asm/shmin.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_SH_SHMIN_H
+#define __ASM_SH_SHMIN_H
+
+#define SHMIN_IO_BASE 0xb0000000UL
+
+#define SHMIN_NE_IRQ IRQ2_IRQ
+#define SHMIN_NE_BASE 0x300
+
+#endif
diff --git a/arch/sh/include/asm/shmparam.h b/arch/sh/include/asm/shmparam.h
new file mode 100644
index 000000000000..ba1758d90106
--- /dev/null
+++ b/arch/sh/include/asm/shmparam.h
@@ -0,0 +1,22 @@
+/*
+ * include/asm-sh/shmparam.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2006 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_SHMPARAM_H
+#define __ASM_SH_SHMPARAM_H
+
+/*
+ * SH-4 and SH-3 7705 have an aliasing dcache. Bump this up to a sensible value
+ * for everyone, and work out the specifics from the probed cache descriptor.
+ */
+#define SHMLBA  0x4000           /* attach addr a multiple of this */
+
+#define __ARCH_FORCE_SHMLBA
+
+#endif /* __ASM_SH_SHMPARAM_H */
diff --git a/arch/sh/include/asm/sigcontext.h b/arch/sh/include/asm/sigcontext.h
new file mode 100644
index 000000000000..8ce1435bc0bf
--- /dev/null
+++ b/arch/sh/include/asm/sigcontext.h
@@ -0,0 +1,40 @@
+#ifndef __ASM_SH_SIGCONTEXT_H
+#define __ASM_SH_SIGCONTEXT_H
+
+struct sigcontext {
+        unsigned long   oldmask;
+
+#if defined(__SH5__) || defined(CONFIG_CPU_SH5)
+        /* CPU registers */
+        unsigned long long sc_regs[63];
+        unsigned long long sc_tregs[8];
+        unsigned long long sc_pc;
+        unsigned long long sc_sr;
+
+        /* FPU registers */
+        unsigned long long sc_fpregs[32];
+        unsigned int sc_fpscr;
+        unsigned int sc_fpvalid;
+#else
+        /* CPU registers */
+        unsigned long sc_regs[16];
+        unsigned long sc_pc;
+        unsigned long sc_pr;
+        unsigned long sc_sr;
+        unsigned long sc_gbr;
+        unsigned long sc_mach;
+        unsigned long sc_macl;
+
+#if defined(__SH4__) || defined(CONFIG_CPU_SH4) || \
+    defined(__SH2A__) || defined(CONFIG_CPU_SH2A)
+        /* FPU registers */
+        unsigned long sc_fpregs[16];
+        unsigned long sc_xfpregs[16];
+        unsigned int sc_fpscr;
+        unsigned int sc_fpul;
+        unsigned int sc_ownedfp;
+#endif
+#endif
+};
+
+#endif /* __ASM_SH_SIGCONTEXT_H */
diff --git a/arch/sh/include/asm/siginfo.h b/arch/sh/include/asm/siginfo.h
new file mode 100644
index 000000000000..813040ed68a9
--- /dev/null
+++ b/arch/sh/include/asm/siginfo.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SH_SIGINFO_H
+#define __ASM_SH_SIGINFO_H
+
+#include <asm-generic/siginfo.h>
+
+#endif /* __ASM_SH_SIGINFO_H */
diff --git a/arch/sh/include/asm/signal.h b/arch/sh/include/asm/signal.h
new file mode 100644
index 000000000000..5c5c1e852089
--- /dev/null
+++ b/arch/sh/include/asm/signal.h
@@ -0,0 +1,160 @@
+#ifndef __ASM_SH_SIGNAL_H
+#define __ASM_SH_SIGNAL_H
+
+#include <linux/types.h>
+
+/* Avoid too many header ordering problems.  */
+struct pt_regs;
+struct siginfo;
+
+#ifdef __KERNEL__
+/* Most things should be clean enough to redefine this at will, if care
+   is taken to make libc match.  */
+
+#define _NSIG           64
+#define _NSIG_BPW       32
+#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
+
+typedef unsigned long old_sigset_t;             /* at least 32 bits */
+
+typedef struct {
+        unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+#else
+/* Here we must cater to libcs that poke about in kernel headers.  */
+
+#define NSIG            32
+typedef unsigned long sigset_t;
+
+#endif /* __KERNEL__ */
+
+#define SIGHUP           1
+#define SIGINT           2
+#define SIGQUIT          3
+#define SIGILL           4
+#define SIGTRAP          5
+#define SIGABRT          6
+#define SIGIOT           6
+#define SIGBUS           7
+#define SIGFPE           8
+#define SIGKILL          9
+#define SIGUSR1         10
+#define SIGSEGV         11
+#define SIGUSR2         12
+#define SIGPIPE         13
+#define SIGALRM         14
+#define SIGTERM         15
+#define SIGSTKFLT       16
+#define SIGCHLD         17
+#define SIGCONT         18
+#define SIGSTOP         19
+#define SIGTSTP         20
+#define SIGTTIN         21
+#define SIGTTOU         22
+#define SIGURG          23
+#define SIGXCPU         24
+#define SIGXFSZ         25
+#define SIGVTALRM       26
+#define SIGPROF         27
+#define SIGWINCH        28
+#define SIGIO           29
+#define SIGPOLL         SIGIO
+/*
+#define SIGLOST         29
+*/
+#define SIGPWR          30
+#define SIGSYS          31
+#define SIGUNUSED       31
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN        32
+#define SIGRTMAX        _NSIG
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK indicates that a registered stack_t will be used.
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP    0x00000001
+#define SA_NOCLDWAIT    0x00000002
+#define SA_SIGINFO      0x00000004
+#define SA_ONSTACK      0x08000000
+#define SA_RESTART      0x10000000
+#define SA_NODEFER      0x40000000
+#define SA_RESETHAND    0x80000000
+
+#define SA_NOMASK       SA_NODEFER
+#define SA_ONESHOT      SA_RESETHAND
+
+#define SA_RESTORER     0x04000000
+
+/* 
+ * sigaltstack controls
+ */
+#define SS_ONSTACK      1
+#define SS_DISABLE      2
+
+#define MINSIGSTKSZ     2048
+#define SIGSTKSZ        8192
+
+#include <asm-generic/signal.h>
+
+#ifdef __KERNEL__
+struct old_sigaction {
+        __sighandler_t sa_handler;
+        old_sigset_t sa_mask;
+        unsigned long sa_flags;
+        void (*sa_restorer)(void);
+};
+
+struct sigaction {
+        __sighandler_t sa_handler;
+        unsigned long sa_flags;
+        void (*sa_restorer)(void);
+        sigset_t sa_mask;               /* mask last for extensibility */
+};
+
+struct k_sigaction {
+        struct sigaction sa;
+};
+#else
+/* Here we must cater to libcs that poke about in kernel headers.  */
+
+struct sigaction {
+        union {
+          __sighandler_t _sa_handler;
+          void (*_sa_sigaction)(int, struct siginfo *, void *);
+        } _u;
+        sigset_t sa_mask;
+        unsigned long sa_flags;
+        void (*sa_restorer)(void);
+};
+
+#define sa_handler      _u._sa_handler
+#define sa_sigaction    _u._sa_sigaction
+
+#endif /* __KERNEL__ */
+
+typedef struct sigaltstack {
+        void *ss_sp;
+        int ss_flags;
+        size_t ss_size;
+} stack_t;
+
+#ifdef __KERNEL__
+#include <asm/sigcontext.h>
+
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_SIGNAL_H */
diff --git a/arch/sh/include/asm/smc37c93x.h b/arch/sh/include/asm/smc37c93x.h
new file mode 100644
index 000000000000..585da2a8fc45
--- /dev/null
+++ b/arch/sh/include/asm/smc37c93x.h
@@ -0,0 +1,190 @@
+#ifndef __ASM_SH_SMC37C93X_H
+#define __ASM_SH_SMC37C93X_H
+
+/*
+ * linux/include/asm-sh/smc37c93x.h
+ *
+ * Copyright (C) 2000  Kazumoto Kojima
+ *
+ * SMSC 37C93x Super IO Chip support
+ */
+
+/* Default base I/O address */
+#define FDC_PRIMARY_BASE        0x3f0
+#define IDE1_PRIMARY_BASE       0x1f0
+#define IDE1_SECONDARY_BASE     0x170
+#define PARPORT_PRIMARY_BASE    0x378
+#define COM1_PRIMARY_BASE       0x2f8
+#define COM2_PRIMARY_BASE       0x3f8
+#define RTC_PRIMARY_BASE        0x070
+#define KBC_PRIMARY_BASE        0x060
+#define AUXIO_PRIMARY_BASE      0x000   /* XXX */
+
+/* Logical device number */
+#define LDN_FDC                 0
+#define LDN_IDE1                1
+#define LDN_IDE2                2
+#define LDN_PARPORT             3
+#define LDN_COM1                4
+#define LDN_COM2                5
+#define LDN_RTC                 6
+#define LDN_KBC                 7
+#define LDN_AUXIO               8
+
+/* Configuration port and key */
+#define CONFIG_PORT             0x3f0
+#define INDEX_PORT              CONFIG_PORT
+#define DATA_PORT               0x3f1
+#define CONFIG_ENTER            0x55
+#define CONFIG_EXIT             0xaa
+
+/* Configuration index */
+#define CURRENT_LDN_INDEX       0x07
+#define POWER_CONTROL_INDEX     0x22
+#define ACTIVATE_INDEX          0x30
+#define IO_BASE_HI_INDEX        0x60
+#define IO_BASE_LO_INDEX        0x61
+#define IRQ_SELECT_INDEX        0x70
+#define DMA_SELECT_INDEX        0x74
+
+#define GPIO46_INDEX            0xc6
+#define GPIO47_INDEX            0xc7
+
+/* UART stuff. Only for debugging.  */
+/* UART Register */
+
+#define UART_RBR        0x0     /* Receiver Buffer Register (Read Only) */
+#define UART_THR        0x0     /* Transmitter Holding Register (Write Only) */
+#define UART_IER        0x2     /* Interrupt Enable Register */
+#define UART_IIR        0x4     /* Interrupt Ident Register (Read Only) */
+#define UART_FCR        0x4     /* FIFO Control Register (Write Only) */
+#define UART_LCR        0x6     /* Line Control Register */
+#define UART_MCR        0x8     /* MODEM Control Register */
+#define UART_LSR        0xa     /* Line Status Register */
+#define UART_MSR        0xc     /* MODEM Status Register */
+#define UART_SCR        0xe     /* Scratch Register */
+#define UART_DLL        0x0     /* Divisor Latch (LS) */
+#define UART_DLM        0x2     /* Divisor Latch (MS) */
+
+#ifndef __ASSEMBLY__
+typedef struct uart_reg {
+        volatile __u16 rbr;
+        volatile __u16 ier;
+        volatile __u16 iir;
+        volatile __u16 lcr;
+        volatile __u16 mcr;
+        volatile __u16 lsr;
+        volatile __u16 msr;
+        volatile __u16 scr;
+} uart_reg;
+#endif /* ! __ASSEMBLY__ */
+
+/* Alias for Write Only Register */
+
+#define thr     rbr
+#define tcr     iir
+
+/* Alias for Divisor Latch Register */
+
+#define dll     rbr
+#define dlm     ier
+#define fcr     iir
+
+/* Interrupt Enable Register */
+
+#define IER_ERDAI       0x0100  /* Enable Received Data Available Interrupt */
+#define IER_ETHREI      0x0200  /* Enable Transmitter Holding Register Empty Interrupt */
+#define IER_ELSI        0x0400  /* Enable Receiver Line Status Interrupt */
+#define IER_EMSI        0x0800  /* Enable MODEM Status Interrupt */
+
+/* Interrupt Ident Register */
+
+#define IIR_IP          0x0100  /* "0" if Interrupt Pending */
+#define IIR_IIB0        0x0200  /* Interrupt ID Bit 0 */
+#define IIR_IIB1        0x0400  /* Interrupt ID Bit 1 */
+#define IIR_IIB2        0x0800  /* Interrupt ID Bit 2 */
+#define IIR_FIFO        0xc000  /* FIFOs enabled */
+
+/* FIFO Control Register */
+
+#define FCR_FEN         0x0100  /* FIFO enable */
+#define FCR_RFRES       0x0200  /* Receiver FIFO reset */
+#define FCR_TFRES       0x0400  /* Transmitter FIFO reset */
+#define FCR_DMA         0x0800  /* DMA mode select */
+#define FCR_RTL         0x4000  /* Receiver triger (LSB) */
+#define FCR_RTM         0x8000  /* Receiver triger (MSB) */
+
+/* Line Control Register */
+
+#define LCR_WLS0        0x0100  /* Word Length Select Bit 0 */
+#define LCR_WLS1        0x0200  /* Word Length Select Bit 1 */
+#define LCR_STB         0x0400  /* Number of Stop Bits */
+#define LCR_PEN         0x0800  /* Parity Enable */
+#define LCR_EPS         0x1000  /* Even Parity Select */
+#define LCR_SP          0x2000  /* Stick Parity */
+#define LCR_SB          0x4000  /* Set Break */
+#define LCR_DLAB        0x8000  /* Divisor Latch Access Bit */
+
+/* MODEM Control Register */
+
+#define MCR_DTR         0x0100  /* Data Terminal Ready */
+#define MCR_RTS         0x0200  /* Request to Send */
+#define MCR_OUT1        0x0400  /* Out 1 */
+#define MCR_IRQEN       0x0800  /* IRQ Enable */
+#define MCR_LOOP        0x1000  /* Loop */
+
+/* Line Status Register */
+
+#define LSR_DR          0x0100  /* Data Ready */
+#define LSR_OE          0x0200  /* Overrun Error */
+#define LSR_PE          0x0400  /* Parity Error */
+#define LSR_FE          0x0800  /* Framing Error */
+#define LSR_BI          0x1000  /* Break Interrupt */
+#define LSR_THRE        0x2000  /* Transmitter Holding Register Empty */
+#define LSR_TEMT        0x4000  /* Transmitter Empty */
+#define LSR_FIFOE       0x8000  /* Receiver FIFO error */
+
+/* MODEM Status Register */
+
+#define MSR_DCTS        0x0100  /* Delta Clear to Send */
+#define MSR_DDSR        0x0200  /* Delta Data Set Ready */
+#define MSR_TERI        0x0400  /* Trailing Edge Ring Indicator */
+#define MSR_DDCD        0x0800  /* Delta Data Carrier Detect */
+#define MSR_CTS         0x1000  /* Clear to Send */
+#define MSR_DSR         0x2000  /* Data Set Ready */
+#define MSR_RI          0x4000  /* Ring Indicator */
+#define MSR_DCD         0x8000  /* Data Carrier Detect */
+
+/* Baud Rate Divisor */
+
+#define UART_CLK        (1843200)       /* 1.8432 MHz */
+#define UART_BAUD(x)    (UART_CLK / (16 * (x)))
+
+/* RTC register definition */
+#define RTC_SECONDS             0
+#define RTC_SECONDS_ALARM       1
+#define RTC_MINUTES             2
+#define RTC_MINUTES_ALARM       3
+#define RTC_HOURS               4
+#define RTC_HOURS_ALARM         5
+#define RTC_DAY_OF_WEEK         6
+#define RTC_DAY_OF_MONTH        7
+#define RTC_MONTH               8
+#define RTC_YEAR                9
+#define RTC_FREQ_SELECT         10
+# define RTC_UIP 0x80
+# define RTC_DIV_CTL 0x70
+/* This RTC can work under 32.768KHz clock only.  */
+# define RTC_OSC_ENABLE 0x20
+# define RTC_OSC_DISABLE 0x00
+#define RTC_CONTROL             11
+# define RTC_SET 0x80
+# define RTC_PIE 0x40
+# define RTC_AIE 0x20
+# define RTC_UIE 0x10
+# define RTC_SQWE 0x08
+# define RTC_DM_BINARY 0x04
+# define RTC_24H 0x02
+# define RTC_DST_EN 0x01
+
+#endif  /* __ASM_SH_SMC37C93X_H */
diff --git a/arch/sh/include/asm/smp.h b/arch/sh/include/asm/smp.h
new file mode 100644
index 000000000000..593343cd26ee
--- /dev/null
+++ b/arch/sh/include/asm/smp.h
@@ -0,0 +1,50 @@
+#ifndef __ASM_SH_SMP_H
+#define __ASM_SH_SMP_H
+
+#include <linux/bitops.h>
+#include <linux/cpumask.h>
+
+#ifdef CONFIG_SMP
+
+#include <linux/spinlock.h>
+#include <asm/atomic.h>
+#include <asm/current.h>
+
+#define raw_smp_processor_id()  (current_thread_info()->cpu)
+#define hard_smp_processor_id() plat_smp_processor_id()
+
+/* Map from cpu id to sequential logical cpu number. */
+extern int __cpu_number_map[NR_CPUS];
+#define cpu_number_map(cpu)  __cpu_number_map[cpu]
+
+/* The reverse map from sequential logical cpu number to cpu id.  */
+extern int __cpu_logical_map[NR_CPUS];
+#define cpu_logical_map(cpu)  __cpu_logical_map[cpu]
+
+/* I've no idea what the real meaning of this is */
+#define PROC_CHANGE_PENALTY     20
+
+#define NO_PROC_ID      (-1)
+
+#define SMP_MSG_FUNCTION        0
+#define SMP_MSG_RESCHEDULE      1
+#define SMP_MSG_FUNCTION_SINGLE 2
+#define SMP_MSG_NR              3
+
+void plat_smp_setup(void);
+void plat_prepare_cpus(unsigned int max_cpus);
+int plat_smp_processor_id(void);
+void plat_start_cpu(unsigned int cpu, unsigned long entry_point);
+void plat_send_ipi(unsigned int cpu, unsigned int message);
+int plat_register_ipi_handler(unsigned int message,
+                              void (*handler)(void *), void *arg);
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi(cpumask_t mask);
+
+#else
+
+#define hard_smp_processor_id() (0)
+
+#endif /* CONFIG_SMP */
+
+#endif /* __ASM_SH_SMP_H */
diff --git a/arch/sh/include/asm/snapgear.h b/arch/sh/include/asm/snapgear.h
new file mode 100644
index 000000000000..042d95f51c4d
--- /dev/null
+++ b/arch/sh/include/asm/snapgear.h
@@ -0,0 +1,71 @@
+/*
+ * include/asm-sh/snapgear.h
+ *
+ * Modified version of io_se.h for the snapgear-specific functions.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * IO functions for a SnapGear
+ */
+
+#ifndef _ASM_SH_IO_SNAPGEAR_H
+#define _ASM_SH_IO_SNAPGEAR_H
+
+#if defined(CONFIG_CPU_SH4)
+/*
+ * The external interrupt lines, these take up ints 0 - 15 inclusive
+ * depending on the priority for the interrupt.  In fact the priority
+ * is the interrupt :-)
+ */
+
+#define IRL0_IRQ        2
+#define IRL0_PRIORITY   13
+
+#define IRL1_IRQ        5
+#define IRL1_PRIORITY   10
+
+#define IRL2_IRQ        8
+#define IRL2_PRIORITY   7
+
+#define IRL3_IRQ        11
+#define IRL3_PRIORITY   4
+#endif
+
+#define __IO_PREFIX     snapgear
+#include <asm/io_generic.h>
+
+#ifdef CONFIG_SH_SECUREEDGE5410
+/*
+ * We need to remember what was written to the ioport as some bits
+ * are shared with other functions and you cannot read back what was
+ * written :-|
+ *
+ * Bit        Read                   Write
+ * -----------------------------------------------
+ * D0         DCD on ttySC1          power
+ * D1         Reset Switch           heatbeat
+ * D2         ttySC0 CTS (7100)      LAN
+ * D3         -                      WAN
+ * D4         ttySC0 DCD (7100)      CONSOLE
+ * D5         -                      ONLINE
+ * D6         -                      VPN
+ * D7         -                      DTR on ttySC1
+ * D8         -                      ttySC0 RTS (7100)
+ * D9         -                      ttySC0 DTR (7100)
+ * D10        -                      RTC SCLK
+ * D11        RTC DATA               RTC DATA
+ * D12        -                      RTS RESET
+ */
+
+#define SECUREEDGE_IOPORT_ADDR ((volatile short *) 0xb0000000)
+extern unsigned short secureedge5410_ioport;
+
+#define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \
+         (secureedge5410_ioport = \
+                        ((secureedge5410_ioport & ~(mask)) | ((val) & (mask)))))
+#define SECUREEDGE_READ_IOPORT() \
+         ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817))
+#endif
+
+#endif /* _ASM_SH_IO_SNAPGEAR_H */
diff --git a/arch/sh/include/asm/socket.h b/arch/sh/include/asm/socket.h
new file mode 100644
index 000000000000..6d4bf6512959
--- /dev/null
+++ b/arch/sh/include/asm/socket.h
@@ -0,0 +1,57 @@
+#ifndef __ASM_SH_SOCKET_H
+#define __ASM_SH_SOCKET_H
+
+#include <asm/sockios.h>
+
+/* For setsockopt(2) */
+#define SOL_SOCKET      1
+
+#define SO_DEBUG        1
+#define SO_REUSEADDR    2
+#define SO_TYPE         3
+#define SO_ERROR        4
+#define SO_DONTROUTE    5
+#define SO_BROADCAST    6
+#define SO_SNDBUF       7
+#define SO_RCVBUF       8
+#define SO_RCVBUFFORCE  32
+#define SO_SNDBUFFORCE  33
+#define SO_KEEPALIVE    9
+#define SO_OOBINLINE    10
+#define SO_NO_CHECK     11
+#define SO_PRIORITY     12
+#define SO_LINGER       13
+#define SO_BSDCOMPAT    14
+/* To add :#define SO_REUSEPORT 15 */
+#define SO_PASSCRED     16
+#define SO_PEERCRED     17
+#define SO_RCVLOWAT     18
+#define SO_SNDLOWAT     19
+#define SO_RCVTIMEO     20
+#define SO_SNDTIMEO     21
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION              22
+#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
+#define SO_SECURITY_ENCRYPTION_NETWORK          24
+
+#define SO_BINDTODEVICE 25
+
+/* Socket filtering */
+#define SO_ATTACH_FILTER        26
+#define SO_DETACH_FILTER        27
+
+#define SO_PEERNAME             28
+#define SO_TIMESTAMP            29
+#define SCM_TIMESTAMP           SO_TIMESTAMP
+
+#define SO_ACCEPTCONN           30
+
+#define SO_PEERSEC              31
+#define SO_PASSSEC              34
+#define SO_TIMESTAMPNS          35
+#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
+
+#define SO_MARK                 36
+
+#endif /* __ASM_SH_SOCKET_H */
diff --git a/arch/sh/include/asm/sockios.h b/arch/sh/include/asm/sockios.h
new file mode 100644
index 000000000000..cf8b96b1f9ab
--- /dev/null
+++ b/arch/sh/include/asm/sockios.h
@@ -0,0 +1,14 @@
+#ifndef __ASM_SH_SOCKIOS_H
+#define __ASM_SH_SOCKIOS_H
+
+/* Socket-level I/O control calls. */
+#define FIOGETOWN       _IOR('f', 123, int)
+#define FIOSETOWN       _IOW('f', 124, int)
+
+#define SIOCATMARK      _IOR('s', 7, int)
+#define SIOCSPGRP       _IOW('s', 8, pid_t)
+#define SIOCGPGRP       _IOR('s', 9, pid_t)
+
+#define SIOCGSTAMP      _IOR('s', 100, struct timeval) /* Get stamp (timeval) */
+#define SIOCGSTAMPNS    _IOR('s', 101, struct timespec) /* Get stamp (timespec) */
+#endif /* __ASM_SH_SOCKIOS_H */
diff --git a/arch/sh/include/asm/sparsemem.h b/arch/sh/include/asm/sparsemem.h
new file mode 100644
index 000000000000..547a540b6667
--- /dev/null
+++ b/arch/sh/include/asm/sparsemem.h
@@ -0,0 +1,16 @@
+#ifndef __ASM_SH_SPARSEMEM_H
+#define __ASM_SH_SPARSEMEM_H
+
+#ifdef __KERNEL__
+/*
+ * SECTION_SIZE_BITS            2^N: how big each section will be
+ * MAX_PHYSADDR_BITS            2^N: how much physical address space we have
+ * MAX_PHYSMEM_BITS             2^N: how much memory we can have in that space
+ */
+#define SECTION_SIZE_BITS       26
+#define MAX_PHYSADDR_BITS       32
+#define MAX_PHYSMEM_BITS        32
+
+#endif
+
+#endif /* __ASM_SH_SPARSEMEM_H */
diff --git a/arch/sh/include/asm/spi.h b/arch/sh/include/asm/spi.h
new file mode 100644
index 000000000000..e96f5b0953c8
--- /dev/null
+++ b/arch/sh/include/asm/spi.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_SPI_H__
+#define __ASM_SPI_H__
+
+struct sh_spi_info;
+
+struct sh_spi_info {
+        int                      bus_num;
+        int                      num_chipselect;
+
+        void (*chip_select)(struct sh_spi_info *spi, int cs, int state);
+};
+
+#endif /* __ASM_SPI_H__ */
diff --git a/arch/sh/include/asm/spinlock.h b/arch/sh/include/asm/spinlock.h
new file mode 100644
index 000000000000..e793181d64da
--- /dev/null
+++ b/arch/sh/include/asm/spinlock.h
@@ -0,0 +1,223 @@
+/*
+ * include/asm-sh/spinlock.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ * Copyright (C) 2006, 2007 Akio Idehara
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_SPINLOCK_H
+#define __ASM_SH_SPINLOCK_H
+
+/*
+ * The only locking implemented here uses SH-4A opcodes. For others,
+ * split this out as per atomic-*.h.
+ */
+#ifndef CONFIG_CPU_SH4A
+#error "Need movli.l/movco.l for spinlocks"
+#endif
+
+/*
+ * Your basic SMP spinlocks, allowing only a single CPU anywhere
+ */
+
+#define __raw_spin_is_locked(x)         ((x)->lock <= 0)
+#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
+#define __raw_spin_unlock_wait(x) \
+        do { cpu_relax(); } while ((x)->lock)
+
+/*
+ * Simple spin lock operations.  There are two variants, one clears IRQ's
+ * on the local processor, one does not.
+ *
+ * We make no fairness assumptions.  They have a cost.
+ */
+static inline void __raw_spin_lock(raw_spinlock_t *lock)
+{
+        unsigned long tmp;
+        unsigned long oldval;
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%2, %0 ! __raw_spin_lock       \n\t"
+                "mov            %0, %1                          \n\t"
+                "mov            #0, %0                          \n\t"
+                "movco.l        %0, @%2                         \n\t"
+                "bf             1b                              \n\t"
+                "cmp/pl         %1                              \n\t"
+                "bf             1b                              \n\t"
+                : "=&z" (tmp), "=&r" (oldval)
+                : "r" (&lock->lock)
+                : "t", "memory"
+        );
+}
+
+static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+                "mov            #1, %0 ! __raw_spin_unlock      \n\t"
+                "mov.l          %0, @%1                         \n\t"
+                : "=&z" (tmp)
+                : "r" (&lock->lock)
+                : "t", "memory"
+        );
+}
+
+static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+{
+        unsigned long tmp, oldval;
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%2, %0 ! __raw_spin_trylock    \n\t"
+                "mov            %0, %1                          \n\t"
+                "mov            #0, %0                          \n\t"
+                "movco.l        %0, @%2                         \n\t"
+                "bf             1b                              \n\t"
+                "synco                                          \n\t"
+                : "=&z" (tmp), "=&r" (oldval)
+                : "r" (&lock->lock)
+                : "t", "memory"
+        );
+
+        return oldval;
+}
+
+/*
+ * Read-write spinlocks, allowing multiple readers but only one writer.
+ *
+ * NOTE! it is quite common to have readers in interrupts but no interrupt
+ * writers. For those circumstances we can "mix" irq-safe locks - any writer
+ * needs to get a irq-safe write-lock, but readers can get non-irqsafe
+ * read-locks.
+ */
+
+/**
+ * read_can_lock - would read_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define __raw_read_can_lock(x)  ((x)->lock > 0)
+
+/**
+ * write_can_lock - would write_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define __raw_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)
+
+static inline void __raw_read_lock(raw_rwlock_t *rw)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%1, %0 ! __raw_read_lock       \n\t"
+                "cmp/pl         %0                              \n\t"
+                "bf             1b                              \n\t"
+                "add            #-1, %0                         \n\t"
+                "movco.l        %0, @%1                         \n\t"
+                "bf             1b                              \n\t"
+                : "=&z" (tmp)
+                : "r" (&rw->lock)
+                : "t", "memory"
+        );
+}
+
+static inline void __raw_read_unlock(raw_rwlock_t *rw)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%1, %0 ! __raw_read_unlock     \n\t"
+                "add            #1, %0                          \n\t"
+                "movco.l        %0, @%1                         \n\t"
+                "bf             1b                              \n\t"
+                : "=&z" (tmp)
+                : "r" (&rw->lock)
+                : "t", "memory"
+        );
+}
+
+static inline void __raw_write_lock(raw_rwlock_t *rw)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%1, %0 ! __raw_write_lock      \n\t"
+                "cmp/hs         %2, %0                          \n\t"
+                "bf             1b                              \n\t"
+                "sub            %2, %0                          \n\t"
+                "movco.l        %0, @%1                         \n\t"
+                "bf             1b                              \n\t"
+                : "=&z" (tmp)
+                : "r" (&rw->lock), "r" (RW_LOCK_BIAS)
+                : "t", "memory"
+        );
+}
+
+static inline void __raw_write_unlock(raw_rwlock_t *rw)
+{
+        __asm__ __volatile__ (
+                "mov.l          %1, @%0 ! __raw_write_unlock    \n\t"
+                :
+                : "r" (&rw->lock), "r" (RW_LOCK_BIAS)
+                : "t", "memory"
+        );
+}
+
+static inline int __raw_read_trylock(raw_rwlock_t *rw)
+{
+        unsigned long tmp, oldval;
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%2, %0 ! __raw_read_trylock    \n\t"
+                "mov            %0, %1                          \n\t"
+                "cmp/pl         %0                              \n\t"
+                "bf             2f                              \n\t"
+                "add            #-1, %0                         \n\t"
+                "movco.l        %0, @%2                         \n\t"
+                "bf             1b                              \n\t"
+                "2:                                             \n\t"
+                "synco                                          \n\t"
+                : "=&z" (tmp), "=&r" (oldval)
+                : "r" (&rw->lock)
+                : "t", "memory"
+        );
+
+        return (oldval > 0);
+}
+
+static inline int __raw_write_trylock(raw_rwlock_t *rw)
+{
+        unsigned long tmp, oldval;
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%2, %0 ! __raw_write_trylock   \n\t"
+                "mov            %0, %1                          \n\t"
+                "cmp/hs         %3, %0                          \n\t"
+                "bf             2f                              \n\t"
+                "sub            %3, %0                          \n\t"
+                "2:                                             \n\t"
+                "movco.l        %0, @%2                         \n\t"
+                "bf             1b                              \n\t"
+                "synco                                          \n\t"
+                : "=&z" (tmp), "=&r" (oldval)
+                : "r" (&rw->lock), "r" (RW_LOCK_BIAS)
+                : "t", "memory"
+        );
+
+        return (oldval > (RW_LOCK_BIAS - 1));
+}
+
+#define _raw_spin_relax(lock)   cpu_relax()
+#define _raw_read_relax(lock)   cpu_relax()
+#define _raw_write_relax(lock)  cpu_relax()
+
+#endif /* __ASM_SH_SPINLOCK_H */
diff --git a/arch/sh/include/asm/spinlock_types.h b/arch/sh/include/asm/spinlock_types.h
new file mode 100644
index 000000000000..b4d244e7b60c
--- /dev/null
+++ b/arch/sh/include/asm/spinlock_types.h
@@ -0,0 +1,21 @@
+#ifndef __ASM_SH_SPINLOCK_TYPES_H
+#define __ASM_SH_SPINLOCK_TYPES_H
+
+#ifndef __LINUX_SPINLOCK_TYPES_H
+# error "please don't include this file directly"
+#endif
+
+typedef struct {
+        volatile unsigned int lock;
+} raw_spinlock_t;
+
+#define __RAW_SPIN_LOCK_UNLOCKED                { 1 }
+
+typedef struct {
+        volatile unsigned int lock;
+} raw_rwlock_t;
+
+#define RW_LOCK_BIAS                    0x01000000
+#define __RAW_RW_LOCK_UNLOCKED          { RW_LOCK_BIAS }
+
+#endif
diff --git a/arch/sh/include/asm/stat.h b/arch/sh/include/asm/stat.h
new file mode 100644
index 000000000000..e1810cc6e3da
--- /dev/null
+++ b/arch/sh/include/asm/stat.h
@@ -0,0 +1,138 @@
+#ifndef __ASM_SH_STAT_H
+#define __ASM_SH_STAT_H
+
+struct __old_kernel_stat {
+        unsigned short st_dev;
+        unsigned short st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned short st_rdev;
+        unsigned long  st_size;
+        unsigned long  st_atime;
+        unsigned long  st_mtime;
+        unsigned long  st_ctime;
+};
+
+#if defined(__SH5__) || defined(CONFIG_CPU_SH5)
+struct stat {
+        unsigned short st_dev;
+        unsigned short __pad1;
+        unsigned long st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned short st_rdev;
+        unsigned short __pad2;
+        unsigned long  st_size;
+        unsigned long  st_blksize;
+        unsigned long  st_blocks;
+        unsigned long  st_atime;
+        unsigned long  st_atime_nsec;
+        unsigned long  st_mtime;
+        unsigned long  st_mtime_nsec;
+        unsigned long  st_ctime;
+        unsigned long  st_ctime_nsec;
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+/* This matches struct stat64 in glibc2.1, hence the absolutely
+ * insane amounts of padding around dev_t's.
+ */
+struct stat64 {
+        unsigned short  st_dev;
+        unsigned char   __pad0[10];
+
+        unsigned long   st_ino;
+        unsigned int    st_mode;
+        unsigned int    st_nlink;
+
+        unsigned long   st_uid;
+        unsigned long   st_gid;
+
+        unsigned short  st_rdev;
+        unsigned char   __pad3[10];
+
+        long long       st_size;
+        unsigned long   st_blksize;
+
+        unsigned long   st_blocks;      /* Number 512-byte blocks allocated. */
+        unsigned long   __pad4;         /* future possible st_blocks high bits */
+
+        unsigned long   st_atime;
+        unsigned long   st_atime_nsec;
+
+        unsigned long   st_mtime;
+        unsigned long   st_mtime_nsec;
+
+        unsigned long   st_ctime;
+        unsigned long   st_ctime_nsec;  /* will be high 32 bits of ctime someday */
+
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+};
+#else
+struct stat {
+        unsigned long  st_dev;
+        unsigned long  st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned long  st_rdev;
+        unsigned long  st_size;
+        unsigned long  st_blksize;
+        unsigned long  st_blocks;
+        unsigned long  st_atime;
+        unsigned long  st_atime_nsec;
+        unsigned long  st_mtime;
+        unsigned long  st_mtime_nsec;
+        unsigned long  st_ctime;
+        unsigned long  st_ctime_nsec;
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+/* This matches struct stat64 in glibc2.1, hence the absolutely
+ * insane amounts of padding around dev_t's.
+ */
+struct stat64 {
+        unsigned long long      st_dev;
+        unsigned char   __pad0[4];
+
+#define STAT64_HAS_BROKEN_ST_INO        1
+        unsigned long   __st_ino;
+
+        unsigned int    st_mode;
+        unsigned int    st_nlink;
+
+        unsigned long   st_uid;
+        unsigned long   st_gid;
+
+        unsigned long long      st_rdev;
+        unsigned char   __pad3[4];
+
+        long long       st_size;
+        unsigned long   st_blksize;
+
+        unsigned long long      st_blocks;      /* Number 512-byte blocks allocated. */
+
+        unsigned long   st_atime;
+        unsigned long   st_atime_nsec;
+
+        unsigned long   st_mtime;
+        unsigned long   st_mtime_nsec;
+
+        unsigned long   st_ctime;
+        unsigned long   st_ctime_nsec;
+
+        unsigned long long      st_ino;
+};
+
+#define STAT_HAVE_NSEC 1
+#endif
+
+#endif /* __ASM_SH_STAT_H */
diff --git a/arch/sh/include/asm/statfs.h b/arch/sh/include/asm/statfs.h
new file mode 100644
index 000000000000..9202a023328f
--- /dev/null
+++ b/arch/sh/include/asm/statfs.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SH_STATFS_H
+#define __ASM_SH_STATFS_H
+
+#include <asm-generic/statfs.h>
+
+#endif /* __ASM_SH_STATFS_H */
diff --git a/arch/sh/include/asm/string.h b/arch/sh/include/asm/string.h
new file mode 100644
index 000000000000..8c1ea21dc0ae
--- /dev/null
+++ b/arch/sh/include/asm/string.h
@@ -0,0 +1,5 @@
+#ifdef CONFIG_SUPERH32
+# include "string_32.h"
+#else
+# include "string_64.h"
+#endif
diff --git a/arch/sh/include/asm/string_32.h b/arch/sh/include/asm/string_32.h
new file mode 100644
index 000000000000..55f8db6bc1d7
--- /dev/null
+++ b/arch/sh/include/asm/string_32.h
@@ -0,0 +1,131 @@
+#ifndef __ASM_SH_STRING_H
+#define __ASM_SH_STRING_H
+
+#ifdef __KERNEL__
+
+/*
+ * Copyright (C) 1999 Niibe Yutaka
+ * But consider these trivial functions to be public domain.
+ */
+
+#define __HAVE_ARCH_STRCPY
+static inline char *strcpy(char *__dest, const char *__src)
+{
+        register char *__xdest = __dest;
+        unsigned long __dummy;
+
+        __asm__ __volatile__("1:\n\t"
+                             "mov.b     @%1+, %2\n\t"
+                             "mov.b     %2, @%0\n\t"
+                             "cmp/eq    #0, %2\n\t"
+                             "bf/s      1b\n\t"
+                             " add      #1, %0\n\t"
+                             : "=r" (__dest), "=r" (__src), "=&z" (__dummy)
+                             : "0" (__dest), "1" (__src)
+                             : "memory", "t");
+
+        return __xdest;
+}
+
+#define __HAVE_ARCH_STRNCPY
+static inline char *strncpy(char *__dest, const char *__src, size_t __n)
+{
+        register char *__xdest = __dest;
+        unsigned long __dummy;
+
+        if (__n == 0)
+                return __xdest;
+
+        __asm__ __volatile__(
+                "1:\n"
+                "mov.b  @%1+, %2\n\t"
+                "mov.b  %2, @%0\n\t"
+                "cmp/eq #0, %2\n\t"
+                "bt/s   2f\n\t"
+                " cmp/eq        %5,%1\n\t"
+                "bf/s   1b\n\t"
+                " add   #1, %0\n"
+                "2:"
+                : "=r" (__dest), "=r" (__src), "=&z" (__dummy)
+                : "0" (__dest), "1" (__src), "r" (__src+__n)
+                : "memory", "t");
+
+        return __xdest;
+}
+
+#define __HAVE_ARCH_STRCMP
+static inline int strcmp(const char *__cs, const char *__ct)
+{
+        register int __res;
+        unsigned long __dummy;
+
+        __asm__ __volatile__(
+                "mov.b  @%1+, %3\n"
+                "1:\n\t"
+                "mov.b  @%0+, %2\n\t"
+                "cmp/eq #0, %3\n\t"
+                "bt     2f\n\t"
+                "cmp/eq %2, %3\n\t"
+                "bt/s   1b\n\t"
+                " mov.b @%1+, %3\n\t"
+                "add    #-2, %1\n\t"
+                "mov.b  @%1, %3\n\t"
+                "sub    %3, %2\n"
+                "2:"
+                : "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
+                : "0" (__cs), "1" (__ct)
+                : "t");
+
+        return __res;
+}
+
+#define __HAVE_ARCH_STRNCMP
+static inline int strncmp(const char *__cs, const char *__ct, size_t __n)
+{
+        register int __res;
+        unsigned long __dummy;
+
+        if (__n == 0)
+                return 0;
+
+        __asm__ __volatile__(
+                "mov.b  @%1+, %3\n"
+                "1:\n\t"
+                "mov.b  @%0+, %2\n\t"
+                "cmp/eq %6, %0\n\t"
+                "bt/s   2f\n\t"
+                " cmp/eq #0, %3\n\t"
+                "bt/s   3f\n\t"
+                " cmp/eq %3, %2\n\t"
+                "bt/s   1b\n\t"
+                " mov.b @%1+, %3\n\t"
+                "add    #-2, %1\n\t"
+                "mov.b  @%1, %3\n"
+                "2:\n\t"
+                "sub    %3, %2\n"
+                "3:"
+                :"=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
+                : "0" (__cs), "1" (__ct), "r" (__cs+__n)
+                : "t");
+
+        return __res;
+}
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *__s, int __c, size_t __count);
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
+
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
+
+#define __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *__s, int __c, size_t __n);
+
+#define __HAVE_ARCH_STRLEN
+extern size_t strlen(const char *);
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_STRING_H */
diff --git a/arch/sh/include/asm/string_64.h b/arch/sh/include/asm/string_64.h
new file mode 100644
index 000000000000..aa1fef229c78
--- /dev/null
+++ b/arch/sh/include/asm/string_64.h
@@ -0,0 +1,17 @@
+#ifndef __ASM_SH_STRING_64_H
+#define __ASM_SH_STRING_64_H
+
+/*
+ * include/asm-sh/string_64.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *dest, const void *src, size_t count);
+
+#endif /* __ASM_SH_STRING_64_H */
diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h
new file mode 100644
index 000000000000..056d68cd2108
--- /dev/null
+++ b/arch/sh/include/asm/system.h
@@ -0,0 +1,190 @@
+#ifndef __ASM_SH_SYSTEM_H
+#define __ASM_SH_SYSTEM_H
+
+/*
+ * Copyright (C) 1999, 2000  Niibe Yutaka  &  Kaz Kojima
+ * Copyright (C) 2002 Paul Mundt
+ */
+
+#include <linux/irqflags.h>
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <asm/types.h>
+#include <asm/ptrace.h>
+
+#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
+
+#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
+#define __icbi()                        \
+{                                       \
+        unsigned long __addr;           \
+        __addr = 0xa8000000;            \
+        __asm__ __volatile__(           \
+                "icbi   %0\n\t"         \
+                : /* no output */       \
+                : "m" (__m(__addr)));   \
+}
+#endif
+
+/*
+ * A brief note on ctrl_barrier(), the control register write barrier.
+ *
+ * Legacy SH cores typically require a sequence of 8 nops after
+ * modification of a control register in order for the changes to take
+ * effect. On newer cores (like the sh4a and sh5) this is accomplished
+ * with icbi.
+ *
+ * Also note that on sh4a in the icbi case we can forego a synco for the
+ * write barrier, as it's not necessary for control registers.
+ *
+ * Historically we have only done this type of barrier for the MMUCR, but
+ * it's also necessary for the CCR, so we make it generic here instead.
+ */
+#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
+#define mb()            __asm__ __volatile__ ("synco": : :"memory")
+#define rmb()           mb()
+#define wmb()           __asm__ __volatile__ ("synco": : :"memory")
+#define ctrl_barrier()  __icbi()
+#define read_barrier_depends()  do { } while(0)
+#else
+#define mb()            __asm__ __volatile__ ("": : :"memory")
+#define rmb()           mb()
+#define wmb()           __asm__ __volatile__ ("": : :"memory")
+#define ctrl_barrier()  __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
+#define read_barrier_depends()  do { } while(0)
+#endif
+
+#ifdef CONFIG_SMP
+#define smp_mb()        mb()
+#define smp_rmb()       rmb()
+#define smp_wmb()       wmb()
+#define smp_read_barrier_depends()      read_barrier_depends()
+#else
+#define smp_mb()        barrier()
+#define smp_rmb()       barrier()
+#define smp_wmb()       barrier()
+#define smp_read_barrier_depends()      do { } while(0)
+#endif
+
+#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
+
+#ifdef CONFIG_GUSA_RB
+#include <asm/cmpxchg-grb.h>
+#else
+#include <asm/cmpxchg-irq.h>
+#endif
+
+extern void __xchg_called_with_bad_pointer(void);
+
+#define __xchg(ptr, x, size)                            \
+({                                                      \
+        unsigned long __xchg__res;                      \
+        volatile void *__xchg_ptr = (ptr);              \
+        switch (size) {                                 \
+        case 4:                                         \
+                __xchg__res = xchg_u32(__xchg_ptr, x);  \
+                break;                                  \
+        case 1:                                         \
+                __xchg__res = xchg_u8(__xchg_ptr, x);   \
+                break;                                  \
+        default:                                        \
+                __xchg_called_with_bad_pointer();       \
+                __xchg__res = x;                        \
+                break;                                  \
+        }                                               \
+                                                        \
+        __xchg__res;                                    \
+})
+
+#define xchg(ptr,x)     \
+        ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
+
+/* This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid cmpxchg(). */
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+#define __HAVE_ARCH_CMPXCHG 1
+
+static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
+                unsigned long new, int size)
+{
+        switch (size) {
+        case 4:
+                return __cmpxchg_u32(ptr, old, new);
+        }
+        __cmpxchg_called_with_bad_pointer();
+        return old;
+}
+
+#define cmpxchg(ptr,o,n)                                                 \
+  ({                                                                     \
+     __typeof__(*(ptr)) _o_ = (o);                                       \
+     __typeof__(*(ptr)) _n_ = (n);                                       \
+     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
+                                    (unsigned long)_n_, sizeof(*(ptr))); \
+  })
+
+extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
+
+extern void *set_exception_table_vec(unsigned int vec, void *handler);
+
+static inline void *set_exception_table_evt(unsigned int evt, void *handler)
+{
+        return set_exception_table_vec(evt >> 5, handler);
+}
+
+/*
+ * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
+ */
+#ifdef CONFIG_CPU_SH2A
+extern unsigned int instruction_size(unsigned int insn);
+#elif defined(CONFIG_SUPERH32)
+#define instruction_size(insn)  (2)
+#else
+#define instruction_size(insn)  (4)
+#endif
+
+extern unsigned long cached_to_uncached;
+
+extern struct dentry *sh_debugfs_root;
+
+void per_cpu_trap_init(void);
+
+asmlinkage void break_point_trap(void);
+
+#ifdef CONFIG_SUPERH32
+#define BUILD_TRAP_HANDLER(name)                                        \
+asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \
+                                    unsigned long r6, unsigned long r7, \
+                                    struct pt_regs __regs)
+
+#define TRAP_HANDLER_DECL                               \
+        struct pt_regs *regs = RELOC_HIDE(&__regs, 0);  \
+        unsigned int vec = regs->tra;                   \
+        (void)vec;
+#else
+#define BUILD_TRAP_HANDLER(name)        \
+asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs)
+#define TRAP_HANDLER_DECL
+#endif
+
+BUILD_TRAP_HANDLER(address_error);
+BUILD_TRAP_HANDLER(debug);
+BUILD_TRAP_HANDLER(bug);
+BUILD_TRAP_HANDLER(fpu_error);
+BUILD_TRAP_HANDLER(fpu_state_restore);
+
+#define arch_align_stack(x) (x)
+
+struct mem_access {
+        unsigned long (*from)(void *dst, const void *src, unsigned long cnt);
+        unsigned long (*to)(void *dst, const void *src, unsigned long cnt);
+};
+
+#ifdef CONFIG_SUPERH32
+# include "system_32.h"
+#else
+# include "system_64.h"
+#endif
+
+#endif
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h
new file mode 100644
index 000000000000..f11bcf0855ed
--- /dev/null
+++ b/arch/sh/include/asm/system_32.h
@@ -0,0 +1,102 @@
+#ifndef __ASM_SH_SYSTEM_32_H
+#define __ASM_SH_SYSTEM_32_H
+
+#include <linux/types.h>
+
+struct task_struct *__switch_to(struct task_struct *prev,
+                                struct task_struct *next);
+
+/*
+ *      switch_to() should switch tasks to task nr n, first
+ */
+#define switch_to(prev, next, last)                                     \
+do {                                                                    \
+        register u32 *__ts1 __asm__ ("r1") = (u32 *)&prev->thread.sp;   \
+        register u32 *__ts2 __asm__ ("r2") = (u32 *)&prev->thread.pc;   \
+        register u32 *__ts4 __asm__ ("r4") = (u32 *)prev;               \
+        register u32 *__ts5 __asm__ ("r5") = (u32 *)next;               \
+        register u32 *__ts6 __asm__ ("r6") = (u32 *)&next->thread.sp;   \
+        register u32 __ts7 __asm__ ("r7") = next->thread.pc;            \
+        struct task_struct *__last;                                     \
+                                                                        \
+        __asm__ __volatile__ (                                          \
+                ".balign 4\n\t"                                         \
+                "stc.l  gbr, @-r15\n\t"                                 \
+                "sts.l  pr, @-r15\n\t"                                  \
+                "mov.l  r8, @-r15\n\t"                                  \
+                "mov.l  r9, @-r15\n\t"                                  \
+                "mov.l  r10, @-r15\n\t"                                 \
+                "mov.l  r11, @-r15\n\t"                                 \
+                "mov.l  r12, @-r15\n\t"                                 \
+                "mov.l  r13, @-r15\n\t"                                 \
+                "mov.l  r14, @-r15\n\t"                                 \
+                "mov.l  r15, @r1\t! save SP\n\t"                        \
+                "mov.l  @r6, r15\t! change to new stack\n\t"            \
+                "mova   1f, %0\n\t"                                     \
+                "mov.l  %0, @r2\t! save PC\n\t"                         \
+                "mov.l  2f, %0\n\t"                                     \
+                "jmp    @%0\t! call __switch_to\n\t"                    \
+                " lds   r7, pr\t!  with return to new PC\n\t"           \
+                ".balign        4\n"                                    \
+                "2:\n\t"                                                \
+                ".long  __switch_to\n"                                  \
+                "1:\n\t"                                                \
+                "mov.l  @r15+, r14\n\t"                                 \
+                "mov.l  @r15+, r13\n\t"                                 \
+                "mov.l  @r15+, r12\n\t"                                 \
+                "mov.l  @r15+, r11\n\t"                                 \
+                "mov.l  @r15+, r10\n\t"                                 \
+                "mov.l  @r15+, r9\n\t"                                  \
+                "mov.l  @r15+, r8\n\t"                                  \
+                "lds.l  @r15+, pr\n\t"                                  \
+                "ldc.l  @r15+, gbr\n\t"                                 \
+                : "=z" (__last)                                         \
+                : "r" (__ts1), "r" (__ts2), "r" (__ts4),                \
+                  "r" (__ts5), "r" (__ts6), "r" (__ts7)                 \
+                : "r3", "t");                                           \
+                                                                        \
+        last = __last;                                                  \
+} while (0)
+
+#define __uses_jump_to_uncached __attribute__ ((__section__ (".uncached.text")))
+
+/*
+ * Jump to uncached area.
+ * When handling TLB or caches, we need to do it from an uncached area.
+ */
+#define jump_to_uncached()                      \
+do {                                            \
+        unsigned long __dummy;                  \
+                                                \
+        __asm__ __volatile__(                   \
+                "mova   1f, %0\n\t"             \
+                "add    %1, %0\n\t"             \
+                "jmp    @%0\n\t"                \
+                " nop\n\t"                      \
+                ".balign 4\n"                   \
+                "1:"                            \
+                : "=&z" (__dummy)               \
+                : "r" (cached_to_uncached));    \
+} while (0)
+
+/*
+ * Back to cached area.
+ */
+#define back_to_cached()                                \
+do {                                                    \
+        unsigned long __dummy;                          \
+        ctrl_barrier();                                 \
+        __asm__ __volatile__(                           \
+                "mov.l  1f, %0\n\t"                     \
+                "jmp    @%0\n\t"                        \
+                " nop\n\t"                              \
+                ".balign 4\n"                           \
+                "1:     .long 2f\n"                     \
+                "2:"                                    \
+                : "=&r" (__dummy));                     \
+} while (0)
+
+int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs,
+                            struct mem_access *ma);
+
+#endif /* __ASM_SH_SYSTEM_32_H */
diff --git a/arch/sh/include/asm/system_64.h b/arch/sh/include/asm/system_64.h
new file mode 100644
index 000000000000..943acf5ea07c
--- /dev/null
+++ b/arch/sh/include/asm/system_64.h
@@ -0,0 +1,40 @@
+#ifndef __ASM_SH_SYSTEM_64_H
+#define __ASM_SH_SYSTEM_64_H
+
+/*
+ * include/asm-sh/system_64.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003  Paul Mundt
+ * Copyright (C) 2004  Richard Curnow
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <asm/processor.h>
+
+/*
+ *      switch_to() should switch tasks to task nr n, first
+ */
+struct task_struct *sh64_switch_to(struct task_struct *prev,
+                                   struct thread_struct *prev_thread,
+                                   struct task_struct *next,
+                                   struct thread_struct *next_thread);
+
+#define switch_to(prev,next,last)                               \
+do {                                                            \
+        if (last_task_used_math != next) {                      \
+                struct pt_regs *regs = next->thread.uregs;      \
+                if (regs) regs->sr |= SR_FD;                    \
+        }                                                       \
+        last = sh64_switch_to(prev, &prev->thread, next,        \
+                              &next->thread);                   \
+} while (0)
+
+#define __uses_jump_to_uncached
+
+#define jump_to_uncached()      do { } while (0)
+#define back_to_cached()        do { } while (0)
+
+#endif /* __ASM_SH_SYSTEM_64_H */
diff --git a/arch/sh/include/asm/systemh7751.h b/arch/sh/include/asm/systemh7751.h
new file mode 100644
index 000000000000..4161122c84ef
--- /dev/null
+++ b/arch/sh/include/asm/systemh7751.h
@@ -0,0 +1,71 @@
+#ifndef __ASM_SH_SYSTEMH_7751SYSTEMH_H
+#define __ASM_SH_SYSTEMH_7751SYSTEMH_H
+
+/*
+ * linux/include/asm-sh/systemh/7751systemh.h
+ *
+ * Copyright (C) 2000  Kazumoto Kojima
+ *
+ * Hitachi SystemH support
+
+ * Modified for 7751 SystemH by
+ * Jonathan Short, 2002.
+ */
+
+/* Box specific addresses.  */
+
+#define PA_ROM          0x00000000      /* EPROM */
+#define PA_ROM_SIZE     0x00400000      /* EPROM size 4M byte */
+#define PA_FROM         0x01000000      /* EPROM */
+#define PA_FROM_SIZE    0x00400000      /* EPROM size 4M byte */
+#define PA_EXT1         0x04000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_EXT2         0x08000000
+#define PA_EXT2_SIZE    0x04000000
+#define PA_SDRAM        0x0c000000
+#define PA_SDRAM_SIZE   0x04000000
+
+#define PA_EXT4         0x12000000
+#define PA_EXT4_SIZE    0x02000000
+#define PA_EXT5         0x14000000
+#define PA_EXT5_SIZE    0x04000000
+#define PA_PCIC         0x18000000      /* MR-SHPC-01 PCMCIA */
+
+#define PA_DIPSW0       0xb9000000      /* Dip switch 5,6 */
+#define PA_DIPSW1       0xb9000002      /* Dip switch 7,8 */
+#define PA_LED          0xba000000      /* LED */
+#define PA_BCR          0xbb000000      /* FPGA on the MS7751SE01 */
+
+#define PA_MRSHPC       0xb83fffe0      /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1   0xb8400000      /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2   0xb8500000      /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO    0xb8600000      /* MR-SHPC-01 I/O window base */
+#define MRSHPC_MODE     (PA_MRSHPC + 4)
+#define MRSHPC_OPTION   (PA_MRSHPC + 6)
+#define MRSHPC_CSR      (PA_MRSHPC + 8)
+#define MRSHPC_ISR      (PA_MRSHPC + 10)
+#define MRSHPC_ICR      (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
+#define MRSHPC_CDCR     (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define BCR_ILCRA       (PA_BCR + 0)
+#define BCR_ILCRB       (PA_BCR + 2)
+#define BCR_ILCRC       (PA_BCR + 4)
+#define BCR_ILCRD       (PA_BCR + 6)
+#define BCR_ILCRE       (PA_BCR + 8)
+#define BCR_ILCRF       (PA_BCR + 10)
+#define BCR_ILCRG       (PA_BCR + 12)
+
+#define IRQ_79C973      13
+
+#define __IO_PREFIX     sh7751systemh
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_SYSTEMH_7751SYSTEMH_H */
diff --git a/arch/sh/include/asm/termbits.h b/arch/sh/include/asm/termbits.h
new file mode 100644
index 000000000000..77db116948cf
--- /dev/null
+++ b/arch/sh/include/asm/termbits.h
@@ -0,0 +1,198 @@
+#ifndef __ASM_SH_TERMBITS_H
+#define __ASM_SH_TERMBITS_H
+
+#include <linux/posix_types.h>
+
+typedef unsigned char   cc_t;
+typedef unsigned int    speed_t;
+typedef unsigned int    tcflag_t;
+
+#define NCCS 19
+struct termios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+};
+
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+/* c_cc characters */
+#define VINTR 0
+#define VQUIT 1
+#define VERASE 2
+#define VKILL 3
+#define VEOF 4
+#define VTIME 5
+#define VMIN 6
+#define VSWTC 7
+#define VSTART 8
+#define VSTOP 9
+#define VSUSP 10
+#define VEOL 11
+#define VREPRINT 12
+#define VDISCARD 13
+#define VWERASE 14
+#define VLNEXT 15
+#define VEOL2 16
+
+/* c_iflag bits */
+#define IGNBRK  0000001
+#define BRKINT  0000002
+#define IGNPAR  0000004
+#define PARMRK  0000010
+#define INPCK   0000020
+#define ISTRIP  0000040
+#define INLCR   0000100
+#define IGNCR   0000200
+#define ICRNL   0000400
+#define IUCLC   0001000
+#define IXON    0002000
+#define IXANY   0004000
+#define IXOFF   0010000
+#define IMAXBEL 0020000
+#define IUTF8   0040000
+
+/* c_oflag bits */
+#define OPOST   0000001
+#define OLCUC   0000002
+#define ONLCR   0000004
+#define OCRNL   0000010
+#define ONOCR   0000020
+#define ONLRET  0000040
+#define OFILL   0000100
+#define OFDEL   0000200
+#define NLDLY   0000400
+#define   NL0   0000000
+#define   NL1   0000400
+#define CRDLY   0003000
+#define   CR0   0000000
+#define   CR1   0001000
+#define   CR2   0002000
+#define   CR3   0003000
+#define TABDLY  0014000
+#define   TAB0  0000000
+#define   TAB1  0004000
+#define   TAB2  0010000
+#define   TAB3  0014000
+#define   XTABS 0014000
+#define BSDLY   0020000
+#define   BS0   0000000
+#define   BS1   0020000
+#define VTDLY   0040000
+#define   VT0   0000000
+#define   VT1   0040000
+#define FFDLY   0100000
+#define   FF0   0000000
+#define   FF1   0100000
+
+/* c_cflag bit meaning */
+#define CBAUD   0010017
+#define  B0     0000000         /* hang up */
+#define  B50    0000001
+#define  B75    0000002
+#define  B110   0000003
+#define  B134   0000004
+#define  B150   0000005
+#define  B200   0000006
+#define  B300   0000007
+#define  B600   0000010
+#define  B1200  0000011
+#define  B1800  0000012
+#define  B2400  0000013
+#define  B4800  0000014
+#define  B9600  0000015
+#define  B19200 0000016
+#define  B38400 0000017
+#define EXTA B19200
+#define EXTB B38400
+#define CSIZE   0000060
+#define   CS5   0000000
+#define   CS6   0000020
+#define   CS7   0000040
+#define   CS8   0000060
+#define CSTOPB  0000100
+#define CREAD   0000200
+#define PARENB  0000400
+#define PARODD  0001000
+#define HUPCL   0002000
+#define CLOCAL  0004000
+#define CBAUDEX 0010000
+#define    BOTHER 0010000
+#define    B57600 0010001
+#define   B115200 0010002
+#define   B230400 0010003
+#define   B460800 0010004
+#define   B500000 0010005
+#define   B576000 0010006
+#define   B921600 0010007
+#define  B1000000 0010010
+#define  B1152000 0010011
+#define  B1500000 0010012
+#define  B2000000 0010013
+#define  B2500000 0010014
+#define  B3000000 0010015
+#define  B3500000 0010016
+#define  B4000000 0010017
+#define CIBAUD    002003600000          /* input baud rate */
+#define CMSPAR    010000000000          /* mark or space (stick) parity */
+#define CRTSCTS   020000000000          /* flow control */
+
+#define IBSHIFT 16              /* Shift from CBAUD to CIBAUD */
+
+/* c_lflag bits */
+#define ISIG    0000001
+#define ICANON  0000002
+#define XCASE   0000004
+#define ECHO    0000010
+#define ECHOE   0000020
+#define ECHOK   0000040
+#define ECHONL  0000100
+#define NOFLSH  0000200
+#define TOSTOP  0000400
+#define ECHOCTL 0001000
+#define ECHOPRT 0002000
+#define ECHOKE  0004000
+#define FLUSHO  0010000
+#define PENDIN  0040000
+#define IEXTEN  0100000
+
+/* tcflow() and TCXONC use these */
+#define TCOOFF          0
+#define TCOON           1
+#define TCIOFF          2
+#define TCION           3
+
+/* tcflush() and TCFLSH use these */
+#define TCIFLUSH        0
+#define TCOFLUSH        1
+#define TCIOFLUSH       2
+
+/* tcsetattr uses these */
+#define TCSANOW         0
+#define TCSADRAIN       1
+#define TCSAFLUSH       2
+
+#endif /* __ASM_SH_TERMBITS_H */
diff --git a/arch/sh/include/asm/termios.h b/arch/sh/include/asm/termios.h
new file mode 100644
index 000000000000..0a8c793c76f2
--- /dev/null
+++ b/arch/sh/include/asm/termios.h
@@ -0,0 +1,90 @@
+#ifndef __ASM_SH_TERMIOS_H
+#define __ASM_SH_TERMIOS_H
+
+#include <asm/termbits.h>
+#include <asm/ioctls.h>
+
+struct winsize {
+        unsigned short ws_row;
+        unsigned short ws_col;
+        unsigned short ws_xpixel;
+        unsigned short ws_ypixel;
+};
+
+#define NCC 8
+struct termio {
+        unsigned short c_iflag;         /* input mode flags */
+        unsigned short c_oflag;         /* output mode flags */
+        unsigned short c_cflag;         /* control mode flags */
+        unsigned short c_lflag;         /* local mode flags */
+        unsigned char c_line;           /* line discipline */
+        unsigned char c_cc[NCC];        /* control characters */
+};
+
+/* modem lines */
+#define TIOCM_LE        0x001
+#define TIOCM_DTR       0x002
+#define TIOCM_RTS       0x004
+#define TIOCM_ST        0x008
+#define TIOCM_SR        0x010
+#define TIOCM_CTS       0x020
+#define TIOCM_CAR       0x040
+#define TIOCM_RNG       0x080
+#define TIOCM_DSR       0x100
+#define TIOCM_CD        TIOCM_CAR
+#define TIOCM_RI        TIOCM_RNG
+#define TIOCM_OUT1      0x2000
+#define TIOCM_OUT2      0x4000
+#define TIOCM_LOOP      0x8000
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+
+#ifdef __KERNEL__
+
+/*      intr=^C         quit=^\         erase=del       kill=^U
+        eof=^D          vtime=\0        vmin=\1         sxtc=\0
+        start=^Q        stop=^S         susp=^Z         eol=\0
+        reprint=^R      discard=^U      werase=^W       lnext=^V
+        eol2=\0
+*/
+#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
+
+/*
+ * Translate a "termio" structure into a "termios". Ugh.
+ */
+#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
+        unsigned short __tmp; \
+        get_user(__tmp,&(termio)->x); \
+        *(unsigned short *) &(termios)->x = __tmp; \
+}
+
+#define user_termio_to_kernel_termios(termios, termio) \
+({ \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
+        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
+})
+
+/*
+ * Translate a "termios" structure into a "termio". Ugh.
+ */
+#define kernel_termios_to_user_termio(termio, termios) \
+({ \
+        put_user((termios)->c_iflag, &(termio)->c_iflag); \
+        put_user((termios)->c_oflag, &(termio)->c_oflag); \
+        put_user((termios)->c_cflag, &(termio)->c_cflag); \
+        put_user((termios)->c_lflag, &(termio)->c_lflag); \
+        put_user((termios)->c_line,  &(termio)->c_line); \
+        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
+})
+
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
+#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
+
+#endif  /* __KERNEL__ */
+
+#endif  /* __ASM_SH_TERMIOS_H */
diff --git a/arch/sh/include/asm/thread_info.h b/arch/sh/include/asm/thread_info.h
new file mode 100644
index 000000000000..eeb4c747119e
--- /dev/null
+++ b/arch/sh/include/asm/thread_info.h
@@ -0,0 +1,141 @@
+#ifndef __ASM_SH_THREAD_INFO_H
+#define __ASM_SH_THREAD_INFO_H
+
+/* SuperH version
+ * Copyright (C) 2002  Niibe Yutaka
+ *
+ * The copyright of original i386 version is:
+ *
+ *  Copyright (C) 2002  David Howells (dhowells@redhat.com)
+ *  - Incorporating suggestions made by Linus Torvalds and Dave Miller
+ */
+#ifdef __KERNEL__
+#include <asm/page.h>
+
+#ifndef __ASSEMBLY__
+#include <asm/processor.h>
+
+struct thread_info {
+        struct task_struct      *task;          /* main task structure */
+        struct exec_domain      *exec_domain;   /* execution domain */
+        unsigned long           flags;          /* low level flags */
+        __u32                   cpu;
+        int                     preempt_count; /* 0 => preemptable, <0 => BUG */
+        mm_segment_t            addr_limit;     /* thread address space */
+        struct restart_block    restart_block;
+        unsigned long           previous_sp;    /* sp of previous stack in case
+                                                   of nested IRQ stacks */
+        __u8                    supervisor_stack[0];
+};
+
+#endif
+
+#define PREEMPT_ACTIVE          0x10000000
+
+#if defined(CONFIG_4KSTACKS)
+#define THREAD_SIZE_ORDER       (0)
+#elif defined(CONFIG_PAGE_SIZE_4KB)
+#define THREAD_SIZE_ORDER       (1)
+#elif defined(CONFIG_PAGE_SIZE_8KB)
+#define THREAD_SIZE_ORDER       (1)
+#elif defined(CONFIG_PAGE_SIZE_16KB)
+#define THREAD_SIZE_ORDER       (0)
+#elif defined(CONFIG_PAGE_SIZE_64KB)
+#define THREAD_SIZE_ORDER       (0)
+#else
+#error "Unknown thread size"
+#endif
+
+#define THREAD_SIZE     (PAGE_SIZE << THREAD_SIZE_ORDER)
+#define STACK_WARN      (THREAD_SIZE >> 3)
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ */
+#ifndef __ASSEMBLY__
+#define INIT_THREAD_INFO(tsk)                   \
+{                                               \
+        .task           = &tsk,                 \
+        .exec_domain    = &default_exec_domain, \
+        .flags          = 0,                    \
+        .cpu            = 0,                    \
+        .preempt_count  = 1,                    \
+        .addr_limit     = KERNEL_DS,            \
+        .restart_block  = {                     \
+                .fn = do_no_restart_syscall,    \
+        },                                      \
+}
+
+#define init_thread_info        (init_thread_union.thread_info)
+#define init_stack              (init_thread_union.stack)
+
+/* how to get the current stack pointer from C */
+register unsigned long current_stack_pointer asm("r15") __used;
+
+/* how to get the thread information struct from C */
+static inline struct thread_info *current_thread_info(void)
+{
+        struct thread_info *ti;
+#if defined(CONFIG_SUPERH64)
+        __asm__ __volatile__ ("getcon   cr17, %0" : "=r" (ti));
+#elif defined(CONFIG_CPU_HAS_SR_RB)
+        __asm__ __volatile__ ("stc      r7_bank, %0" : "=r" (ti));
+#else
+        unsigned long __dummy;
+
+        __asm__ __volatile__ (
+                "mov    r15, %0\n\t"
+                "and    %1, %0\n\t"
+                : "=&r" (ti), "=r" (__dummy)
+                : "1" (~(THREAD_SIZE - 1))
+                : "memory");
+#endif
+
+        return ti;
+}
+
+#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
+
+/* thread information allocation */
+#ifdef CONFIG_DEBUG_STACK_USAGE
+#define alloc_thread_info(ti)   kzalloc(THREAD_SIZE, GFP_KERNEL)
+#else
+#define alloc_thread_info(ti)   kmalloc(THREAD_SIZE, GFP_KERNEL)
+#endif
+#define free_thread_info(ti)    kfree(ti)
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * thread information flags
+ * - these are process state flags that various assembly files may need to access
+ * - pending work-to-be-done flags are in LSW
+ * - other flags in MSW
+ */
+#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
+#define TIF_SIGPENDING          1       /* signal pending */
+#define TIF_NEED_RESCHED        2       /* rescheduling necessary */
+#define TIF_RESTORE_SIGMASK     3       /* restore signal mask in do_signal() */
+#define TIF_SINGLESTEP          4       /* singlestepping active */
+#define TIF_SYSCALL_AUDIT       5
+#define TIF_USEDFPU             16      /* FPU was used by this task this quantum (SMP) */
+#define TIF_POLLING_NRFLAG      17      /* true if poll_idle() is polling TIF_NEED_RESCHED */
+#define TIF_MEMDIE              18
+#define TIF_FREEZE              19
+
+#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
+#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
+#define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
+#define _TIF_SINGLESTEP         (1<<TIF_SINGLESTEP)
+#define _TIF_SYSCALL_AUDIT              (1<<TIF_SYSCALL_AUDIT)
+#define _TIF_USEDFPU            (1<<TIF_USEDFPU)
+#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
+#define _TIF_FREEZE             (1<<TIF_FREEZE)
+
+#define _TIF_WORK_MASK          0x000000FE      /* work to do on interrupt/exception return */
+#define _TIF_ALLWORK_MASK       0x000000FF      /* work to do on any return to u-space */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_THREAD_INFO_H */
diff --git a/arch/sh/include/asm/timer.h b/arch/sh/include/asm/timer.h
new file mode 100644
index 000000000000..a7ca3a195bb5
--- /dev/null
+++ b/arch/sh/include/asm/timer.h
@@ -0,0 +1,44 @@
+#ifndef __ASM_SH_TIMER_H
+#define __ASM_SH_TIMER_H
+
+#include <linux/sysdev.h>
+#include <linux/clocksource.h>
+#include <cpu/timer.h>
+
+struct sys_timer_ops {
+        int (*init)(void);
+        int (*start)(void);
+        int (*stop)(void);
+        cycle_t (*read)(void);
+#ifndef CONFIG_GENERIC_TIME
+        unsigned long (*get_offset)(void);
+#endif
+};
+
+struct sys_timer {
+        const char              *name;
+
+        struct sys_device       dev;
+        struct sys_timer_ops    *ops;
+};
+
+#define TICK_SIZE (tick_nsec / 1000)
+
+extern struct sys_timer tmu_timer, cmt_timer, mtu2_timer;
+extern struct sys_timer *sys_timer;
+
+#ifndef CONFIG_GENERIC_TIME
+static inline unsigned long get_timer_offset(void)
+{
+        return sys_timer->ops->get_offset();
+}
+#endif
+
+/* arch/sh/kernel/timers/timer.c */
+struct sys_timer *get_sys_timer(void);
+
+/* arch/sh/kernel/time.c */
+void handle_timer_tick(void);
+extern unsigned long sh_hpt_frequency;
+
+#endif /* __ASM_SH_TIMER_H */
diff --git a/arch/sh/include/asm/timex.h b/arch/sh/include/asm/timex.h
new file mode 100644
index 000000000000..a873e24113cf
--- /dev/null
+++ b/arch/sh/include/asm/timex.h
@@ -0,0 +1,18 @@
+/*
+ * linux/include/asm-sh/timex.h
+ *
+ * sh architecture timex specifications
+ */
+#ifndef __ASM_SH_TIMEX_H
+#define __ASM_SH_TIMEX_H
+
+#define CLOCK_TICK_RATE         (CONFIG_SH_PCLK_FREQ / 4) /* Underlying HZ */
+
+typedef unsigned long long cycles_t;
+
+static __inline__ cycles_t get_cycles (void)
+{
+        return 0;
+}
+
+#endif /* __ASM_SH_TIMEX_H */
diff --git a/arch/sh/include/asm/titan.h b/arch/sh/include/asm/titan.h
new file mode 100644
index 000000000000..03f3583c8918
--- /dev/null
+++ b/arch/sh/include/asm/titan.h
@@ -0,0 +1,17 @@
+/*
+ * Platform defintions for Titan
+ */
+#ifndef _ASM_SH_TITAN_H
+#define _ASM_SH_TITAN_H
+
+#define __IO_PREFIX titan
+#include <asm/io_generic.h>
+
+/* IRQ assignments */
+#define TITAN_IRQ_WAN           2       /* eth0 (WAN) */
+#define TITAN_IRQ_LAN           5       /* eth1 (LAN) */
+#define TITAN_IRQ_MPCIA         8       /* mPCI A */
+#define TITAN_IRQ_MPCIB         11      /* mPCI B */
+#define TITAN_IRQ_USB           11      /* USB */
+
+#endif /* __ASM_SH_TITAN_H */
diff --git a/arch/sh/include/asm/tlb.h b/arch/sh/include/asm/tlb.h
new file mode 100644
index 000000000000..88ff1ae8a6b8
--- /dev/null
+++ b/arch/sh/include/asm/tlb.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_SH_TLB_H
+#define __ASM_SH_TLB_H
+
+#ifdef CONFIG_SUPERH64
+# include "tlb_64.h"
+#endif
+
+#ifndef __ASSEMBLY__
+
+#define tlb_start_vma(tlb, vma) \
+        flush_cache_range(vma, vma->vm_start, vma->vm_end)
+
+#define tlb_end_vma(tlb, vma)   \
+        flush_tlb_range(vma, vma->vm_start, vma->vm_end)
+
+#define __tlb_remove_tlb_entry(tlb, pte, address)       do { } while (0)
+
+/*
+ * Flush whole TLBs for MM
+ */
+#define tlb_flush(tlb)                          flush_tlb_mm((tlb)->mm)
+
+#include <linux/pagemap.h>
+#include <asm-generic/tlb.h>
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_SH_TLB_H */
diff --git a/arch/sh/include/asm/tlb_64.h b/arch/sh/include/asm/tlb_64.h
new file mode 100644
index 000000000000..0a96f3af69e3
--- /dev/null
+++ b/arch/sh/include/asm/tlb_64.h
@@ -0,0 +1,77 @@
+/*
+ * include/asm-sh/tlb_64.h
+ *
+ * Copyright (C) 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_TLB_64_H
+#define __ASM_SH_TLB_64_H
+
+/* ITLB defines */
+#define ITLB_FIXED      0x00000000      /* First fixed ITLB, see head.S */
+#define ITLB_LAST_VAR_UNRESTRICTED      0x000003F0      /* Last ITLB */
+
+/* DTLB defines */
+#define DTLB_FIXED      0x00800000      /* First fixed DTLB, see head.S */
+#define DTLB_LAST_VAR_UNRESTRICTED      0x008003F0      /* Last DTLB */
+
+#ifndef __ASSEMBLY__
+
+/**
+ * for_each_dtlb_entry
+ *
+ * @tlb:        TLB entry
+ *
+ * Iterate over free (non-wired) DTLB entries
+ */
+#define for_each_dtlb_entry(tlb)                \
+        for (tlb  = cpu_data->dtlb.first;       \
+             tlb <= cpu_data->dtlb.last;        \
+             tlb += cpu_data->dtlb.step)
+
+/**
+ * for_each_itlb_entry
+ *
+ * @tlb:        TLB entry
+ *
+ * Iterate over free (non-wired) ITLB entries
+ */
+#define for_each_itlb_entry(tlb)                \
+        for (tlb  = cpu_data->itlb.first;       \
+             tlb <= cpu_data->itlb.last;        \
+             tlb += cpu_data->itlb.step)
+
+/**
+ * __flush_tlb_slot
+ *
+ * @slot:       Address of TLB slot.
+ *
+ * Flushes TLB slot @slot.
+ */
+static inline void __flush_tlb_slot(unsigned long long slot)
+{
+        __asm__ __volatile__ ("putcfg %0, 0, r63\n" : : "r" (slot));
+}
+
+#ifdef CONFIG_MMU
+/* arch/sh64/mm/tlb.c */
+int sh64_tlb_init(void);
+unsigned long long sh64_next_free_dtlb_entry(void);
+unsigned long long sh64_get_wired_dtlb_entry(void);
+int sh64_put_wired_dtlb_entry(unsigned long long entry);
+void sh64_setup_tlb_slot(unsigned long long config_addr, unsigned long eaddr,
+                         unsigned long asid, unsigned long paddr);
+void sh64_teardown_tlb_slot(unsigned long long config_addr);
+#else
+#define sh64_tlb_init()                                 do { } while (0)
+#define sh64_next_free_dtlb_entry()                     (0)
+#define sh64_get_wired_dtlb_entry()                     (0)
+#define sh64_put_wired_dtlb_entry(entry)                do { } while (0)
+#define sh64_setup_tlb_slot(conf, virt, asid, phys)     do { } while (0)
+#define sh64_teardown_tlb_slot(addr)                    do { } while (0)
+#endif /* CONFIG_MMU */
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_SH_TLB_64_H */
diff --git a/arch/sh/include/asm/tlbflush.h b/arch/sh/include/asm/tlbflush.h
new file mode 100644
index 000000000000..e0ac97221ae6
--- /dev/null
+++ b/arch/sh/include/asm/tlbflush.h
@@ -0,0 +1,49 @@
+#ifndef __ASM_SH_TLBFLUSH_H
+#define __ASM_SH_TLBFLUSH_H
+
+/*
+ * TLB flushing:
+ *
+ *  - flush_tlb_all() flushes all processes TLBs
+ *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
+ *  - flush_tlb_page(vma, vmaddr) flushes one page
+ *  - flush_tlb_range(vma, start, end) flushes a range of pages
+ *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
+ */
+extern void local_flush_tlb_all(void);
+extern void local_flush_tlb_mm(struct mm_struct *mm);
+extern void local_flush_tlb_range(struct vm_area_struct *vma,
+                                  unsigned long start,
+                                  unsigned long end);
+extern void local_flush_tlb_page(struct vm_area_struct *vma,
+                                 unsigned long page);
+extern void local_flush_tlb_kernel_range(unsigned long start,
+                                         unsigned long end);
+extern void local_flush_tlb_one(unsigned long asid, unsigned long page);
+
+#ifdef CONFIG_SMP
+
+extern void flush_tlb_all(void);
+extern void flush_tlb_mm(struct mm_struct *mm);
+extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
+                            unsigned long end);
+extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
+extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
+extern void flush_tlb_one(unsigned long asid, unsigned long page);
+
+#else
+
+#define flush_tlb_all()                 local_flush_tlb_all()
+#define flush_tlb_mm(mm)                local_flush_tlb_mm(mm)
+#define flush_tlb_page(vma, page)       local_flush_tlb_page(vma, page)
+#define flush_tlb_one(asid, page)       local_flush_tlb_one(asid, page)
+
+#define flush_tlb_range(vma, start, end)        \
+        local_flush_tlb_range(vma, start, end)
+
+#define flush_tlb_kernel_range(start, end)      \
+        local_flush_tlb_kernel_range(start, end)
+
+#endif /* CONFIG_SMP */
+
+#endif /* __ASM_SH_TLBFLUSH_H */
diff --git a/arch/sh/include/asm/topology.h b/arch/sh/include/asm/topology.h
new file mode 100644
index 000000000000..95f0085e098a
--- /dev/null
+++ b/arch/sh/include/asm/topology.h
@@ -0,0 +1,47 @@
+#ifndef _ASM_SH_TOPOLOGY_H
+#define _ASM_SH_TOPOLOGY_H
+
+#ifdef CONFIG_NUMA
+
+/* sched_domains SD_NODE_INIT for sh machines */
+#define SD_NODE_INIT (struct sched_domain) {            \
+        .span                   = CPU_MASK_NONE,        \
+        .parent                 = NULL,                 \
+        .child                  = NULL,                 \
+        .groups                 = NULL,                 \
+        .min_interval           = 8,                    \
+        .max_interval           = 32,                   \
+        .busy_factor            = 32,                   \
+        .imbalance_pct          = 125,                  \
+        .cache_nice_tries       = 2,                    \
+        .busy_idx               = 3,                    \
+        .idle_idx               = 2,                    \
+        .newidle_idx            = 2,                    \
+        .wake_idx               = 1,                    \
+        .forkexec_idx           = 1,                    \
+        .flags                  = SD_LOAD_BALANCE       \
+                                | SD_BALANCE_FORK       \
+                                | SD_BALANCE_EXEC       \
+                                | SD_SERIALIZE          \
+                                | SD_WAKE_BALANCE,      \
+        .last_balance           = jiffies,              \
+        .balance_interval       = 1,                    \
+        .nr_balance_failed      = 0,                    \
+}
+
+#define cpu_to_node(cpu)        ((void)(cpu),0)
+#define parent_node(node)       ((void)(node),0)
+
+#define node_to_cpumask(node)   ((void)node, cpu_online_map)
+#define node_to_first_cpu(node) ((void)(node),0)
+
+#define pcibus_to_node(bus)     ((void)(bus), -1)
+#define pcibus_to_cpumask(bus)  (pcibus_to_node(bus) == -1 ? \
+                                        CPU_MASK_ALL : \
+                                        node_to_cpumask(pcibus_to_node(bus)) \
+                                )
+#endif
+
+#include <asm-generic/topology.h>
+
+#endif /* _ASM_SH_TOPOLOGY_H */
diff --git a/arch/sh/include/asm/types.h b/arch/sh/include/asm/types.h
new file mode 100644
index 000000000000..beea4e6f8dfd
--- /dev/null
+++ b/arch/sh/include/asm/types.h
@@ -0,0 +1,35 @@
+#ifndef __ASM_SH_TYPES_H
+#define __ASM_SH_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+
+#ifdef CONFIG_SUPERH32
+typedef u16 opcode_t;
+#else
+typedef u32 opcode_t;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_TYPES_H */
diff --git a/arch/sh/include/asm/uaccess.h b/arch/sh/include/asm/uaccess.h
new file mode 100644
index 000000000000..075848f43b6a
--- /dev/null
+++ b/arch/sh/include/asm/uaccess.h
@@ -0,0 +1,258 @@
+#ifndef __ASM_SH_UACCESS_H
+#define __ASM_SH_UACCESS_H
+
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <asm/segment.h>
+
+#define VERIFY_READ    0
+#define VERIFY_WRITE   1
+
+#define __addr_ok(addr) \
+        ((unsigned long __force)(addr) < current_thread_info()->addr_limit.seg)
+
+/*
+ * __access_ok: Check if address with size is OK or not.
+ *
+ * Uhhuh, this needs 33-bit arithmetic. We have a carry..
+ *
+ * sum := addr + size;  carry? --> flag = true;
+ * if (sum >= addr_limit) flag = true;
+ */
+#define __access_ok(addr, size)         \
+        (__addr_ok((addr) + (size)))
+#define access_ok(type, addr, size)     \
+        (__chk_user_ptr(addr),          \
+         __access_ok((unsigned long __force)(addr), (size)))
+
+/*
+ * Uh, these should become the main single-value transfer routines ...
+ * They automatically use the right size if we just have the right
+ * pointer type ...
+ *
+ * As SuperH uses the same address space for kernel and user data, we
+ * can just do these as direct assignments.
+ *
+ * Careful to not
+ * (a) re-use the arguments for side effects (sizeof is ok)
+ * (b) require any knowledge of processes at this stage
+ */
+#define put_user(x,ptr)         __put_user_check((x), (ptr), sizeof(*(ptr)))
+#define get_user(x,ptr)         __get_user_check((x), (ptr), sizeof(*(ptr)))
+
+/*
+ * The "__xxx" versions do not do address space checking, useful when
+ * doing multiple accesses to the same area (the user has to do the
+ * checks by hand with "access_ok()")
+ */
+#define __put_user(x,ptr)       __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
+#define __get_user(x,ptr)       __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) (*(struct __large_struct __user *)(x))
+
+#define __get_user_nocheck(x,ptr,size)                          \
+({                                                              \
+        long __gu_err;                                          \
+        unsigned long __gu_val;                                 \
+        const __typeof__(*(ptr)) __user *__gu_addr = (ptr);     \
+        __chk_user_ptr(ptr);                                    \
+        __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
+        (x) = (__typeof__(*(ptr)))__gu_val;                     \
+        __gu_err;                                               \
+})
+
+#define __get_user_check(x,ptr,size)                                    \
+({                                                                      \
+        long __gu_err = -EFAULT;                                        \
+        unsigned long __gu_val = 0;                                     \
+        const __typeof__(*(ptr)) *__gu_addr = (ptr);                    \
+        if (likely(access_ok(VERIFY_READ, __gu_addr, (size))))          \
+                __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
+        (x) = (__typeof__(*(ptr)))__gu_val;                             \
+        __gu_err;                                                       \
+})
+
+#define __put_user_nocheck(x,ptr,size)                          \
+({                                                              \
+        long __pu_err;                                          \
+        __typeof__(*(ptr)) __user *__pu_addr = (ptr);           \
+        __typeof__(*(ptr)) __pu_val = x;                        \
+        __chk_user_ptr(ptr);                                    \
+        __put_user_size(__pu_val, __pu_addr, (size), __pu_err); \
+        __pu_err;                                               \
+})
+
+#define __put_user_check(x,ptr,size)                            \
+({                                                              \
+        long __pu_err = -EFAULT;                                \
+        __typeof__(*(ptr)) __user *__pu_addr = (ptr);           \
+        __typeof__(*(ptr)) __pu_val = x;                        \
+        if (likely(access_ok(VERIFY_WRITE, __pu_addr, size)))   \
+                __put_user_size(__pu_val, __pu_addr, (size),    \
+                                __pu_err);                      \
+        __pu_err;                                               \
+})
+
+#ifdef CONFIG_SUPERH32
+# include "uaccess_32.h"
+#else
+# include "uaccess_64.h"
+#endif
+
+/* Generic arbitrary sized copy.  */
+/* Return the number of bytes NOT copied */
+__kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n);
+
+static __always_inline unsigned long
+__copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+        return __copy_user(to, (__force void *)from, n);
+}
+
+static __always_inline unsigned long __must_check
+__copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+        return __copy_user((__force void *)to, from, n);
+}
+
+#define __copy_to_user_inatomic __copy_to_user
+#define __copy_from_user_inatomic __copy_from_user
+
+/*
+ * Clear the area and return remaining number of bytes
+ * (on failure.  Usually it's 0.)
+ */
+__kernel_size_t __clear_user(void *addr, __kernel_size_t size);
+
+#define clear_user(addr,n)                                              \
+({                                                                      \
+        void __user * __cl_addr = (addr);                               \
+        unsigned long __cl_size = (n);                                  \
+                                                                        \
+        if (__cl_size && access_ok(VERIFY_WRITE,                        \
+                ((unsigned long)(__cl_addr)), __cl_size))               \
+                __cl_size = __clear_user(__cl_addr, __cl_size);         \
+                                                                        \
+        __cl_size;                                                      \
+})
+
+/**
+ * strncpy_from_user: - Copy a NUL terminated string from userspace.
+ * @dst:   Destination address, in kernel space.  This buffer must be at
+ *         least @count bytes long.
+ * @src:   Source address, in user space.
+ * @count: Maximum number of bytes to copy, including the trailing NUL.
+ *
+ * Copies a NUL-terminated string from userspace to kernel space.
+ *
+ * On success, returns the length of the string (not including the trailing
+ * NUL).
+ *
+ * If access to userspace fails, returns -EFAULT (some data may have been
+ * copied).
+ *
+ * If @count is smaller than the length of the string, copies @count bytes
+ * and returns @count.
+ */
+#define strncpy_from_user(dest,src,count)                               \
+({                                                                      \
+        unsigned long __sfu_src = (unsigned long)(src);                 \
+        int __sfu_count = (int)(count);                                 \
+        long __sfu_res = -EFAULT;                                       \
+                                                                        \
+        if (__access_ok(__sfu_src, __sfu_count))                        \
+                __sfu_res = __strncpy_from_user((unsigned long)(dest),  \
+                                __sfu_src, __sfu_count);                \
+                                                                        \
+        __sfu_res;                                                      \
+})
+
+static inline unsigned long
+copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+        unsigned long __copy_from = (unsigned long) from;
+        __kernel_size_t __copy_size = (__kernel_size_t) n;
+
+        if (__copy_size && __access_ok(__copy_from, __copy_size))
+                return __copy_user(to, from, __copy_size);
+
+        return __copy_size;
+}
+
+static inline unsigned long
+copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+        unsigned long __copy_to = (unsigned long) to;
+        __kernel_size_t __copy_size = (__kernel_size_t) n;
+
+        if (__copy_size && __access_ok(__copy_to, __copy_size))
+                return __copy_user(to, from, __copy_size);
+
+        return __copy_size;
+}
+
+/**
+ * strnlen_user: - Get the size of a string in user space.
+ * @s: The string to measure.
+ * @n: The maximum valid length
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Get the size of a NUL-terminated string in user space.
+ *
+ * Returns the size of the string INCLUDING the terminating NUL.
+ * On exception, returns 0.
+ * If the string is too long, returns a value greater than @n.
+ */
+static inline long strnlen_user(const char __user *s, long n)
+{
+        if (!__addr_ok(s))
+                return 0;
+        else
+                return __strnlen_user(s, n);
+}
+
+/**
+ * strlen_user: - Get the size of a string in user space.
+ * @str: The string to measure.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Get the size of a NUL-terminated string in user space.
+ *
+ * Returns the size of the string INCLUDING the terminating NUL.
+ * On exception, returns 0.
+ *
+ * If there is a limit on the length of a valid string, you may wish to
+ * consider using strnlen_user() instead.
+ */
+#define strlen_user(str)        strnlen_user(str, ~0UL >> 1)
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+struct exception_table_entry {
+        unsigned long insn, fixup;
+};
+
+#if defined(CONFIG_SUPERH64) && defined(CONFIG_MMU)
+#define ARCH_HAS_SEARCH_EXTABLE
+#endif
+
+int fixup_exception(struct pt_regs *regs);
+/* Returns 0 if exception not found and fixup.unit otherwise.  */
+unsigned long search_exception_table(unsigned long addr);
+const struct exception_table_entry *search_exception_tables(unsigned long addr);
+
+
+#endif /* __ASM_SH_UACCESS_H */
diff --git a/arch/sh/include/asm/uaccess_32.h b/arch/sh/include/asm/uaccess_32.h
new file mode 100644
index 000000000000..ae0d24f6653f
--- /dev/null
+++ b/arch/sh/include/asm/uaccess_32.h
@@ -0,0 +1,248 @@
+/*
+ * User space memory access functions
+ *
+ * Copyright (C) 1999, 2002  Niibe Yutaka
+ * Copyright (C) 2003 - 2008  Paul Mundt
+ *
+ *  Based on:
+ *     MIPS implementation version 1.15 by
+ *              Copyright (C) 1996, 1997, 1998 by Ralf Baechle
+ *     and i386 version.
+ */
+#ifndef __ASM_SH_UACCESS_32_H
+#define __ASM_SH_UACCESS_32_H
+
+#define __get_user_size(x,ptr,size,retval)                      \
+do {                                                            \
+        retval = 0;                                             \
+        switch (size) {                                         \
+        case 1:                                                 \
+                __get_user_asm(x, ptr, retval, "b");            \
+                break;                                          \
+        case 2:                                                 \
+                __get_user_asm(x, ptr, retval, "w");            \
+                break;                                          \
+        case 4:                                                 \
+                __get_user_asm(x, ptr, retval, "l");            \
+                break;                                          \
+        default:                                                \
+                __get_user_unknown();                           \
+                break;                                          \
+        }                                                       \
+} while (0)
+
+#ifdef CONFIG_MMU
+#define __get_user_asm(x, addr, err, insn) \
+({ \
+__asm__ __volatile__( \
+        "1:\n\t" \
+        "mov." insn "   %2, %1\n\t" \
+        "2:\n" \
+        ".section       .fixup,\"ax\"\n" \
+        "3:\n\t" \
+        "mov    #0, %1\n\t" \
+        "mov.l  4f, %0\n\t" \
+        "jmp    @%0\n\t" \
+        " mov   %3, %0\n\t" \
+        ".balign        4\n" \
+        "4:     .long   2b\n\t" \
+        ".previous\n" \
+        ".section       __ex_table,\"a\"\n\t" \
+        ".long  1b, 3b\n\t" \
+        ".previous" \
+        :"=&r" (err), "=&r" (x) \
+        :"m" (__m(addr)), "i" (-EFAULT), "0" (err)); })
+#else
+#define __get_user_asm(x, addr, err, insn)              \
+do {                                                    \
+        __asm__ __volatile__ (                          \
+                "mov." insn "   %1, %0\n\t"             \
+                : "=&r" (x)                             \
+                : "m" (__m(addr))                       \
+        );                                              \
+} while (0)
+#endif /* CONFIG_MMU */
+
+extern void __get_user_unknown(void);
+
+#define __put_user_size(x,ptr,size,retval)              \
+do {                                                    \
+        retval = 0;                                     \
+        switch (size) {                                 \
+        case 1:                                         \
+                __put_user_asm(x, ptr, retval, "b");    \
+                break;                                  \
+        case 2:                                         \
+                __put_user_asm(x, ptr, retval, "w");    \
+                break;                                  \
+        case 4:                                         \
+                __put_user_asm(x, ptr, retval, "l");    \
+                break;                                  \
+        case 8:                                         \
+                __put_user_u64(x, ptr, retval);         \
+                break;                                  \
+        default:                                        \
+                __put_user_unknown();                   \
+        }                                               \
+} while (0)
+
+#ifdef CONFIG_MMU
+#define __put_user_asm(x, addr, err, insn)                      \
+do {                                                            \
+        __asm__ __volatile__ (                                  \
+                "1:\n\t"                                        \
+                "mov." insn "   %1, %2\n\t"                     \
+                "2:\n"                                          \
+                ".section       .fixup,\"ax\"\n"                \
+                "3:\n\t"                                        \
+                "mov.l  4f, %0\n\t"                             \
+                "jmp    @%0\n\t"                                \
+                " mov   %3, %0\n\t"                             \
+                ".balign        4\n"                            \
+                "4:     .long   2b\n\t"                         \
+                ".previous\n"                                   \
+                ".section       __ex_table,\"a\"\n\t"           \
+                ".long  1b, 3b\n\t"                             \
+                ".previous"                                     \
+                : "=&r" (err)                                   \
+                : "r" (x), "m" (__m(addr)), "i" (-EFAULT),      \
+                  "0" (err)                                     \
+                : "memory"                                      \
+        );                                                      \
+} while (0)
+#else
+#define __put_user_asm(x, addr, err, insn)              \
+do {                                                    \
+        __asm__ __volatile__ (                          \
+                "mov." insn "   %0, %1\n\t"             \
+                : /* no outputs */                      \
+                : "r" (x), "m" (__m(addr))              \
+                : "memory"                              \
+        );                                              \
+} while (0)
+#endif /* CONFIG_MMU */
+
+#if defined(CONFIG_CPU_LITTLE_ENDIAN)
+#define __put_user_u64(val,addr,retval) \
+({ \
+__asm__ __volatile__( \
+        "1:\n\t" \
+        "mov.l  %R1,%2\n\t" \
+        "mov.l  %S1,%T2\n\t" \
+        "2:\n" \
+        ".section       .fixup,\"ax\"\n" \
+        "3:\n\t" \
+        "mov.l  4f,%0\n\t" \
+        "jmp    @%0\n\t" \
+        " mov   %3,%0\n\t" \
+        ".balign        4\n" \
+        "4:     .long   2b\n\t" \
+        ".previous\n" \
+        ".section       __ex_table,\"a\"\n\t" \
+        ".long  1b, 3b\n\t" \
+        ".previous" \
+        : "=r" (retval) \
+        : "r" (val), "m" (__m(addr)), "i" (-EFAULT), "0" (retval) \
+        : "memory"); })
+#else
+#define __put_user_u64(val,addr,retval) \
+({ \
+__asm__ __volatile__( \
+        "1:\n\t" \
+        "mov.l  %S1,%2\n\t" \
+        "mov.l  %R1,%T2\n\t" \
+        "2:\n" \
+        ".section       .fixup,\"ax\"\n" \
+        "3:\n\t" \
+        "mov.l  4f,%0\n\t" \
+        "jmp    @%0\n\t" \
+        " mov   %3,%0\n\t" \
+        ".balign        4\n" \
+        "4:     .long   2b\n\t" \
+        ".previous\n" \
+        ".section       __ex_table,\"a\"\n\t" \
+        ".long  1b, 3b\n\t" \
+        ".previous" \
+        : "=r" (retval) \
+        : "r" (val), "m" (__m(addr)), "i" (-EFAULT), "0" (retval) \
+        : "memory"); })
+#endif
+
+extern void __put_user_unknown(void);
+
+static inline int
+__strncpy_from_user(unsigned long __dest, unsigned long __user __src, int __count)
+{
+        __kernel_size_t res;
+        unsigned long __dummy, _d, _s, _c;
+
+        __asm__ __volatile__(
+                "9:\n"
+                "mov.b  @%2+, %1\n\t"
+                "cmp/eq #0, %1\n\t"
+                "bt/s   2f\n"
+                "1:\n"
+                "mov.b  %1, @%3\n\t"
+                "dt     %4\n\t"
+                "bf/s   9b\n\t"
+                " add   #1, %3\n\t"
+                "2:\n\t"
+                "sub    %4, %0\n"
+                "3:\n"
+                ".section .fixup,\"ax\"\n"
+                "4:\n\t"
+                "mov.l  5f, %1\n\t"
+                "jmp    @%1\n\t"
+                " mov   %9, %0\n\t"
+                ".balign 4\n"
+                "5:     .long 3b\n"
+                ".previous\n"
+                ".section __ex_table,\"a\"\n"
+                "       .balign 4\n"
+                "       .long 9b,4b\n"
+                ".previous"
+                : "=r" (res), "=&z" (__dummy), "=r" (_s), "=r" (_d), "=r"(_c)
+                : "0" (__count), "2" (__src), "3" (__dest), "4" (__count),
+                  "i" (-EFAULT)
+                : "memory", "t");
+
+        return res;
+}
+
+/*
+ * Return the size of a string (including the ending 0 even when we have
+ * exceeded the maximum string length).
+ */
+static inline long __strnlen_user(const char __user *__s, long __n)
+{
+        unsigned long res;
+        unsigned long __dummy;
+
+        __asm__ __volatile__(
+                "1:\t"
+                "mov.b  @(%0,%3), %1\n\t"
+                "cmp/eq %4, %0\n\t"
+                "bt/s   2f\n\t"
+                " add   #1, %0\n\t"
+                "tst    %1, %1\n\t"
+                "bf     1b\n\t"
+                "2:\n"
+                ".section .fixup,\"ax\"\n"
+                "3:\n\t"
+                "mov.l  4f, %1\n\t"
+                "jmp    @%1\n\t"
+                " mov   #0, %0\n"
+                ".balign 4\n"
+                "4:     .long 2b\n"
+                ".previous\n"
+                ".section __ex_table,\"a\"\n"
+                "       .balign 4\n"
+                "       .long 1b,3b\n"
+                ".previous"
+                : "=z" (res), "=&r" (__dummy)
+                : "0" (0), "r" (__s), "r" (__n)
+                : "t");
+        return res;
+}
+
+#endif /* __ASM_SH_UACCESS_32_H */
diff --git a/arch/sh/include/asm/uaccess_64.h b/arch/sh/include/asm/uaccess_64.h
new file mode 100644
index 000000000000..81b3d515fcb3
--- /dev/null
+++ b/arch/sh/include/asm/uaccess_64.h
@@ -0,0 +1,79 @@
+#ifndef __ASM_SH_UACCESS_64_H
+#define __ASM_SH_UACCESS_64_H
+
+/*
+ * include/asm-sh/uaccess_64.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003, 2004  Paul Mundt
+ *
+ * User space memory access functions
+ *
+ * Copyright (C) 1999  Niibe Yutaka
+ *
+ *  Based on:
+ *     MIPS implementation version 1.15 by
+ *              Copyright (C) 1996, 1997, 1998 by Ralf Baechle
+ *     and i386 version.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#define __get_user_size(x,ptr,size,retval)                      \
+do {                                                            \
+        retval = 0;                                             \
+        switch (size) {                                         \
+        case 1:                                                 \
+                retval = __get_user_asm_b(x, ptr);              \
+                break;                                          \
+        case 2:                                                 \
+                retval = __get_user_asm_w(x, ptr);              \
+                break;                                          \
+        case 4:                                                 \
+                retval = __get_user_asm_l(x, ptr);              \
+                break;                                          \
+        case 8:                                                 \
+                retval = __get_user_asm_q(x, ptr);              \
+                break;                                          \
+        default:                                                \
+                __get_user_unknown();                           \
+                break;                                          \
+        }                                                       \
+} while (0)
+
+extern long __get_user_asm_b(void *, long);
+extern long __get_user_asm_w(void *, long);
+extern long __get_user_asm_l(void *, long);
+extern long __get_user_asm_q(void *, long);
+extern void __get_user_unknown(void);
+
+#define __put_user_size(x,ptr,size,retval)                      \
+do {                                                            \
+        retval = 0;                                             \
+        switch (size) {                                         \
+        case 1:                                                 \
+                retval = __put_user_asm_b(x, ptr);              \
+                break;                                          \
+        case 2:                                                 \
+                retval = __put_user_asm_w(x, ptr);              \
+                break;                                          \
+        case 4:                                                 \
+                retval = __put_user_asm_l(x, ptr);              \
+                break;                                          \
+        case 8:                                                 \
+                retval = __put_user_asm_q(x, ptr);              \
+                break;                                          \
+        default:                                                \
+                __put_user_unknown();                           \
+        }                                                       \
+} while (0)
+
+extern long __put_user_asm_b(void *, long);
+extern long __put_user_asm_w(void *, long);
+extern long __put_user_asm_l(void *, long);
+extern long __put_user_asm_q(void *, long);
+extern void __put_user_unknown(void);
+
+#endif /* __ASM_SH_UACCESS_64_H */
diff --git a/arch/sh/include/asm/ubc.h b/arch/sh/include/asm/ubc.h
new file mode 100644
index 000000000000..a7b9028bbfbb
--- /dev/null
+++ b/arch/sh/include/asm/ubc.h
@@ -0,0 +1,64 @@
+/*
+ * include/asm-sh/ubc.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_UBC_H
+#define __ASM_SH_UBC_H
+#ifdef __KERNEL__
+
+#include <cpu/ubc.h>
+
+/* User Break Controller */
+#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
+#define UBC_TYPE_SH7729 (current_cpu_data.type == CPU_SH7729)
+#else
+#define UBC_TYPE_SH7729 0
+#endif
+
+#define BAMR_ASID               (1 << 2)
+#define BAMR_NONE               0
+#define BAMR_10                 0x1
+#define BAMR_12                 0x2
+#define BAMR_ALL                0x3
+#define BAMR_16                 0x8
+#define BAMR_20                 0x9
+
+#define BBR_INST                (1 << 4)
+#define BBR_DATA                (2 << 4)
+#define BBR_READ                (1 << 2)
+#define BBR_WRITE               (2 << 2)
+#define BBR_BYTE                0x1
+#define BBR_HALF                0x2
+#define BBR_LONG                0x3
+#define BBR_QUAD                (1 << 6)        /* SH7750 */
+#define BBR_CPU                 (1 << 6)        /* SH7709A,SH7729 */
+#define BBR_DMA                 (2 << 6)        /* SH7709A,SH7729 */
+
+#define BRCR_CMFA               (1 << 15)
+#define BRCR_CMFB               (1 << 14)
+#define BRCR_PCTE               (1 << 11)
+#define BRCR_PCBA               (1 << 10)       /* 1: after execution */
+#define BRCR_DBEB               (1 << 7)
+#define BRCR_PCBB               (1 << 6)
+#define BRCR_SEQ                (1 << 3)
+#define BRCR_UBDE               (1 << 0)
+
+#ifndef __ASSEMBLY__
+/* arch/sh/kernel/cpu/ubc.S */
+extern void ubc_sleep(void);
+
+#ifdef CONFIG_UBC_WAKEUP
+extern void ubc_wakeup(void);
+#else
+#define ubc_wakeup()    do { } while (0)
+#endif
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_UBC_H */
diff --git a/arch/sh/include/asm/ucontext.h b/arch/sh/include/asm/ucontext.h
new file mode 100644
index 000000000000..202ef1d5a3c4
--- /dev/null
+++ b/arch/sh/include/asm/ucontext.h
@@ -0,0 +1,12 @@
+#ifndef __ASM_SH_UCONTEXT_H
+#define __ASM_SH_UCONTEXT_H
+
+struct ucontext {
+        unsigned long     uc_flags;
+        struct ucontext  *uc_link;
+        stack_t           uc_stack;
+        struct sigcontext uc_mcontext;
+        sigset_t          uc_sigmask;   /* mask last for extensibility */
+};
+
+#endif /* __ASM_SH_UCONTEXT_H */
diff --git a/arch/sh/include/asm/unaligned.h b/arch/sh/include/asm/unaligned.h
new file mode 100644
index 000000000000..c1641a01d50f
--- /dev/null
+++ b/arch/sh/include/asm/unaligned.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_SH_UNALIGNED_H
+#define _ASM_SH_UNALIGNED_H
+
+/* SH can't handle unaligned accesses. */
+#ifdef __LITTLE_ENDIAN__
+# include <linux/unaligned/le_struct.h>
+# include <linux/unaligned/be_byteshift.h>
+# include <linux/unaligned/generic.h>
+# define get_unaligned  __get_unaligned_le
+# define put_unaligned  __put_unaligned_le
+#else
+# include <linux/unaligned/be_struct.h>
+# include <linux/unaligned/le_byteshift.h>
+# include <linux/unaligned/generic.h>
+# define get_unaligned  __get_unaligned_be
+# define put_unaligned  __put_unaligned_be
+#endif
+
+#endif /* _ASM_SH_UNALIGNED_H */
diff --git a/arch/sh/include/asm/unistd.h b/arch/sh/include/asm/unistd.h
new file mode 100644
index 000000000000..65be656ead7d
--- /dev/null
+++ b/arch/sh/include/asm/unistd.h
@@ -0,0 +1,13 @@
+#ifdef __KERNEL__
+# ifdef CONFIG_SUPERH32
+#  include "unistd_32.h"
+# else
+#  include "unistd_64.h"
+# endif
+#else
+# ifdef __SH5__
+#  include "unistd_64.h"
+# else
+#  include "unistd_32.h"
+# endif
+#endif
diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h
new file mode 100644
index 000000000000..d52c000cf924
--- /dev/null
+++ b/arch/sh/include/asm/unistd_32.h
@@ -0,0 +1,384 @@
+#ifndef __ASM_SH_UNISTD_H
+#define __ASM_SH_UNISTD_H
+
+/*
+ * Copyright (C) 1999  Niibe Yutaka
+ */
+
+/*
+ * This file contains the system call numbers.
+ */
+
+#define __NR_restart_syscall      0
+#define __NR_exit                 1
+#define __NR_fork                 2
+#define __NR_read                 3
+#define __NR_write                4
+#define __NR_open                 5
+#define __NR_close                6
+#define __NR_waitpid              7
+#define __NR_creat                8
+#define __NR_link                 9
+#define __NR_unlink              10
+#define __NR_execve              11
+#define __NR_chdir               12
+#define __NR_time                13
+#define __NR_mknod               14
+#define __NR_chmod               15
+#define __NR_lchown              16
+#define __NR_break               17
+#define __NR_oldstat             18
+#define __NR_lseek               19
+#define __NR_getpid              20
+#define __NR_mount               21
+#define __NR_umount              22
+#define __NR_setuid              23
+#define __NR_getuid              24
+#define __NR_stime               25
+#define __NR_ptrace              26
+#define __NR_alarm               27
+#define __NR_oldfstat            28
+#define __NR_pause               29
+#define __NR_utime               30
+#define __NR_stty                31
+#define __NR_gtty                32
+#define __NR_access              33
+#define __NR_nice                34
+#define __NR_ftime               35
+#define __NR_sync                36
+#define __NR_kill                37
+#define __NR_rename              38
+#define __NR_mkdir               39
+#define __NR_rmdir               40
+#define __NR_dup                 41
+#define __NR_pipe                42
+#define __NR_times               43
+#define __NR_prof                44
+#define __NR_brk                 45
+#define __NR_setgid              46
+#define __NR_getgid              47
+#define __NR_signal              48
+#define __NR_geteuid             49
+#define __NR_getegid             50
+#define __NR_acct                51
+#define __NR_umount2             52
+#define __NR_lock                53
+#define __NR_ioctl               54
+#define __NR_fcntl               55
+#define __NR_mpx                 56
+#define __NR_setpgid             57
+#define __NR_ulimit              58
+#define __NR_oldolduname         59
+#define __NR_umask               60
+#define __NR_chroot              61
+#define __NR_ustat               62
+#define __NR_dup2                63
+#define __NR_getppid             64
+#define __NR_getpgrp             65
+#define __NR_setsid              66
+#define __NR_sigaction           67
+#define __NR_sgetmask            68
+#define __NR_ssetmask            69
+#define __NR_setreuid            70
+#define __NR_setregid            71
+#define __NR_sigsuspend          72
+#define __NR_sigpending          73
+#define __NR_sethostname         74
+#define __NR_setrlimit           75
+#define __NR_getrlimit           76     /* Back compatible 2Gig limited rlimit */
+#define __NR_getrusage           77
+#define __NR_gettimeofday        78
+#define __NR_settimeofday        79
+#define __NR_getgroups           80
+#define __NR_setgroups           81
+#define __NR_select              82
+#define __NR_symlink             83
+#define __NR_oldlstat            84
+#define __NR_readlink            85
+#define __NR_uselib              86
+#define __NR_swapon              87
+#define __NR_reboot              88
+#define __NR_readdir             89
+#define __NR_mmap                90
+#define __NR_munmap              91
+#define __NR_truncate            92
+#define __NR_ftruncate           93
+#define __NR_fchmod              94
+#define __NR_fchown              95
+#define __NR_getpriority         96
+#define __NR_setpriority         97
+#define __NR_profil              98
+#define __NR_statfs              99
+#define __NR_fstatfs            100
+#define __NR_ioperm             101
+#define __NR_socketcall         102
+#define __NR_syslog             103
+#define __NR_setitimer          104
+#define __NR_getitimer          105
+#define __NR_stat               106
+#define __NR_lstat              107
+#define __NR_fstat              108
+#define __NR_olduname           109
+#define __NR_iopl               110
+#define __NR_vhangup            111
+#define __NR_idle               112
+#define __NR_vm86old            113
+#define __NR_wait4              114
+#define __NR_swapoff            115
+#define __NR_sysinfo            116
+#define __NR_ipc                117
+#define __NR_fsync              118
+#define __NR_sigreturn          119
+#define __NR_clone              120
+#define __NR_setdomainname      121
+#define __NR_uname              122
+#define __NR_modify_ldt         123
+#define __NR_adjtimex           124
+#define __NR_mprotect           125
+#define __NR_sigprocmask        126
+#define __NR_create_module      127
+#define __NR_init_module        128
+#define __NR_delete_module      129
+#define __NR_get_kernel_syms    130
+#define __NR_quotactl           131
+#define __NR_getpgid            132
+#define __NR_fchdir             133
+#define __NR_bdflush            134
+#define __NR_sysfs              135
+#define __NR_personality        136
+#define __NR_afs_syscall        137 /* Syscall for Andrew File System */
+#define __NR_setfsuid           138
+#define __NR_setfsgid           139
+#define __NR__llseek            140
+#define __NR_getdents           141
+#define __NR__newselect         142
+#define __NR_flock              143
+#define __NR_msync              144
+#define __NR_readv              145
+#define __NR_writev             146
+#define __NR_getsid             147
+#define __NR_fdatasync          148
+#define __NR__sysctl            149
+#define __NR_mlock              150
+#define __NR_munlock            151
+#define __NR_mlockall           152
+#define __NR_munlockall         153
+#define __NR_sched_setparam             154
+#define __NR_sched_getparam             155
+#define __NR_sched_setscheduler         156
+#define __NR_sched_getscheduler         157
+#define __NR_sched_yield                158
+#define __NR_sched_get_priority_max     159
+#define __NR_sched_get_priority_min     160
+#define __NR_sched_rr_get_interval      161
+#define __NR_nanosleep          162
+#define __NR_mremap             163
+#define __NR_setresuid          164
+#define __NR_getresuid          165
+#define __NR_vm86               166
+#define __NR_query_module       167
+#define __NR_poll               168
+#define __NR_nfsservctl         169
+#define __NR_setresgid          170
+#define __NR_getresgid          171
+#define __NR_prctl              172
+#define __NR_rt_sigreturn       173
+#define __NR_rt_sigaction       174
+#define __NR_rt_sigprocmask     175
+#define __NR_rt_sigpending      176
+#define __NR_rt_sigtimedwait    177
+#define __NR_rt_sigqueueinfo    178
+#define __NR_rt_sigsuspend      179
+#define __NR_pread64            180
+#define __NR_pwrite64           181
+#define __NR_chown              182
+#define __NR_getcwd             183
+#define __NR_capget             184
+#define __NR_capset             185
+#define __NR_sigaltstack        186
+#define __NR_sendfile           187
+#define __NR_streams1           188     /* some people actually want it */
+#define __NR_streams2           189     /* some people actually want it */
+#define __NR_vfork              190
+#define __NR_ugetrlimit         191     /* SuS compliant getrlimit */
+#define __NR_mmap2              192
+#define __NR_truncate64         193
+#define __NR_ftruncate64        194
+#define __NR_stat64             195
+#define __NR_lstat64            196
+#define __NR_fstat64            197
+#define __NR_lchown32           198
+#define __NR_getuid32           199
+#define __NR_getgid32           200
+#define __NR_geteuid32          201
+#define __NR_getegid32          202
+#define __NR_setreuid32         203
+#define __NR_setregid32         204
+#define __NR_getgroups32        205
+#define __NR_setgroups32        206
+#define __NR_fchown32           207
+#define __NR_setresuid32        208
+#define __NR_getresuid32        209
+#define __NR_setresgid32        210
+#define __NR_getresgid32        211
+#define __NR_chown32            212
+#define __NR_setuid32           213
+#define __NR_setgid32           214
+#define __NR_setfsuid32         215
+#define __NR_setfsgid32         216
+#define __NR_pivot_root         217
+#define __NR_mincore            218
+#define __NR_madvise            219
+#define __NR_getdents64         220
+#define __NR_fcntl64            221
+/* 223 is unused */
+#define __NR_gettid             224
+#define __NR_readahead          225
+#define __NR_setxattr           226
+#define __NR_lsetxattr          227
+#define __NR_fsetxattr          228
+#define __NR_getxattr           229
+#define __NR_lgetxattr          230
+#define __NR_fgetxattr          231
+#define __NR_listxattr          232
+#define __NR_llistxattr         233
+#define __NR_flistxattr         234
+#define __NR_removexattr        235
+#define __NR_lremovexattr       236
+#define __NR_fremovexattr       237
+#define __NR_tkill              238
+#define __NR_sendfile64         239
+#define __NR_futex              240
+#define __NR_sched_setaffinity  241
+#define __NR_sched_getaffinity  242
+#define __NR_set_thread_area    243
+#define __NR_get_thread_area    244
+#define __NR_io_setup           245
+#define __NR_io_destroy         246
+#define __NR_io_getevents       247
+#define __NR_io_submit          248
+#define __NR_io_cancel          249
+#define __NR_fadvise64          250
+
+#define __NR_exit_group         252
+#define __NR_lookup_dcookie     253
+#define __NR_epoll_create       254
+#define __NR_epoll_ctl          255
+#define __NR_epoll_wait         256
+#define __NR_remap_file_pages   257
+#define __NR_set_tid_address    258
+#define __NR_timer_create       259
+#define __NR_timer_settime      (__NR_timer_create+1)
+#define __NR_timer_gettime      (__NR_timer_create+2)
+#define __NR_timer_getoverrun   (__NR_timer_create+3)
+#define __NR_timer_delete       (__NR_timer_create+4)
+#define __NR_clock_settime      (__NR_timer_create+5)
+#define __NR_clock_gettime      (__NR_timer_create+6)
+#define __NR_clock_getres       (__NR_timer_create+7)
+#define __NR_clock_nanosleep    (__NR_timer_create+8)
+#define __NR_statfs64           268
+#define __NR_fstatfs64          269
+#define __NR_tgkill             270
+#define __NR_utimes             271
+#define __NR_fadvise64_64       272
+#define __NR_vserver            273
+#define __NR_mbind              274
+#define __NR_get_mempolicy      275
+#define __NR_set_mempolicy      276
+#define __NR_mq_open            277
+#define __NR_mq_unlink          (__NR_mq_open+1)
+#define __NR_mq_timedsend       (__NR_mq_open+2)
+#define __NR_mq_timedreceive    (__NR_mq_open+3)
+#define __NR_mq_notify          (__NR_mq_open+4)
+#define __NR_mq_getsetattr      (__NR_mq_open+5)
+#define __NR_kexec_load         283
+#define __NR_waitid             284
+#define __NR_add_key            285
+#define __NR_request_key        286
+#define __NR_keyctl             287
+#define __NR_ioprio_set         288
+#define __NR_ioprio_get         289
+#define __NR_inotify_init       290
+#define __NR_inotify_add_watch  291
+#define __NR_inotify_rm_watch   292
+/* 293 is unused */
+#define __NR_migrate_pages      294
+#define __NR_openat             295
+#define __NR_mkdirat            296
+#define __NR_mknodat            297
+#define __NR_fchownat           298
+#define __NR_futimesat          299
+#define __NR_fstatat64          300
+#define __NR_unlinkat           301
+#define __NR_renameat           302
+#define __NR_linkat             303
+#define __NR_symlinkat          304
+#define __NR_readlinkat         305
+#define __NR_fchmodat           306
+#define __NR_faccessat          307
+#define __NR_pselect6           308
+#define __NR_ppoll              309
+#define __NR_unshare            310
+#define __NR_set_robust_list    311
+#define __NR_get_robust_list    312
+#define __NR_splice             313
+#define __NR_sync_file_range    314
+#define __NR_tee                315
+#define __NR_vmsplice           316
+#define __NR_move_pages         317
+#define __NR_getcpu             318
+#define __NR_epoll_pwait        319
+#define __NR_utimensat          320
+#define __NR_signalfd           321
+#define __NR_timerfd_create     322
+#define __NR_eventfd            323
+#define __NR_fallocate          324
+#define __NR_timerfd_settime    325
+#define __NR_timerfd_gettime    326
+#define __NR_signalfd4          327
+#define __NR_eventfd2           328
+#define __NR_epoll_create1      329
+#define __NR_dup3               330
+#define __NR_pipe2              331
+#define __NR_inotify_init1      332
+
+#define NR_syscalls 333
+
+#ifdef __KERNEL__
+
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_OLD_STAT
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SGETMASK
+#define __ARCH_WANT_SYS_SIGNAL
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_WAITPID
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLD_GETRLIMIT
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_RT_SIGACTION
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#ifndef cond_syscall
+#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_UNISTD_H */
diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h
new file mode 100644
index 000000000000..7c54e91753c1
--- /dev/null
+++ b/arch/sh/include/asm/unistd_64.h
@@ -0,0 +1,423 @@
+#ifndef __ASM_SH_UNISTD_64_H
+#define __ASM_SH_UNISTD_64_H
+
+/*
+ * include/asm-sh/unistd_64.h
+ *
+ * This file contains the system call numbers.
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003 - 2007 Paul Mundt
+ * Copyright (C) 2004  Sean McGoogan
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#define __NR_restart_syscall      0
+#define __NR_exit                 1
+#define __NR_fork                 2
+#define __NR_read                 3
+#define __NR_write                4
+#define __NR_open                 5
+#define __NR_close                6
+#define __NR_waitpid              7
+#define __NR_creat                8
+#define __NR_link                 9
+#define __NR_unlink              10
+#define __NR_execve              11
+#define __NR_chdir               12
+#define __NR_time                13
+#define __NR_mknod               14
+#define __NR_chmod               15
+#define __NR_lchown              16
+#define __NR_break               17
+#define __NR_oldstat             18
+#define __NR_lseek               19
+#define __NR_getpid              20
+#define __NR_mount               21
+#define __NR_umount              22
+#define __NR_setuid              23
+#define __NR_getuid              24
+#define __NR_stime               25
+#define __NR_ptrace              26
+#define __NR_alarm               27
+#define __NR_oldfstat            28
+#define __NR_pause               29
+#define __NR_utime               30
+#define __NR_stty                31
+#define __NR_gtty                32
+#define __NR_access              33
+#define __NR_nice                34
+#define __NR_ftime               35
+#define __NR_sync                36
+#define __NR_kill                37
+#define __NR_rename              38
+#define __NR_mkdir               39
+#define __NR_rmdir               40
+#define __NR_dup                 41
+#define __NR_pipe                42
+#define __NR_times               43
+#define __NR_prof                44
+#define __NR_brk                 45
+#define __NR_setgid              46
+#define __NR_getgid              47
+#define __NR_signal              48
+#define __NR_geteuid             49
+#define __NR_getegid             50
+#define __NR_acct                51
+#define __NR_umount2             52
+#define __NR_lock                53
+#define __NR_ioctl               54
+#define __NR_fcntl               55
+#define __NR_mpx                 56
+#define __NR_setpgid             57
+#define __NR_ulimit              58
+#define __NR_oldolduname         59
+#define __NR_umask               60
+#define __NR_chroot              61
+#define __NR_ustat               62
+#define __NR_dup2                63
+#define __NR_getppid             64
+#define __NR_getpgrp             65
+#define __NR_setsid              66
+#define __NR_sigaction           67
+#define __NR_sgetmask            68
+#define __NR_ssetmask            69
+#define __NR_setreuid            70
+#define __NR_setregid            71
+#define __NR_sigsuspend          72
+#define __NR_sigpending          73
+#define __NR_sethostname         74
+#define __NR_setrlimit           75
+#define __NR_getrlimit           76     /* Back compatible 2Gig limited rlimit */
+#define __NR_getrusage           77
+#define __NR_gettimeofday        78
+#define __NR_settimeofday        79
+#define __NR_getgroups           80
+#define __NR_setgroups           81
+#define __NR_select              82
+#define __NR_symlink             83
+#define __NR_oldlstat            84
+#define __NR_readlink            85
+#define __NR_uselib              86
+#define __NR_swapon              87
+#define __NR_reboot              88
+#define __NR_readdir             89
+#define __NR_mmap                90
+#define __NR_munmap              91
+#define __NR_truncate            92
+#define __NR_ftruncate           93
+#define __NR_fchmod              94
+#define __NR_fchown              95
+#define __NR_getpriority         96
+#define __NR_setpriority         97
+#define __NR_profil              98
+#define __NR_statfs              99
+#define __NR_fstatfs            100
+#define __NR_ioperm             101
+#define __NR_socketcall         102     /* old implementation of socket systemcall */
+#define __NR_syslog             103
+#define __NR_setitimer          104
+#define __NR_getitimer          105
+#define __NR_stat               106
+#define __NR_lstat              107
+#define __NR_fstat              108
+#define __NR_olduname           109
+#define __NR_iopl               110
+#define __NR_vhangup            111
+#define __NR_idle               112
+#define __NR_vm86old            113
+#define __NR_wait4              114
+#define __NR_swapoff            115
+#define __NR_sysinfo            116
+#define __NR_ipc                117
+#define __NR_fsync              118
+#define __NR_sigreturn          119
+#define __NR_clone              120
+#define __NR_setdomainname      121
+#define __NR_uname              122
+#define __NR_modify_ldt         123
+#define __NR_adjtimex           124
+#define __NR_mprotect           125
+#define __NR_sigprocmask        126
+#define __NR_create_module      127
+#define __NR_init_module        128
+#define __NR_delete_module      129
+#define __NR_get_kernel_syms    130
+#define __NR_quotactl           131
+#define __NR_getpgid            132
+#define __NR_fchdir             133
+#define __NR_bdflush            134
+#define __NR_sysfs              135
+#define __NR_personality        136
+#define __NR_afs_syscall        137 /* Syscall for Andrew File System */
+#define __NR_setfsuid           138
+#define __NR_setfsgid           139
+#define __NR__llseek            140
+#define __NR_getdents           141
+#define __NR__newselect         142
+#define __NR_flock              143
+#define __NR_msync              144
+#define __NR_readv              145
+#define __NR_writev             146
+#define __NR_getsid             147
+#define __NR_fdatasync          148
+#define __NR__sysctl            149
+#define __NR_mlock              150
+#define __NR_munlock            151
+#define __NR_mlockall           152
+#define __NR_munlockall         153
+#define __NR_sched_setparam             154
+#define __NR_sched_getparam             155
+#define __NR_sched_setscheduler         156
+#define __NR_sched_getscheduler         157
+#define __NR_sched_yield                158
+#define __NR_sched_get_priority_max     159
+#define __NR_sched_get_priority_min     160
+#define __NR_sched_rr_get_interval      161
+#define __NR_nanosleep          162
+#define __NR_mremap             163
+#define __NR_setresuid          164
+#define __NR_getresuid          165
+#define __NR_vm86               166
+#define __NR_query_module       167
+#define __NR_poll               168
+#define __NR_nfsservctl         169
+#define __NR_setresgid          170
+#define __NR_getresgid          171
+#define __NR_prctl              172
+#define __NR_rt_sigreturn       173
+#define __NR_rt_sigaction       174
+#define __NR_rt_sigprocmask     175
+#define __NR_rt_sigpending      176
+#define __NR_rt_sigtimedwait    177
+#define __NR_rt_sigqueueinfo    178
+#define __NR_rt_sigsuspend      179
+#define __NR_pread64            180
+#define __NR_pwrite64           181
+#define __NR_chown              182
+#define __NR_getcwd             183
+#define __NR_capget             184
+#define __NR_capset             185
+#define __NR_sigaltstack        186
+#define __NR_sendfile           187
+#define __NR_streams1           188     /* some people actually want it */
+#define __NR_streams2           189     /* some people actually want it */
+#define __NR_vfork              190
+#define __NR_ugetrlimit         191     /* SuS compliant getrlimit */
+#define __NR_mmap2              192
+#define __NR_truncate64         193
+#define __NR_ftruncate64        194
+#define __NR_stat64             195
+#define __NR_lstat64            196
+#define __NR_fstat64            197
+#define __NR_lchown32           198
+#define __NR_getuid32           199
+#define __NR_getgid32           200
+#define __NR_geteuid32          201
+#define __NR_getegid32          202
+#define __NR_setreuid32         203
+#define __NR_setregid32         204
+#define __NR_getgroups32        205
+#define __NR_setgroups32        206
+#define __NR_fchown32           207
+#define __NR_setresuid32        208
+#define __NR_getresuid32        209
+#define __NR_setresgid32        210
+#define __NR_getresgid32        211
+#define __NR_chown32            212
+#define __NR_setuid32           213
+#define __NR_setgid32           214
+#define __NR_setfsuid32         215
+#define __NR_setfsgid32         216
+#define __NR_pivot_root         217
+#define __NR_mincore            218
+#define __NR_madvise            219
+
+/* Non-multiplexed socket family */
+#define __NR_socket             220
+#define __NR_bind               221
+#define __NR_connect            222
+#define __NR_listen             223
+#define __NR_accept             224
+#define __NR_getsockname        225
+#define __NR_getpeername        226
+#define __NR_socketpair         227
+#define __NR_send               228
+#define __NR_sendto             229
+#define __NR_recv               230
+#define __NR_recvfrom           231
+#define __NR_shutdown           232
+#define __NR_setsockopt         233
+#define __NR_getsockopt         234
+#define __NR_sendmsg            235
+#define __NR_recvmsg            236
+
+/* Non-multiplexed IPC family */
+#define __NR_semop              237
+#define __NR_semget             238
+#define __NR_semctl             239
+#define __NR_msgsnd             240
+#define __NR_msgrcv             241
+#define __NR_msgget             242
+#define __NR_msgctl             243
+#if 0
+#define __NR_shmatcall          244
+#endif
+#define __NR_shmdt              245
+#define __NR_shmget             246
+#define __NR_shmctl             247
+
+#define __NR_getdents64         248
+#define __NR_fcntl64            249
+/* 223 is unused */
+#define __NR_gettid             252
+#define __NR_readahead          253
+#define __NR_setxattr           254
+#define __NR_lsetxattr          255
+#define __NR_fsetxattr          256
+#define __NR_getxattr           257
+#define __NR_lgetxattr          258
+#define __NR_fgetxattr          269
+#define __NR_listxattr          260
+#define __NR_llistxattr         261
+#define __NR_flistxattr         262
+#define __NR_removexattr        263
+#define __NR_lremovexattr       264
+#define __NR_fremovexattr       265
+#define __NR_tkill              266
+#define __NR_sendfile64         267
+#define __NR_futex              268
+#define __NR_sched_setaffinity  269
+#define __NR_sched_getaffinity  270
+#define __NR_set_thread_area    271
+#define __NR_get_thread_area    272
+#define __NR_io_setup           273
+#define __NR_io_destroy         274
+#define __NR_io_getevents       275
+#define __NR_io_submit          276
+#define __NR_io_cancel          277
+#define __NR_fadvise64          278
+#define __NR_exit_group         280
+
+#define __NR_lookup_dcookie     281
+#define __NR_epoll_create       282
+#define __NR_epoll_ctl          283
+#define __NR_epoll_wait         284
+#define __NR_remap_file_pages   285
+#define __NR_set_tid_address    286
+#define __NR_timer_create       287
+#define __NR_timer_settime      (__NR_timer_create+1)
+#define __NR_timer_gettime      (__NR_timer_create+2)
+#define __NR_timer_getoverrun   (__NR_timer_create+3)
+#define __NR_timer_delete       (__NR_timer_create+4)
+#define __NR_clock_settime      (__NR_timer_create+5)
+#define __NR_clock_gettime      (__NR_timer_create+6)
+#define __NR_clock_getres       (__NR_timer_create+7)
+#define __NR_clock_nanosleep    (__NR_timer_create+8)
+#define __NR_statfs64           296
+#define __NR_fstatfs64          297
+#define __NR_tgkill             298
+#define __NR_utimes             299
+#define __NR_fadvise64_64       300
+#define __NR_vserver            301
+#define __NR_mbind              302
+#define __NR_get_mempolicy      303
+#define __NR_set_mempolicy      304
+#define __NR_mq_open            305
+#define __NR_mq_unlink          (__NR_mq_open+1)
+#define __NR_mq_timedsend       (__NR_mq_open+2)
+#define __NR_mq_timedreceive    (__NR_mq_open+3)
+#define __NR_mq_notify          (__NR_mq_open+4)
+#define __NR_mq_getsetattr      (__NR_mq_open+5)
+#define __NR_kexec_load         311
+#define __NR_waitid             312
+#define __NR_add_key            313
+#define __NR_request_key        314
+#define __NR_keyctl             315
+#define __NR_ioprio_set         316
+#define __NR_ioprio_get         317
+#define __NR_inotify_init       318
+#define __NR_inotify_add_watch  319
+#define __NR_inotify_rm_watch   320
+/* 321 is unused */
+#define __NR_migrate_pages      322
+#define __NR_openat             323
+#define __NR_mkdirat            324
+#define __NR_mknodat            325
+#define __NR_fchownat           326
+#define __NR_futimesat          327
+#define __NR_fstatat64          328
+#define __NR_unlinkat           329
+#define __NR_renameat           330
+#define __NR_linkat             331
+#define __NR_symlinkat          332
+#define __NR_readlinkat         333
+#define __NR_fchmodat           334
+#define __NR_faccessat          335
+#define __NR_pselect6           336
+#define __NR_ppoll              337
+#define __NR_unshare            338
+#define __NR_set_robust_list    339
+#define __NR_get_robust_list    340
+#define __NR_splice             341
+#define __NR_sync_file_range    342
+#define __NR_tee                343
+#define __NR_vmsplice           344
+#define __NR_move_pages         345
+#define __NR_getcpu             346
+#define __NR_epoll_pwait        347
+#define __NR_utimensat          348
+#define __NR_signalfd           349
+#define __NR_timerfd_create     350
+#define __NR_eventfd            351
+#define __NR_fallocate          352
+#define __NR_timerfd_settime    353
+#define __NR_timerfd_gettime    354
+#define __NR_signalfd4          355
+#define __NR_eventfd2           356
+#define __NR_epoll_create1      357
+#define __NR_dup3               358
+#define __NR_pipe2              359
+#define __NR_inotify_init1      360
+
+#ifdef __KERNEL__
+
+#define NR_syscalls 361
+
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_OLD_STAT
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SGETMASK
+#define __ARCH_WANT_SYS_SIGNAL
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_WAITPID
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLD_GETRLIMIT
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_RT_SIGACTION
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#ifndef cond_syscall
+#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_UNISTD_64_H */
diff --git a/arch/sh/include/asm/user.h b/arch/sh/include/asm/user.h
new file mode 100644
index 000000000000..8fd3cf6c58d4
--- /dev/null
+++ b/arch/sh/include/asm/user.h
@@ -0,0 +1,67 @@
+#ifndef __ASM_SH_USER_H
+#define __ASM_SH_USER_H
+
+#include <asm/ptrace.h>
+#include <asm/page.h>
+
+/*
+ * Core file format: The core file is written in such a way that gdb
+ * can understand it and provide useful information to the user (under
+ * linux we use the `trad-core' bfd).  The file contents are as follows:
+ *
+ *  upage: 1 page consisting of a user struct that tells gdb
+ *      what is present in the file.  Directly after this is a
+ *      copy of the task_struct, which is currently not used by gdb,
+ *      but it may come in handy at some point.  All of the registers
+ *      are stored as part of the upage.  The upage should always be
+ *      only one page long.
+ *  data: The data segment follows next.  We use current->end_text to
+ *      current->brk to pick up all of the user variables, plus any memory
+ *      that may have been sbrk'ed.  No attempt is made to determine if a
+ *      page is demand-zero or if a page is totally unused, we just cover
+ *      the entire range.  All of the addresses are rounded in such a way
+ *      that an integral number of pages is written.
+ *  stack: We need the stack information in order to get a meaningful
+ *      backtrace.  We need to write the data from usp to
+ *      current->start_stack, so we round each of these in order to be able
+ *      to write an integer number of pages.
+ */
+
+#if defined(__SH5__) || defined(CONFIG_CPU_SH5)
+struct user_fpu_struct {
+        unsigned long fp_regs[32];
+        unsigned int fpscr;
+};
+#else
+struct user_fpu_struct {
+        unsigned long fp_regs[16];
+        unsigned long xfp_regs[16];
+        unsigned long fpscr;
+        unsigned long fpul;
+};
+#endif
+
+struct user {
+        struct pt_regs  regs;                   /* entire machine state */
+        struct user_fpu_struct fpu;     /* Math Co-processor registers  */
+        int u_fpvalid;          /* True if math co-processor being used */
+        size_t          u_tsize;                /* text size (pages) */
+        size_t          u_dsize;                /* data size (pages) */
+        size_t          u_ssize;                /* stack size (pages) */
+        unsigned long   start_code;             /* text starting address */
+        unsigned long   start_data;             /* data starting address */
+        unsigned long   start_stack;            /* stack starting address */
+        long int        signal;                 /* signal causing core dump */
+        unsigned long   u_ar0;                  /* help gdb find registers */
+        struct user_fpu_struct* u_fpstate;      /* Math Co-processor pointer */
+        unsigned long   magic;                  /* identifies a core file */
+        char            u_comm[32];             /* user command name */
+};
+
+#define NBPG                    PAGE_SIZE
+#define UPAGES                  1
+#define HOST_TEXT_START_ADDR    (u.start_code)
+#define HOST_DATA_START_ADDR    (u.start_data)
+#define HOST_STACK_END_ADDR     (u.start_stack + u.u_ssize * NBPG)
+
+#endif /* __ASM_SH_USER_H */
diff --git a/arch/sh/include/asm/vga.h b/arch/sh/include/asm/vga.h
new file mode 100644
index 000000000000..06a5de8ace1a
--- /dev/null
+++ b/arch/sh/include/asm/vga.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SH_VGA_H
+#define __ASM_SH_VGA_H
+
+/* Stupid drivers. */
+
+#endif /* __ASM_SH_VGA_H */
diff --git a/arch/sh/include/asm/watchdog.h b/arch/sh/include/asm/watchdog.h
new file mode 100644
index 000000000000..f024fed00a72
--- /dev/null
+++ b/arch/sh/include/asm/watchdog.h
@@ -0,0 +1,107 @@
+/*
+ * include/asm-sh/watchdog.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __ASM_SH_WATCHDOG_H
+#define __ASM_SH_WATCHDOG_H
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <cpu/watchdog.h>
+#include <asm/io.h>
+
+/* 
+ * See cpu-sh2/watchdog.h for explanation of this stupidity..
+ */
+#ifndef WTCNT_R
+#  define WTCNT_R       WTCNT
+#endif
+
+#ifndef WTCSR_R
+#  define WTCSR_R       WTCSR
+#endif
+
+#define WTCNT_HIGH      0x5a
+#define WTCSR_HIGH      0xa5
+
+#define WTCSR_CKS2      0x04
+#define WTCSR_CKS1      0x02
+#define WTCSR_CKS0      0x01
+
+/*
+ * CKS0-2 supports a number of clock division ratios. At the time the watchdog
+ * is enabled, it defaults to a 41 usec overflow period .. we overload this to
+ * something a little more reasonable, and really can't deal with anything
+ * lower than WTCSR_CKS_1024, else we drop back into the usec range.
+ *
+ * Clock Division Ratio         Overflow Period
+ * --------------------------------------------
+ *     1/32 (initial value)       41 usecs
+ *     1/64                       82 usecs
+ *     1/128                     164 usecs
+ *     1/256                     328 usecs
+ *     1/512                     656 usecs
+ *     1/1024                   1.31 msecs
+ *     1/2048                   2.62 msecs
+ *     1/4096                   5.25 msecs
+ */
+#define WTCSR_CKS_32    0x00
+#define WTCSR_CKS_64    0x01
+#define WTCSR_CKS_128   0x02
+#define WTCSR_CKS_256   0x03
+#define WTCSR_CKS_512   0x04
+#define WTCSR_CKS_1024  0x05
+#define WTCSR_CKS_2048  0x06
+#define WTCSR_CKS_4096  0x07
+
+/**
+ *      sh_wdt_read_cnt - Read from Counter
+ *      Reads back the WTCNT value.
+ */
+static inline __u8 sh_wdt_read_cnt(void)
+{
+        return ctrl_inb(WTCNT_R);
+}
+
+/**
+ *      sh_wdt_write_cnt - Write to Counter
+ *      @val: Value to write
+ *
+ *      Writes the given value @val to the lower byte of the timer counter.
+ *      The upper byte is set manually on each write.
+ */
+static inline void sh_wdt_write_cnt(__u8 val)
+{
+        ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, WTCNT);
+}
+
+/**
+ *      sh_wdt_read_csr - Read from Control/Status Register
+ *
+ *      Reads back the WTCSR value.
+ */
+static inline __u8 sh_wdt_read_csr(void)
+{
+        return ctrl_inb(WTCSR_R);
+}
+
+/**
+ *      sh_wdt_write_csr - Write to Control/Status Register
+ *      @val: Value to write
+ *
+ *      Writes the given value @val to the lower byte of the control/status
+ *      register. The upper byte is set manually on each write.
+ */
+static inline void sh_wdt_write_csr(__u8 val)
+{
+        ctrl_outw((WTCSR_HIGH << 8) | (__u16)val, WTCSR);
+}
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_WATCHDOG_H */
diff --git a/arch/sh/include/asm/xor.h b/arch/sh/include/asm/xor.h
new file mode 100644
index 000000000000..c82eb12a5b18
--- /dev/null
+++ b/arch/sh/include/asm/xor.h
@@ -0,0 +1 @@
+#include <asm-generic/xor.h>
diff --git a/arch/sh/include/cpu-common/cpu/addrspace.h b/arch/sh/include/cpu-common/cpu/addrspace.h
new file mode 100644
index 000000000000..2b9ab93efa4e
--- /dev/null
+++ b/arch/sh/include/cpu-common/cpu/addrspace.h
@@ -0,0 +1,19 @@
+/*
+ * Definitions for the address spaces of the SH-2 CPUs.
+ *
+ * Copyright (C) 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_ADDRSPACE_H
+#define __ASM_CPU_SH2_ADDRSPACE_H
+
+#define P0SEG           0x00000000
+#define P1SEG           0x80000000
+#define P2SEG           0xa0000000
+#define P3SEG           0xc0000000
+#define P4SEG           0xe0000000
+
+#endif /* __ASM_CPU_SH2_ADDRSPACE_H */
diff --git a/arch/sh/include/cpu-common/cpu/cacheflush.h b/arch/sh/include/cpu-common/cpu/cacheflush.h
new file mode 100644
index 000000000000..c3db00b73605
--- /dev/null
+++ b/arch/sh/include/cpu-common/cpu/cacheflush.h
@@ -0,0 +1,44 @@
+/*
+ * include/asm-sh/cpu-sh2/cacheflush.h
+ *
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_CACHEFLUSH_H
+#define __ASM_CPU_SH2_CACHEFLUSH_H
+
+/*
+ * Cache flushing:
+ *
+ *  - flush_cache_all() flushes entire cache
+ *  - flush_cache_mm(mm) flushes the specified mm context's cache lines
+ *  - flush_cache_dup mm(mm) handles cache flushing when forking
+ *  - flush_cache_page(mm, vmaddr, pfn) flushes a single page
+ *  - flush_cache_range(vma, start, end) flushes a range of pages
+ *
+ *  - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
+ *  - flush_icache_range(start, end) flushes(invalidates) a range for icache
+ *  - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
+ *
+ *  Caches are indexed (effectively) by physical address on SH-2, so
+ *  we don't need them.
+ */
+#define flush_cache_all()                       do { } while (0)
+#define flush_cache_mm(mm)                      do { } while (0)
+#define flush_cache_dup_mm(mm)                  do { } while (0)
+#define flush_cache_range(vma, start, end)      do { } while (0)
+#define flush_cache_page(vma, vmaddr, pfn)      do { } while (0)
+#define flush_dcache_page(page)                 do { } while (0)
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+#define flush_icache_range(start, end)          do { } while (0)
+#define flush_icache_page(vma,pg)               do { } while (0)
+#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
+#define flush_cache_sigtramp(vaddr)             do { } while (0)
+
+#define p3_cache_init()                         do { } while (0)
+
+#endif /* __ASM_CPU_SH2_CACHEFLUSH_H */
diff --git a/arch/sh/include/cpu-common/cpu/mmu_context.h b/arch/sh/include/cpu-common/cpu/mmu_context.h
new file mode 100644
index 000000000000..beeb299e01ec
--- /dev/null
+++ b/arch/sh/include/cpu-common/cpu/mmu_context.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-sh/cpu-sh2/mmu_context.h
+ *
+ * Copyright (C) 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_MMU_CONTEXT_H
+#define __ASM_CPU_SH2_MMU_CONTEXT_H
+
+/* No MMU */
+
+#endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */
+
diff --git a/arch/sh/include/cpu-common/cpu/rtc.h b/arch/sh/include/cpu-common/cpu/rtc.h
new file mode 100644
index 000000000000..39e2d6e94782
--- /dev/null
+++ b/arch/sh/include/cpu-common/cpu/rtc.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_SH_CPU_SH2_RTC_H
+#define __ASM_SH_CPU_SH2_RTC_H
+
+#define rtc_reg_size            sizeof(u16)
+#define RTC_BIT_INVERTED        0
+#define RTC_DEF_CAPABILITIES    0UL
+
+#endif /* __ASM_SH_CPU_SH2_RTC_H */
diff --git a/arch/sh/include/cpu-common/cpu/sigcontext.h b/arch/sh/include/cpu-common/cpu/sigcontext.h
new file mode 100644
index 000000000000..fe5c15dd6e87
--- /dev/null
+++ b/arch/sh/include/cpu-common/cpu/sigcontext.h
@@ -0,0 +1,17 @@
+#ifndef __ASM_CPU_SH2_SIGCONTEXT_H
+#define __ASM_CPU_SH2_SIGCONTEXT_H
+
+struct sigcontext {
+        unsigned long   oldmask;
+
+        /* CPU registers */
+        unsigned long sc_regs[16];
+        unsigned long sc_pc;
+        unsigned long sc_pr;
+        unsigned long sc_sr;
+        unsigned long sc_gbr;
+        unsigned long sc_mach;
+        unsigned long sc_macl;
+};
+
+#endif /* __ASM_CPU_SH2_SIGCONTEXT_H */
diff --git a/arch/sh/include/cpu-common/cpu/timer.h b/arch/sh/include/cpu-common/cpu/timer.h
new file mode 100644
index 000000000000..a39c241e8195
--- /dev/null
+++ b/arch/sh/include/cpu-common/cpu/timer.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_CPU_SH2_TIMER_H
+#define __ASM_CPU_SH2_TIMER_H
+
+/* Nothing needed yet */
+
+#endif /* __ASM_CPU_SH2_TIMER_H */
diff --git a/arch/sh/include/cpu-sh2/cpu/cache.h b/arch/sh/include/cpu-sh2/cpu/cache.h
new file mode 100644
index 000000000000..4e0b16500686
--- /dev/null
+++ b/arch/sh/include/cpu-sh2/cpu/cache.h
@@ -0,0 +1,41 @@
+/*
+ * include/asm-sh/cpu-sh2/cache.h
+ *
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_CACHE_H
+#define __ASM_CPU_SH2_CACHE_H
+
+#define L1_CACHE_SHIFT  4
+
+#define SH_CACHE_VALID          1
+#define SH_CACHE_UPDATED        2
+#define SH_CACHE_COMBINED       4
+#define SH_CACHE_ASSOC          8
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7619)
+#define CCR             0xffffffec
+
+#define CCR_CACHE_CE    0x01    /* Cache enable */
+#define CCR_CACHE_WT    0x06    /* CCR[bit1=1,bit2=1] */
+                                /* 0x00000000-0x7fffffff: Write-through  */
+                                /* 0x80000000-0x9fffffff: Write-back     */
+                                /* 0xc0000000-0xdfffffff: Write-through  */
+#define CCR_CACHE_CB    0x00    /* CCR[bit1=0,bit2=0] */
+                                /* 0x00000000-0x7fffffff: Write-back     */
+                                /* 0x80000000-0x9fffffff: Write-through  */
+                                /* 0xc0000000-0xdfffffff: Write-back     */
+#define CCR_CACHE_CF    0x08    /* Cache invalidate */
+
+#define CACHE_OC_ADDRESS_ARRAY  0xf0000000
+#define CACHE_OC_DATA_ARRAY     0xf1000000
+
+#define CCR_CACHE_ENABLE        CCR_CACHE_CE
+#define CCR_CACHE_INVALIDATE    CCR_CACHE_CF
+#endif
+
+#endif /* __ASM_CPU_SH2_CACHE_H */
diff --git a/arch/sh/include/cpu-sh2/cpu/dma.h b/arch/sh/include/cpu-sh2/cpu/dma.h
new file mode 100644
index 000000000000..d66b43cdc637
--- /dev/null
+++ b/arch/sh/include/cpu-sh2/cpu/dma.h
@@ -0,0 +1,23 @@
+/*
+ * Definitions for the SH-2 DMAC.
+ *
+ * Copyright (C) 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_DMA_H
+#define __ASM_CPU_SH2_DMA_H
+
+#define SH_MAX_DMA_CHANNELS     2
+
+#define SAR     ((unsigned long[]){ 0xffffff80, 0xffffff90 })
+#define DAR     ((unsigned long[]){ 0xffffff84, 0xffffff94 })
+#define DMATCR  ((unsigned long[]){ 0xffffff88, 0xffffff98 })
+#define CHCR    ((unsigned long[]){ 0xfffffffc, 0xffffff9c })
+
+#define DMAOR   0xffffffb0
+
+#endif /* __ASM_CPU_SH2_DMA_H */
+
diff --git a/arch/sh/include/cpu-sh2/cpu/freq.h b/arch/sh/include/cpu-sh2/cpu/freq.h
new file mode 100644
index 000000000000..31de475da70b
--- /dev/null
+++ b/arch/sh/include/cpu-sh2/cpu/freq.h
@@ -0,0 +1,18 @@
+/*
+ * include/asm-sh/cpu-sh2/freq.h
+ *
+ * Copyright (C) 2006  Yoshinori Sato
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_FREQ_H
+#define __ASM_CPU_SH2_FREQ_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7619)
+#define FREQCR  0xf815ff80
+#endif
+
+#endif /* __ASM_CPU_SH2_FREQ_H */
+
diff --git a/arch/sh/include/cpu-sh2/cpu/ubc.h b/arch/sh/include/cpu-sh2/cpu/ubc.h
new file mode 100644
index 000000000000..ba0e87f19c7a
--- /dev/null
+++ b/arch/sh/include/cpu-sh2/cpu/ubc.h
@@ -0,0 +1,32 @@
+/*
+ * include/asm-sh/cpu-sh2/ubc.h
+ *
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_UBC_H
+#define __ASM_CPU_SH2_UBC_H
+
+#define UBC_BARA                0xffffff40
+#define UBC_BAMRA               0xffffff44
+#define UBC_BBRA                0xffffff48
+#define UBC_BARB                0xffffff60
+#define UBC_BAMRB               0xffffff64
+#define UBC_BBRB                0xffffff68
+#define UBC_BDRB                0xffffff70
+#define UBC_BDMRB               0xffffff74
+#define UBC_BRCR                0xffffff78
+
+/*
+ * We don't have any ASID changes to make in the UBC on the SH-2.
+ *
+ * Make these purposely invalid to track misuse.
+ */
+#define UBC_BASRA               0x00000000
+#define UBC_BASRB               0x00000000
+
+#endif /* __ASM_CPU_SH2_UBC_H */
+
diff --git a/arch/sh/include/cpu-sh2/cpu/watchdog.h b/arch/sh/include/cpu-sh2/cpu/watchdog.h
new file mode 100644
index 000000000000..393161c9c6d0
--- /dev/null
+++ b/arch/sh/include/cpu-sh2/cpu/watchdog.h
@@ -0,0 +1,69 @@
+/*
+ * include/asm-sh/cpu-sh2/watchdog.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_WATCHDOG_H
+#define __ASM_CPU_SH2_WATCHDOG_H
+
+/*
+ * More SH-2 brilliance .. its not good enough that we can't read
+ * and write the same sizes to WTCNT, now we have to read and write
+ * with different sizes at different addresses for WTCNT _and_ RSTCSR.
+ *
+ * At least on the bright side no one has managed to screw over WTCSR
+ * in this fashion .. yet.
+ */
+/* Register definitions */
+#define WTCNT           0xfffffe80
+#define WTCSR           0xfffffe80
+#define RSTCSR          0xfffffe82
+
+#define WTCNT_R         (WTCNT + 1)
+#define RSTCSR_R        (RSTCSR + 1)
+
+/* Bit definitions */
+#define WTCSR_IOVF      0x80
+#define WTCSR_WT        0x40
+#define WTCSR_TME       0x20
+#define WTCSR_RSTS      0x00
+
+#define RSTCSR_RSTS     0x20
+
+/**
+ *      sh_wdt_read_rstcsr - Read from Reset Control/Status Register
+ *
+ *      Reads back the RSTCSR value.
+ */
+static inline __u8 sh_wdt_read_rstcsr(void)
+{
+        /*
+         * Same read/write brain-damage as for WTCNT here..
+         */
+        return ctrl_inb(RSTCSR_R);
+}
+
+/**
+ *      sh_wdt_write_csr - Write to Reset Control/Status Register
+ *
+ *      @val: Value to write
+ *
+ *      Writes the given value @val to the lower byte of the control/status
+ *      register. The upper byte is set manually on each write.
+ */
+static inline void sh_wdt_write_rstcsr(__u8 val)
+{
+        /*
+         * Note: Due to the brain-damaged nature of this register,
+         * we can't presently touch the WOVF bit, since the upper byte
+         * has to be swapped for this. So just leave it alone..
+         */
+        ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, RSTCSR);
+}
+
+#endif /* __ASM_CPU_SH2_WATCHDOG_H */
+
diff --git a/arch/sh/include/cpu-sh2a/cpu/cache.h b/arch/sh/include/cpu-sh2a/cpu/cache.h
new file mode 100644
index 000000000000..afe228b3f493
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/cache.h
@@ -0,0 +1,40 @@
+/*
+ * include/asm-sh/cpu-sh2a/cache.h
+ *
+ * Copyright (C) 2004 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2A_CACHE_H
+#define __ASM_CPU_SH2A_CACHE_H
+
+#define L1_CACHE_SHIFT  4
+
+#define SH_CACHE_VALID          1
+#define SH_CACHE_UPDATED        2
+#define SH_CACHE_COMBINED       4
+#define SH_CACHE_ASSOC          8
+
+#define CCR             0xfffc1000 /* CCR1 */
+#define CCR2            0xfffc1004
+
+/*
+ * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
+ * listed here are reserved.
+ */
+#define CCR_CACHE_CB    0x0000  /* Hack */
+#define CCR_CACHE_OCE   0x0001
+#define CCR_CACHE_WT    0x0002
+#define CCR_CACHE_OCI   0x0008  /* OCF */
+#define CCR_CACHE_ICE   0x0100
+#define CCR_CACHE_ICI   0x0800  /* ICF */
+
+#define CACHE_IC_ADDRESS_ARRAY  0xf0000000
+#define CACHE_OC_ADDRESS_ARRAY  0xf0800000
+
+#define CCR_CACHE_ENABLE        (CCR_CACHE_OCE | CCR_CACHE_ICE)
+#define CCR_CACHE_INVALIDATE    (CCR_CACHE_OCI | CCR_CACHE_ICI)
+
+#endif /* __ASM_CPU_SH2A_CACHE_H */
diff --git a/arch/sh/include/cpu-sh2a/cpu/dma.h b/arch/sh/include/cpu-sh2a/cpu/dma.h
new file mode 100644
index 000000000000..27a13ef4fdfc
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/dma.h
@@ -0,0 +1 @@
+#include <cpu-sh2/cpu/dma.h>
diff --git a/arch/sh/include/cpu-sh2a/cpu/freq.h b/arch/sh/include/cpu-sh2a/cpu/freq.h
new file mode 100644
index 000000000000..830fd43b6cdc
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/freq.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-sh/cpu-sh2a/freq.h
+ *
+ * Copyright (C) 2006  Yoshinori Sato
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2A_FREQ_H
+#define __ASM_CPU_SH2A_FREQ_H
+
+#define FREQCR  0xfffe0010
+
+#endif /* __ASM_CPU_SH2A_FREQ_H */
+
diff --git a/arch/sh/include/cpu-sh2a/cpu/rtc.h b/arch/sh/include/cpu-sh2a/cpu/rtc.h
new file mode 100644
index 000000000000..afb511e2bed7
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/rtc.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_SH_CPU_SH2A_RTC_H
+#define __ASM_SH_CPU_SH2A_RTC_H
+
+#define rtc_reg_size            sizeof(u16)
+#define RTC_BIT_INVERTED        0
+#define RTC_DEF_CAPABILITIES    RTC_CAP_4_DIGIT_YEAR
+
+#endif /* __ASM_SH_CPU_SH2A_RTC_H */
diff --git a/arch/sh/include/cpu-sh2a/cpu/ubc.h b/arch/sh/include/cpu-sh2a/cpu/ubc.h
new file mode 100644
index 000000000000..8ce2fc1cf625
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/ubc.h
@@ -0,0 +1 @@
+#include <cpu-sh2/cpu/ubc.h>
diff --git a/arch/sh/include/cpu-sh2a/cpu/watchdog.h b/arch/sh/include/cpu-sh2a/cpu/watchdog.h
new file mode 100644
index 000000000000..e7e8259e468c
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/watchdog.h
@@ -0,0 +1 @@
+#include <cpu-sh2/cpu/watchdog.h>
diff --git a/arch/sh/include/cpu-sh3/cpu/adc.h b/arch/sh/include/cpu-sh3/cpu/adc.h
new file mode 100644
index 000000000000..b289e3ca19a6
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/adc.h
@@ -0,0 +1,28 @@
+#ifndef __ASM_CPU_SH3_ADC_H
+#define __ASM_CPU_SH3_ADC_H
+
+/*
+ * Copyright (C) 2004  Andriy Skulysh
+ */
+
+
+#define ADDRAH  0xa4000080
+#define ADDRAL  0xa4000082
+#define ADDRBH  0xa4000084
+#define ADDRBL  0xa4000086
+#define ADDRCH  0xa4000088
+#define ADDRCL  0xa400008a
+#define ADDRDH  0xa400008c
+#define ADDRDL  0xa400008e
+#define ADCSR   0xa4000090
+
+#define ADCSR_ADF       0x80
+#define ADCSR_ADIE      0x40
+#define ADCSR_ADST      0x20
+#define ADCSR_MULTI     0x10
+#define ADCSR_CKS       0x08
+#define ADCSR_CH_MASK   0x07
+
+#define ADCR    0xa4000092
+
+#endif /* __ASM_CPU_SH3_ADC_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/cache.h b/arch/sh/include/cpu-sh3/cpu/cache.h
new file mode 100644
index 000000000000..bee2d81c56bf
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/cache.h
@@ -0,0 +1,43 @@
+/*
+ * include/asm-sh/cpu-sh3/cache.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH3_CACHE_H
+#define __ASM_CPU_SH3_CACHE_H
+
+#define L1_CACHE_SHIFT  4
+
+#define SH_CACHE_VALID          1
+#define SH_CACHE_UPDATED        2
+#define SH_CACHE_COMBINED       4
+#define SH_CACHE_ASSOC          8
+
+#define CCR             0xffffffec      /* Address of Cache Control Register */
+
+#define CCR_CACHE_CE    0x01    /* Cache Enable */
+#define CCR_CACHE_WT    0x02    /* Write-Through (for P0,U0,P3) (else writeback) */
+#define CCR_CACHE_CB    0x04    /* Write-Back (for P1) (else writethrough) */
+#define CCR_CACHE_CF    0x08    /* Cache Flush */
+#define CCR_CACHE_ORA   0x20    /* RAM mode */
+
+#define CACHE_OC_ADDRESS_ARRAY  0xf0000000
+#define CACHE_PHYSADDR_MASK     0x1ffffc00
+
+#define CCR_CACHE_ENABLE        CCR_CACHE_CE
+#define CCR_CACHE_INVALIDATE    CCR_CACHE_CF
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
+#define CCR3_REG        0xa40000b4
+#define CCR_CACHE_16KB  0x00010000
+#define CCR_CACHE_32KB  0x00020000
+#endif
+
+#endif /* __ASM_CPU_SH3_CACHE_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/cacheflush.h b/arch/sh/include/cpu-sh3/cpu/cacheflush.h
new file mode 100644
index 000000000000..abc909880807
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/cacheflush.h
@@ -0,0 +1,36 @@
+/*
+ * include/asm-sh/cpu-sh3/cacheflush.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH3_CACHEFLUSH_H
+#define __ASM_CPU_SH3_CACHEFLUSH_H
+
+#if defined(CONFIG_SH7705_CACHE_32KB)
+/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the
+ * SH4. Unlike the SH4 this is a unified cache so we need to do some work
+ * in mmap when 'exec'ing a new binary
+ */
+ /* 32KB cache, 4kb PAGE sizes need to check bit 12 */
+#define CACHE_ALIAS 0x00001000
+
+#define PG_mapped       PG_arch_1
+
+void flush_cache_all(void);
+void flush_cache_mm(struct mm_struct *mm);
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
+void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
+                              unsigned long end);
+void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
+void flush_dcache_page(struct page *pg);
+void flush_icache_range(unsigned long start, unsigned long end);
+void flush_icache_page(struct vm_area_struct *vma, struct page *page);
+#else
+#include <cpu-common/cpu/cacheflush.h>
+#endif
+
+#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/dac.h b/arch/sh/include/cpu-sh3/cpu/dac.h
new file mode 100644
index 000000000000..05fda8316ebc
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/dac.h
@@ -0,0 +1,41 @@
+#ifndef __ASM_CPU_SH3_DAC_H
+#define __ASM_CPU_SH3_DAC_H
+
+/*
+ * Copyright (C) 2003  Andriy Skulysh
+ */
+
+
+#define DADR0   0xa40000a0
+#define DADR1   0xa40000a2
+#define DACR    0xa40000a4
+#define DACR_DAOE1      0x80
+#define DACR_DAOE0      0x40
+#define DACR_DAE        0x20
+
+
+static __inline__ void sh_dac_enable(int channel)
+{
+        unsigned char v;
+        v = ctrl_inb(DACR);
+        if(channel) v |= DACR_DAOE1;
+        else v |= DACR_DAOE0;
+        ctrl_outb(v,DACR);
+}
+
+static __inline__ void sh_dac_disable(int channel)
+{
+        unsigned char v;
+        v = ctrl_inb(DACR);
+        if(channel) v &= ~DACR_DAOE1;
+        else v &= ~DACR_DAOE0;
+        ctrl_outb(v,DACR);
+}
+
+static __inline__ void sh_dac_output(u8 value, int channel)
+{
+        if(channel) ctrl_outb(value,DADR1);
+        else ctrl_outb(value,DADR0);
+}
+
+#endif /* __ASM_CPU_SH3_DAC_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/dma.h b/arch/sh/include/cpu-sh3/cpu/dma.h
new file mode 100644
index 000000000000..6813c3220a1d
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/dma.h
@@ -0,0 +1,51 @@
+#ifndef __ASM_CPU_SH3_DMA_H
+#define __ASM_CPU_SH3_DMA_H
+
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
+#define SH_DMAC_BASE    0xa4010020
+#else
+#define SH_DMAC_BASE    0xa4000020
+#endif
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
+#define DMTE0_IRQ       48
+#define DMTE1_IRQ       49
+#define DMTE2_IRQ       50
+#define DMTE3_IRQ       51
+#define DMTE4_IRQ       76
+#define DMTE5_IRQ       77
+#endif
+
+/* Definitions for the SuperH DMAC */
+#define TM_BURST        0x00000020
+#define TS_8            0x00000000
+#define TS_16           0x00000008
+#define TS_32           0x00000010
+#define TS_128          0x00000018
+
+#define CHCR_TS_MASK    0x18
+#define CHCR_TS_SHIFT   3
+
+#define DMAOR_INIT      DMAOR_DME
+
+/*
+ * The SuperH DMAC supports a number of transmit sizes, we list them here,
+ * with their respective values as they appear in the CHCR registers.
+ */
+enum {
+        XMIT_SZ_8BIT,
+        XMIT_SZ_16BIT,
+        XMIT_SZ_32BIT,
+        XMIT_SZ_128BIT,
+};
+
+static unsigned int ts_shift[] __maybe_unused = {
+        [XMIT_SZ_8BIT]          = 0,
+        [XMIT_SZ_16BIT]         = 1,
+        [XMIT_SZ_32BIT]         = 2,
+        [XMIT_SZ_128BIT]        = 4,
+};
+
+#endif /* __ASM_CPU_SH3_DMA_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/freq.h b/arch/sh/include/cpu-sh3/cpu/freq.h
new file mode 100644
index 000000000000..53c62302b2e3
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/freq.h
@@ -0,0 +1,27 @@
+/*
+ * include/asm-sh/cpu-sh3/freq.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH3_FREQ_H
+#define __ASM_CPU_SH3_FREQ_H
+
+#ifdef CONFIG_CPU_SUBTYPE_SH7712
+#define FRQCR                   0xA415FF80
+#else
+#define FRQCR                   0xffffff80
+#endif
+
+#define MIN_DIVISOR_NR          0
+#define MAX_DIVISOR_NR          4
+
+#define FRQCR_CKOEN     0x0100
+#define FRQCR_PLLEN     0x0080
+#define FRQCR_PSTBY     0x0040
+
+#endif /* __ASM_CPU_SH3_FREQ_H */
+
diff --git a/arch/sh/include/cpu-sh3/cpu/gpio.h b/arch/sh/include/cpu-sh3/cpu/gpio.h
new file mode 100644
index 000000000000..4e53eb314b8f
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/gpio.h
@@ -0,0 +1,67 @@
+/*
+ *  include/asm-sh/cpu-sh3/gpio.h
+ *
+ *  Copyright (C) 2007  Markus Brunner, Mark Jonas
+ *
+ *  Addresses for the Pin Function Controller
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _CPU_SH3_GPIO_H
+#define _CPU_SH3_GPIO_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
+
+/* Control registers */
+#define PORT_PACR       0xA4050100UL
+#define PORT_PBCR       0xA4050102UL
+#define PORT_PCCR       0xA4050104UL
+#define PORT_PDCR       0xA4050106UL
+#define PORT_PECR       0xA4050108UL
+#define PORT_PFCR       0xA405010AUL
+#define PORT_PGCR       0xA405010CUL
+#define PORT_PHCR       0xA405010EUL
+#define PORT_PJCR       0xA4050110UL
+#define PORT_PKCR       0xA4050112UL
+#define PORT_PLCR       0xA4050114UL
+#define PORT_PMCR       0xA4050116UL
+#define PORT_PPCR       0xA4050118UL
+#define PORT_PRCR       0xA405011AUL
+#define PORT_PSCR       0xA405011CUL
+#define PORT_PTCR       0xA405011EUL
+#define PORT_PUCR       0xA4050120UL
+#define PORT_PVCR       0xA4050122UL
+
+/* Data registers */
+#define PORT_PADR       0xA4050140UL
+/* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */
+#define PORT_PBDR       0xA4050142UL
+#define PORT_PCDR       0xA4050144UL
+#define PORT_PDDR       0xA4050146UL
+#define PORT_PEDR       0xA4050148UL
+#define PORT_PFDR       0xA405014AUL
+#define PORT_PGDR       0xA405014CUL
+#define PORT_PHDR       0xA405014EUL
+#define PORT_PJDR       0xA4050150UL
+#define PORT_PKDR       0xA4050152UL
+#define PORT_PLDR       0xA4050154UL
+#define PORT_PMDR       0xA4050156UL
+#define PORT_PPDR       0xA4050158UL
+#define PORT_PRDR       0xA405015AUL
+#define PORT_PSDR       0xA405015CUL
+#define PORT_PTDR       0xA405015EUL
+#define PORT_PUDR       0xA4050160UL
+#define PORT_PVDR       0xA4050162UL
+
+/* Pin Select Registers */
+#define PORT_PSELA      0xA4050124UL
+#define PORT_PSELB      0xA4050126UL
+#define PORT_PSELC      0xA4050128UL
+#define PORT_PSELD      0xA405012AUL
+
+#endif
+
+#endif
diff --git a/arch/sh/include/cpu-sh3/cpu/mmu_context.h b/arch/sh/include/cpu-sh3/cpu/mmu_context.h
new file mode 100644
index 000000000000..ab09da73ce77
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/mmu_context.h
@@ -0,0 +1,44 @@
+/*
+ * include/asm-sh/cpu-sh3/mmu_context.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH3_MMU_CONTEXT_H
+#define __ASM_CPU_SH3_MMU_CONTEXT_H
+
+#define MMU_PTEH        0xFFFFFFF0      /* Page table entry register HIGH */
+#define MMU_PTEL        0xFFFFFFF4      /* Page table entry register LOW */
+#define MMU_TTB         0xFFFFFFF8      /* Translation table base register */
+#define MMU_TEA         0xFFFFFFFC      /* TLB Exception Address */
+
+#define MMUCR           0xFFFFFFE0      /* MMU Control Register */
+
+#define MMU_TLB_ADDRESS_ARRAY   0xF2000000
+#define MMU_PAGE_ASSOC_BIT      0x80
+
+#define MMU_NTLB_ENTRIES        128     /* for 7708 */
+#define MMU_NTLB_WAYS           4
+#define MMU_CONTROL_INIT        0x007   /* SV=0, TF=1, IX=1, AT=1 */
+
+#define TRA     0xffffffd0
+#define EXPEVT  0xffffffd4
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7706) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7709) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7712) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
+#define INTEVT  0xa4000000      /* INTEVTE2(0xa4000000) */
+#else
+#define INTEVT  0xffffffd8
+#endif
+
+#endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */
+
diff --git a/arch/sh/include/cpu-sh3/cpu/timer.h b/arch/sh/include/cpu-sh3/cpu/timer.h
new file mode 100644
index 000000000000..793acf12aa08
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/timer.h
@@ -0,0 +1,67 @@
+/*
+ * include/asm-sh/cpu-sh3/timer.h
+ *
+ * Copyright (C) 2004 Lineo Solutions, Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH3_TIMER_H
+#define __ASM_CPU_SH3_TIMER_H
+
+/*
+ * ---------------------------------------------------------------------------
+ * TMU Common definitions for SH3 processors
+ *      SH7706
+ *      SH7709S
+ *      SH7727
+ *      SH7729R
+ *      SH7710
+ *      SH7720
+ *      SH7710
+ * ---------------------------------------------------------------------------
+ */
+
+#if  !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
+#define TMU_TOCR        0xfffffe90      /* Byte access */
+#endif
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
+#define TMU_012_TSTR    0xa412fe92      /* Byte access */
+
+#define TMU0_TCOR       0xa412fe94      /* Long access */
+#define TMU0_TCNT       0xa412fe98      /* Long access */
+#define TMU0_TCR        0xa412fe9c      /* Word access */
+
+#define TMU1_TCOR       0xa412fea0      /* Long access */
+#define TMU1_TCNT       0xa412fea4      /* Long access */
+#define TMU1_TCR        0xa412fea8      /* Word access */
+
+#define TMU2_TCOR       0xa412feac      /* Long access */
+#define TMU2_TCNT       0xa412feb0      /* Long access */
+#define TMU2_TCR        0xa412feb4      /* Word access */
+
+#else
+#define TMU_012_TSTR    0xfffffe92      /* Byte access */
+
+#define TMU0_TCOR       0xfffffe94      /* Long access */
+#define TMU0_TCNT       0xfffffe98      /* Long access */
+#define TMU0_TCR        0xfffffe9c      /* Word access */
+
+#define TMU1_TCOR       0xfffffea0      /* Long access */
+#define TMU1_TCNT       0xfffffea4      /* Long access */
+#define TMU1_TCR        0xfffffea8      /* Word access */
+
+#define TMU2_TCOR       0xfffffeac      /* Long access */
+#define TMU2_TCNT       0xfffffeb0      /* Long access */
+#define TMU2_TCR        0xfffffeb4      /* Word access */
+#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
+#define TMU2_TCPR2      0xfffffeb8      /* Long access */
+#endif
+#endif
+
+#endif /* __ASM_CPU_SH3_TIMER_H */
+
diff --git a/arch/sh/include/cpu-sh3/cpu/ubc.h b/arch/sh/include/cpu-sh3/cpu/ubc.h
new file mode 100644
index 000000000000..4e6381d5ff7a
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/ubc.h
@@ -0,0 +1,42 @@
+/*
+ * include/asm-sh/cpu-sh3/ubc.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH3_UBC_H
+#define __ASM_CPU_SH3_UBC_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
+#define UBC_BARA                0xa4ffffb0
+#define UBC_BAMRA               0xa4ffffb4
+#define UBC_BBRA                0xa4ffffb8
+#define UBC_BASRA               0xffffffe4
+#define UBC_BARB                0xa4ffffa0
+#define UBC_BAMRB               0xa4ffffa4
+#define UBC_BBRB                0xa4ffffa8
+#define UBC_BASRB               0xffffffe8
+#define UBC_BDRB                0xa4ffff90
+#define UBC_BDMRB               0xa4ffff94
+#define UBC_BRCR                0xa4ffff98
+#else
+#define UBC_BARA                0xffffffb0
+#define UBC_BAMRA               0xffffffb4
+#define UBC_BBRA                0xffffffb8
+#define UBC_BASRA               0xffffffe4
+#define UBC_BARB                0xffffffa0
+#define UBC_BAMRB               0xffffffa4
+#define UBC_BBRB                0xffffffa8
+#define UBC_BASRB               0xffffffe8
+#define UBC_BDRB                0xffffff90
+#define UBC_BDMRB               0xffffff94
+#define UBC_BRCR                0xffffff98
+#endif
+
+#endif /* __ASM_CPU_SH3_UBC_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/watchdog.h b/arch/sh/include/cpu-sh3/cpu/watchdog.h
new file mode 100644
index 000000000000..4ee0347298d8
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/watchdog.h
@@ -0,0 +1,25 @@
+/*
+ * include/asm-sh/cpu-sh3/watchdog.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH3_WATCHDOG_H
+#define __ASM_CPU_SH3_WATCHDOG_H
+
+/* Register definitions */
+#define WTCNT           0xffffff84
+#define WTCSR           0xffffff86
+
+/* Bit definitions */
+#define WTCSR_TME       0x80
+#define WTCSR_WT        0x40
+#define WTCSR_RSTS      0x20
+#define WTCSR_WOVF      0x10
+#define WTCSR_IOVF      0x08
+
+#endif /* __ASM_CPU_SH3_WATCHDOG_H */
+
diff --git a/arch/sh/include/cpu-sh4/cpu/addrspace.h b/arch/sh/include/cpu-sh4/cpu/addrspace.h
new file mode 100644
index 000000000000..a3fa733c1c7d
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/addrspace.h
@@ -0,0 +1,35 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 by Kaz Kojima
+ *
+ * Defitions for the address spaces of the SH-4 CPUs.
+ */
+#ifndef __ASM_CPU_SH4_ADDRSPACE_H
+#define __ASM_CPU_SH4_ADDRSPACE_H
+
+#define P0SEG           0x00000000
+#define P1SEG           0x80000000
+#define P2SEG           0xa0000000
+#define P3SEG           0xc0000000
+#define P4SEG           0xe0000000
+
+/* Detailed P4SEG  */
+#define P4SEG_STORE_QUE (P4SEG)
+#define P4SEG_IC_ADDR   0xf0000000
+#define P4SEG_IC_DATA   0xf1000000
+#define P4SEG_ITLB_ADDR 0xf2000000
+#define P4SEG_ITLB_DATA 0xf3000000
+#define P4SEG_OC_ADDR   0xf4000000
+#define P4SEG_OC_DATA   0xf5000000
+#define P4SEG_TLB_ADDR  0xf6000000
+#define P4SEG_TLB_DATA  0xf7000000
+#define P4SEG_REG_BASE  0xff000000
+
+#define PA_AREA5_IO     0xb4000000      /* Area 5 IO Memory */
+#define PA_AREA6_IO     0xb8000000      /* Area 6 IO Memory */
+
+#endif /* __ASM_CPU_SH4_ADDRSPACE_H */
+
diff --git a/arch/sh/include/cpu-sh4/cpu/cache.h b/arch/sh/include/cpu-sh4/cpu/cache.h
new file mode 100644
index 000000000000..1c61ebf5c8e3
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/cache.h
@@ -0,0 +1,42 @@
+/*
+ * include/asm-sh/cpu-sh4/cache.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_CACHE_H
+#define __ASM_CPU_SH4_CACHE_H
+
+#define L1_CACHE_SHIFT  5
+
+#define SH_CACHE_VALID          1
+#define SH_CACHE_UPDATED        2
+#define SH_CACHE_COMBINED       4
+#define SH_CACHE_ASSOC          8
+
+#define CCR             0xff00001c      /* Address of Cache Control Register */
+#define CCR_CACHE_OCE   0x0001  /* Operand Cache Enable */
+#define CCR_CACHE_WT    0x0002  /* Write-Through (for P0,U0,P3) (else writeback)*/
+#define CCR_CACHE_CB    0x0004  /* Copy-Back (for P1) (else writethrough) */
+#define CCR_CACHE_OCI   0x0008  /* OC Invalidate */
+#define CCR_CACHE_ORA   0x0020  /* OC RAM Mode */
+#define CCR_CACHE_OIX   0x0080  /* OC Index Enable */
+#define CCR_CACHE_ICE   0x0100  /* Instruction Cache Enable */
+#define CCR_CACHE_ICI   0x0800  /* IC Invalidate */
+#define CCR_CACHE_IIX   0x8000  /* IC Index Enable */
+#ifndef CONFIG_CPU_SH4A
+#define CCR_CACHE_EMODE 0x80000000      /* EMODE Enable */
+#endif
+
+/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
+#define CCR_CACHE_ENABLE        (CCR_CACHE_OCE|CCR_CACHE_ICE)
+#define CCR_CACHE_INVALIDATE    (CCR_CACHE_OCI|CCR_CACHE_ICI)
+
+#define CACHE_IC_ADDRESS_ARRAY  0xf0000000
+#define CACHE_OC_ADDRESS_ARRAY  0xf4000000
+
+#endif /* __ASM_CPU_SH4_CACHE_H */
+
diff --git a/arch/sh/include/cpu-sh4/cpu/cacheflush.h b/arch/sh/include/cpu-sh4/cpu/cacheflush.h
new file mode 100644
index 000000000000..065306d376eb
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/cacheflush.h
@@ -0,0 +1,43 @@
+/*
+ * include/asm-sh/cpu-sh4/cacheflush.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_CACHEFLUSH_H
+#define __ASM_CPU_SH4_CACHEFLUSH_H
+
+/*
+ *  Caches are broken on SH-4 (unless we use write-through
+ *  caching; in which case they're only semi-broken),
+ *  so we need them.
+ */
+void flush_cache_all(void);
+void flush_dcache_all(void);
+void flush_cache_mm(struct mm_struct *mm);
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
+void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
+                       unsigned long end);
+void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
+                      unsigned long pfn);
+void flush_dcache_page(struct page *pg);
+
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+
+void flush_icache_range(unsigned long start, unsigned long end);
+void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
+                             unsigned long addr, int len);
+
+#define flush_icache_page(vma,pg)               do { } while (0)
+
+/* Initialization of P3 area for copy_user_page */
+void p3_cache_init(void);
+
+#define PG_mapped       PG_arch_1
+
+#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h b/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h
new file mode 100644
index 000000000000..71b426a6e482
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h
@@ -0,0 +1,39 @@
+#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
+#define __ASM_SH_CPU_SH4_DMA_SH7780_H
+
+#define REQ_HE  0x000000C0
+#define REQ_H   0x00000080
+#define REQ_LE  0x00000040
+#define TM_BURST 0x0000020
+#define TS_8    0x00000000
+#define TS_16   0x00000008
+#define TS_32   0x00000010
+#define TS_16BLK        0x00000018
+#define TS_32BLK        0x00100000
+
+/*
+ * The SuperH DMAC supports a number of transmit sizes, we list them here,
+ * with their respective values as they appear in the CHCR registers.
+ *
+ * Defaults to a 64-bit transfer size.
+ */
+enum {
+        XMIT_SZ_8BIT,
+        XMIT_SZ_16BIT,
+        XMIT_SZ_32BIT,
+        XMIT_SZ_128BIT,
+        XMIT_SZ_256BIT,
+};
+
+/*
+ * The DMA count is defined as the number of bytes to transfer.
+ */
+static unsigned int ts_shift[] __maybe_unused = {
+        [XMIT_SZ_8BIT]          = 0,
+        [XMIT_SZ_16BIT]         = 1,
+        [XMIT_SZ_32BIT]         = 2,
+        [XMIT_SZ_128BIT]        = 4,
+        [XMIT_SZ_256BIT]        = 5,
+};
+
+#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma.h b/arch/sh/include/cpu-sh4/cpu/dma.h
new file mode 100644
index 000000000000..235b7cd1fc9a
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/dma.h
@@ -0,0 +1,65 @@
+#ifndef __ASM_CPU_SH4_DMA_H
+#define __ASM_CPU_SH4_DMA_H
+
+#define DMAOR_INIT      ( 0x8000 | DMAOR_DME )
+
+/* SH7751/7760/7780 DMA IRQ sources */
+#define DMTE0_IRQ       34
+#define DMTE1_IRQ       35
+#define DMTE2_IRQ       36
+#define DMTE3_IRQ       37
+#define DMTE4_IRQ       44
+#define DMTE5_IRQ       45
+#define DMTE6_IRQ       46
+#define DMTE7_IRQ       47
+#define DMAE_IRQ        38
+
+#ifdef CONFIG_CPU_SH4A
+#define SH_DMAC_BASE    0xfc808020
+
+#define CHCR_TS_MASK    0x18
+#define CHCR_TS_SHIFT   3
+
+#include <cpu/dma-sh7780.h>
+#else
+#define SH_DMAC_BASE    0xffa00000
+
+/* Definitions for the SuperH DMAC */
+#define TM_BURST        0x0000080
+#define TS_8            0x00000010
+#define TS_16           0x00000020
+#define TS_32           0x00000030
+#define TS_64           0x00000000
+
+#define CHCR_TS_MASK    0x70
+#define CHCR_TS_SHIFT   4
+
+#define DMAOR_COD       0x00000008
+
+/*
+ * The SuperH DMAC supports a number of transmit sizes, we list them here,
+ * with their respective values as they appear in the CHCR registers.
+ *
+ * Defaults to a 64-bit transfer size.
+ */
+enum {
+        XMIT_SZ_64BIT,
+        XMIT_SZ_8BIT,
+        XMIT_SZ_16BIT,
+        XMIT_SZ_32BIT,
+        XMIT_SZ_256BIT,
+};
+
+/*
+ * The DMA count is defined as the number of bytes to transfer.
+ */
+static unsigned int ts_shift[] __maybe_unused = {
+        [XMIT_SZ_64BIT]         = 3,
+        [XMIT_SZ_8BIT]          = 0,
+        [XMIT_SZ_16BIT]         = 1,
+        [XMIT_SZ_32BIT]         = 2,
+        [XMIT_SZ_256BIT]        = 5,
+};
+#endif
+
+#endif /* __ASM_CPU_SH4_DMA_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/fpu.h b/arch/sh/include/cpu-sh4/cpu/fpu.h
new file mode 100644
index 000000000000..febef7342528
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/fpu.h
@@ -0,0 +1,32 @@
+/*
+ * linux/arch/sh/kernel/cpu/sh4/sh4_fpu.h
+ *
+ * Copyright (C) 2006 STMicroelectronics Limited
+ * Author: Carl Shaw <carl.shaw@st.com>
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License Version 2.  See linux/COPYING for more information.
+ *
+ * Definitions for SH4 FPU operations
+ */
+
+#ifndef __CPU_SH4_FPU_H
+#define __CPU_SH4_FPU_H
+
+#define FPSCR_ENABLE_MASK       0x00000f80UL
+
+#define FPSCR_FMOV_DOUBLE       (1<<1)
+
+#define FPSCR_CAUSE_INEXACT     (1<<12)
+#define FPSCR_CAUSE_UNDERFLOW   (1<<13)
+#define FPSCR_CAUSE_OVERFLOW    (1<<14)
+#define FPSCR_CAUSE_DIVZERO     (1<<15)
+#define FPSCR_CAUSE_INVALID     (1<<16)
+#define FPSCR_CAUSE_ERROR       (1<<17)
+
+#define FPSCR_DBL_PRECISION     (1<<19)
+#define FPSCR_ROUNDING_MODE(x)  ((x >> 20) & 3)
+#define FPSCR_RM_NEAREST        (0)
+#define FPSCR_RM_ZERO           (1)
+
+#endif
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
new file mode 100644
index 000000000000..c23af81c2e70
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -0,0 +1,44 @@
+/*
+ * include/asm-sh/cpu-sh4/freq.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_FREQ_H
+#define __ASM_CPU_SH4_FREQ_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7723) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7343) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7366)
+#define FRQCR                   0xa4150000
+#define VCLKCR                  0xa4150004
+#define SCLKACR                 0xa4150008
+#define SCLKBCR                 0xa415000c
+#define IrDACLKCR               0xa4150010
+#define MSTPCR0                 0xa4150030
+#define MSTPCR1                 0xa4150034
+#define MSTPCR2                 0xa4150038
+#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
+      defined(CONFIG_CPU_SUBTYPE_SH7780)
+#define FRQCR                   0xffc80000
+#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
+#define FRQCR0                  0xffc80000
+#define FRQCR1                  0xffc80004
+#define FRQMR1                  0xffc80014
+#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
+#define FRQCR                   0xffc00014
+#else
+#define FRQCR                   0xffc00000
+#define FRQCR_PSTBY             0x0200
+#define FRQCR_PLLEN             0x0400
+#define FRQCR_CKOEN             0x0800
+#endif
+#define MIN_DIVISOR_NR          0
+#define MAX_DIVISOR_NR          3
+
+#endif /* __ASM_CPU_SH4_FREQ_H */
+
diff --git a/arch/sh/include/cpu-sh4/cpu/mmu_context.h b/arch/sh/include/cpu-sh4/cpu/mmu_context.h
new file mode 100644
index 000000000000..9ea8eb27b18e
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/mmu_context.h
@@ -0,0 +1,63 @@
+/*
+ * include/asm-sh/cpu-sh4/mmu_context.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
+#define __ASM_CPU_SH4_MMU_CONTEXT_H
+
+#define MMU_PTEH        0xFF000000      /* Page table entry register HIGH */
+#define MMU_PTEL        0xFF000004      /* Page table entry register LOW */
+#define MMU_TTB         0xFF000008      /* Translation table base register */
+#define MMU_TEA         0xFF00000C      /* TLB Exception Address */
+#define MMU_PTEA        0xFF000034      /* Page table entry assistance register */
+
+#define MMUCR           0xFF000010      /* MMU Control Register */
+
+#define MMU_ITLB_ADDRESS_ARRAY  0xF2000000
+#define MMU_UTLB_ADDRESS_ARRAY  0xF6000000
+#define MMU_PAGE_ASSOC_BIT      0x80
+
+#define MMUCR_TI                (1<<2)
+
+#ifdef CONFIG_X2TLB
+#define MMUCR_ME                (1 << 7)
+#else
+#define MMUCR_ME                (0)
+#endif
+
+#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
+#define MMUCR_SE                (1 << 4)
+#else
+#define MMUCR_SE                (0)
+#endif
+
+#ifdef CONFIG_SH_STORE_QUEUES
+#define MMUCR_SQMD              (1 << 9)
+#else
+#define MMUCR_SQMD              (0)
+#endif
+
+#define MMU_NTLB_ENTRIES        64
+#define MMU_CONTROL_INIT        (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE)
+
+#define MMU_ITLB_DATA_ARRAY     0xF3000000
+#define MMU_UTLB_DATA_ARRAY     0xF7000000
+
+#define MMU_UTLB_ENTRIES           64
+#define MMU_U_ENTRY_SHIFT           8
+#define MMU_UTLB_VALID          0x100
+#define MMU_ITLB_ENTRIES            4
+#define MMU_I_ENTRY_SHIFT           8
+#define MMU_ITLB_VALID          0x100
+
+#define TRA     0xff000020
+#define EXPEVT  0xff000024
+#define INTEVT  0xff000028
+
+#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */
+
diff --git a/arch/sh/include/cpu-sh4/cpu/rtc.h b/arch/sh/include/cpu-sh4/cpu/rtc.h
new file mode 100644
index 000000000000..25b1e6adfe8c
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/rtc.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_SH_CPU_SH4_RTC_H
+#define __ASM_SH_CPU_SH4_RTC_H
+
+#ifdef CONFIG_CPU_SUBTYPE_SH7723
+#define rtc_reg_size            sizeof(u16)
+#else
+#define rtc_reg_size            sizeof(u32)
+#endif
+
+#define RTC_BIT_INVERTED        0x40    /* bug on SH7750, SH7750S */
+#define RTC_DEF_CAPABILITIES    RTC_CAP_4_DIGIT_YEAR
+
+#endif /* __ASM_SH_CPU_SH4_RTC_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/sigcontext.h b/arch/sh/include/cpu-sh4/cpu/sigcontext.h
new file mode 100644
index 000000000000..ab392f120e06
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sigcontext.h
@@ -0,0 +1,24 @@
+#ifndef __ASM_CPU_SH4_SIGCONTEXT_H
+#define __ASM_CPU_SH4_SIGCONTEXT_H
+
+struct sigcontext {
+        unsigned long   oldmask;
+
+        /* CPU registers */
+        unsigned long sc_regs[16];
+        unsigned long sc_pc;
+        unsigned long sc_pr;
+        unsigned long sc_sr;
+        unsigned long sc_gbr;
+        unsigned long sc_mach;
+        unsigned long sc_macl;
+
+        /* FPU registers */
+        unsigned long sc_fpregs[16];
+        unsigned long sc_xfpregs[16];
+        unsigned int sc_fpscr;
+        unsigned int sc_fpul;
+        unsigned int sc_ownedfp;
+};
+
+#endif /* __ASM_CPU_SH4_SIGCONTEXT_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/sq.h b/arch/sh/include/cpu-sh4/cpu/sq.h
new file mode 100644
index 000000000000..586d6491816a
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sq.h
@@ -0,0 +1,35 @@
+/*
+ * include/asm-sh/cpu-sh4/sq.h
+ *
+ * Copyright (C) 2001, 2002, 2003  Paul Mundt
+ * Copyright (C) 2001, 2002  M. R. Brown
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_SQ_H
+#define __ASM_CPU_SH4_SQ_H
+
+#include <asm/addrspace.h>
+
+/*
+ * Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be
+ * mapped to any physical address space. Since data is written (and aligned)
+ * to 32-byte boundaries, we need to be sure that all allocations are aligned.
+ */
+#define SQ_SIZE                 32
+#define SQ_ALIGN_MASK           (~(SQ_SIZE - 1))
+#define SQ_ALIGN(addr)          (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK)
+
+#define SQ_QACR0                (P4SEG_REG_BASE  + 0x38)
+#define SQ_QACR1                (P4SEG_REG_BASE  + 0x3c)
+#define SQ_ADDRMAX              (P4SEG_STORE_QUE + 0x04000000)
+
+/* arch/sh/kernel/cpu/sh4/sq.c */
+unsigned long sq_remap(unsigned long phys, unsigned int size,
+                       const char *name, unsigned long flags);
+void sq_unmap(unsigned long vaddr);
+void sq_flush_range(unsigned long start, unsigned int len);
+
+#endif /* __ASM_CPU_SH4_SQ_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/timer.h b/arch/sh/include/cpu-sh4/cpu/timer.h
new file mode 100644
index 000000000000..d1e796b96888
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/timer.h
@@ -0,0 +1,60 @@
+/*
+ * include/asm-sh/cpu-sh4/timer.h
+ *
+ * Copyright (C) 2004 Lineo Solutions, Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_TIMER_H
+#define __ASM_CPU_SH4_TIMER_H
+
+/*
+ * ---------------------------------------------------------------------------
+ * TMU Common definitions for SH4 processors
+ *      SH7750S/SH7750R
+ *      SH7751/SH7751R
+ *      SH7760
+ *      SH-X3
+ * ---------------------------------------------------------------------------
+ */
+#ifdef CONFIG_CPU_SUBTYPE_SHX3
+#define TMU_012_BASE    0xffc10000
+#define TMU_345_BASE    0xffc20000
+#else
+#define TMU_012_BASE    0xffd80000
+#define TMU_345_BASE    0xfe100000
+#endif
+
+#define TMU_TOCR        TMU_012_BASE    /* Not supported on all CPUs */
+
+#define TMU_012_TSTR    (TMU_012_BASE + 0x04)
+#define TMU_345_TSTR    (TMU_345_BASE + 0x04)
+
+#define TMU0_TCOR       (TMU_012_BASE + 0x08)
+#define TMU0_TCNT       (TMU_012_BASE + 0x0c)
+#define TMU0_TCR        (TMU_012_BASE + 0x10)
+
+#define TMU1_TCOR       (TMU_012_BASE + 0x14)
+#define TMU1_TCNT       (TMU_012_BASE + 0x18)
+#define TMU1_TCR        (TMU_012_BASE + 0x1c)
+
+#define TMU2_TCOR       (TMU_012_BASE + 0x20)
+#define TMU2_TCNT       (TMU_012_BASE + 0x24)
+#define TMU2_TCR        (TMU_012_BASE + 0x28)
+#define TMU2_TCPR       (TMU_012_BASE + 0x2c)
+
+#define TMU3_TCOR       (TMU_345_BASE + 0x08)
+#define TMU3_TCNT       (TMU_345_BASE + 0x0c)
+#define TMU3_TCR        (TMU_345_BASE + 0x10)
+
+#define TMU4_TCOR       (TMU_345_BASE + 0x14)
+#define TMU4_TCNT       (TMU_345_BASE + 0x18)
+#define TMU4_TCR        (TMU_345_BASE + 0x1c)
+
+#define TMU5_TCOR       (TMU_345_BASE + 0x20)
+#define TMU5_TCNT       (TMU_345_BASE + 0x24)
+#define TMU5_TCR        (TMU_345_BASE + 0x28)
+
+#endif /* __ASM_CPU_SH4_TIMER_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/ubc.h b/arch/sh/include/cpu-sh4/cpu/ubc.h
new file mode 100644
index 000000000000..c86e17050935
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/ubc.h
@@ -0,0 +1,64 @@
+/*
+ * include/asm-sh/cpu-sh4/ubc.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2003 Paul Mundt
+ * Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_UBC_H
+#define __ASM_CPU_SH4_UBC_H
+
+#if defined(CONFIG_CPU_SH4A)
+#define UBC_CBR0                0xff200000
+#define UBC_CRR0                0xff200004
+#define UBC_CAR0                0xff200008
+#define UBC_CAMR0               0xff20000c
+#define UBC_CBR1                0xff200020
+#define UBC_CRR1                0xff200024
+#define UBC_CAR1                0xff200028
+#define UBC_CAMR1               0xff20002c
+#define UBC_CDR1                0xff200030
+#define UBC_CDMR1               0xff200034
+#define UBC_CETR1               0xff200038
+#define UBC_CCMFR               0xff200600
+#define UBC_CBCR                0xff200620
+
+/* CBR  */
+#define UBC_CBR_AIE             (0x01<<30)
+#define UBC_CBR_ID_INST         (0x01<<4)
+#define UBC_CBR_RW_READ         (0x01<<1)
+#define UBC_CBR_CE              (0x01)
+
+#define UBC_CBR_AIV_MASK        (0x00FF0000)
+#define UBC_CBR_AIV_SHIFT       (16)
+#define UBC_CBR_AIV_SET(asid)   (((asid)<<UBC_CBR_AIV_SHIFT) & UBC_CBR_AIV_MASK)
+
+#define UBC_CBR_INIT            0x20000000
+
+/* CRR  */
+#define UBC_CRR_RES             (0x01<<13)
+#define UBC_CRR_PCB             (0x01<<1)
+#define UBC_CRR_BIE             (0x01)
+
+#define UBC_CRR_INIT            0x00002000
+
+#else   /* CONFIG_CPU_SH4 */
+#define UBC_BARA                0xff200000
+#define UBC_BAMRA               0xff200004
+#define UBC_BBRA                0xff200008
+#define UBC_BASRA               0xff000014
+#define UBC_BARB                0xff20000c
+#define UBC_BAMRB               0xff200010
+#define UBC_BBRB                0xff200014
+#define UBC_BASRB               0xff000018
+#define UBC_BDRB                0xff200018
+#define UBC_BDMRB               0xff20001c
+#define UBC_BRCR                0xff200020
+#endif  /* CONFIG_CPU_SH4 */
+
+#endif /* __ASM_CPU_SH4_UBC_H */
+
diff --git a/arch/sh/include/cpu-sh4/cpu/watchdog.h b/arch/sh/include/cpu-sh4/cpu/watchdog.h
new file mode 100644
index 000000000000..259f6a0ce23d
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/watchdog.h
@@ -0,0 +1,25 @@
+/*
+ * include/asm-sh/cpu-sh4/watchdog.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_WATCHDOG_H
+#define __ASM_CPU_SH4_WATCHDOG_H
+
+/* Register definitions */
+#define WTCNT           0xffc00008
+#define WTCSR           0xffc0000c
+
+/* Bit definitions */
+#define WTCSR_TME       0x80
+#define WTCSR_WT        0x40
+#define WTCSR_RSTS      0x20
+#define WTCSR_WOVF      0x10
+#define WTCSR_IOVF      0x08
+
+#endif /* __ASM_CPU_SH4_WATCHDOG_H */
+
diff --git a/arch/sh/include/cpu-sh5/cpu/addrspace.h b/arch/sh/include/cpu-sh5/cpu/addrspace.h
new file mode 100644
index 000000000000..dc36b9a03af6
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/addrspace.h
@@ -0,0 +1,11 @@
+#ifndef __ASM_SH_CPU_SH5_ADDRSPACE_H
+#define __ASM_SH_CPU_SH5_ADDRSPACE_H
+
+#define PHYS_PERIPHERAL_BLOCK   0x09000000
+#define PHYS_DMAC_BLOCK         0x0e000000
+#define PHYS_PCI_BLOCK          0x60000000
+#define PHYS_EMI_BLOCK          0xff000000
+
+/* No segmentation.. */
+
+#endif /* __ASM_SH_CPU_SH5_ADDRSPACE_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/cache.h b/arch/sh/include/cpu-sh5/cpu/cache.h
new file mode 100644
index 000000000000..ed050ab526f2
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/cache.h
@@ -0,0 +1,97 @@
+#ifndef __ASM_SH_CPU_SH5_CACHE_H
+#define __ASM_SH_CPU_SH5_CACHE_H
+
+/*
+ * include/asm-sh/cpu-sh5/cache.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003, 2004  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#define L1_CACHE_SHIFT          5
+
+/* Valid and Dirty bits */
+#define SH_CACHE_VALID          (1LL<<0)
+#define SH_CACHE_UPDATED        (1LL<<57)
+
+/* Unimplemented compat bits.. */
+#define SH_CACHE_COMBINED       0
+#define SH_CACHE_ASSOC          0
+
+/* Cache flags */
+#define SH_CACHE_MODE_WT        (1LL<<0)
+#define SH_CACHE_MODE_WB        (1LL<<1)
+
+/*
+ * Control Registers.
+ */
+#define ICCR_BASE       0x01600000      /* Instruction Cache Control Register */
+#define ICCR_REG0       0               /* Register 0 offset */
+#define ICCR_REG1       1               /* Register 1 offset */
+#define ICCR0           ICCR_BASE+ICCR_REG0
+#define ICCR1           ICCR_BASE+ICCR_REG1
+
+#define ICCR0_OFF       0x0             /* Set ICACHE off */
+#define ICCR0_ON        0x1             /* Set ICACHE on */
+#define ICCR0_ICI       0x2             /* Invalidate all in IC */
+
+#define ICCR1_NOLOCK    0x0             /* Set No Locking */
+
+#define OCCR_BASE       0x01E00000      /* Operand Cache Control Register */
+#define OCCR_REG0       0               /* Register 0 offset */
+#define OCCR_REG1       1               /* Register 1 offset */
+#define OCCR0           OCCR_BASE+OCCR_REG0
+#define OCCR1           OCCR_BASE+OCCR_REG1
+
+#define OCCR0_OFF       0x0             /* Set OCACHE off */
+#define OCCR0_ON        0x1             /* Set OCACHE on */
+#define OCCR0_OCI       0x2             /* Invalidate all in OC */
+#define OCCR0_WT        0x4             /* Set OCACHE in WT Mode */
+#define OCCR0_WB        0x0             /* Set OCACHE in WB Mode */
+
+#define OCCR1_NOLOCK    0x0             /* Set No Locking */
+
+/*
+ * SH-5
+ * A bit of description here, for neff=32.
+ *
+ *                               |<--- tag  (19 bits) --->|
+ * +-----------------------------+-----------------+------+----------+------+
+ * |                             |                 | ways |set index |offset|
+ * +-----------------------------+-----------------+------+----------+------+
+ *                                ^                 2 bits   8 bits   5 bits
+ *                                +- Bit 31
+ *
+ * Cacheline size is based on offset: 5 bits = 32 bytes per line
+ * A cache line is identified by a tag + set but OCACHETAG/ICACHETAG
+ * have a broader space for registers. These are outlined by
+ * CACHE_?C_*_STEP below.
+ *
+ */
+
+/* Instruction cache */
+#define CACHE_IC_ADDRESS_ARRAY 0x01000000
+
+/* Operand Cache */
+#define CACHE_OC_ADDRESS_ARRAY 0x01800000
+
+/* These declarations relate to cache 'synonyms' in the operand cache.  A
+   'synonym' occurs where effective address bits overlap between those used for
+   indexing the cache sets and those passed to the MMU for translation.  In the
+   case of SH5-101 & SH5-103, only bit 12 is affected for 4k pages. */
+
+#define CACHE_OC_N_SYNBITS  1               /* Number of synonym bits */
+#define CACHE_OC_SYN_SHIFT  12
+/* Mask to select synonym bit(s) */
+#define CACHE_OC_SYN_MASK   (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT)
+
+/*
+ * Instruction cache can't be invalidated based on physical addresses.
+ * No Instruction Cache defines required, then.
+ */
+
+#endif /* __ASM_SH_CPU_SH5_CACHE_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/cacheflush.h b/arch/sh/include/cpu-sh5/cpu/cacheflush.h
new file mode 100644
index 000000000000..5a11f0b7e66a
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/cacheflush.h
@@ -0,0 +1,33 @@
+#ifndef __ASM_SH_CPU_SH5_CACHEFLUSH_H
+#define __ASM_SH_CPU_SH5_CACHEFLUSH_H
+
+#ifndef __ASSEMBLY__
+
+struct vm_area_struct;
+struct page;
+struct mm_struct;
+
+extern void flush_cache_all(void);
+extern void flush_cache_mm(struct mm_struct *mm);
+extern void flush_cache_sigtramp(unsigned long vaddr);
+extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
+                              unsigned long end);
+extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
+extern void flush_dcache_page(struct page *pg);
+extern void flush_icache_range(unsigned long start, unsigned long end);
+extern void flush_icache_user_range(struct vm_area_struct *vma,
+                                    struct page *page, unsigned long addr,
+                                    int len);
+
+#define flush_cache_dup_mm(mm)  flush_cache_mm(mm)
+
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+
+#define flush_icache_page(vma, page)    do { } while (0)
+void p3_cache_init(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_SH_CPU_SH5_CACHEFLUSH_H */
+
diff --git a/arch/sh/include/cpu-sh5/cpu/dma.h b/arch/sh/include/cpu-sh5/cpu/dma.h
new file mode 100644
index 000000000000..7bf6bb3d35ed
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/dma.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SH_CPU_SH5_DMA_H
+#define __ASM_SH_CPU_SH5_DMA_H
+
+/* Nothing yet */
+
+#endif /* __ASM_SH_CPU_SH5_DMA_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/irq.h b/arch/sh/include/cpu-sh5/cpu/irq.h
new file mode 100644
index 000000000000..f0f0756e6e84
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/irq.h
@@ -0,0 +1,117 @@
+#ifndef __ASM_SH_CPU_SH5_IRQ_H
+#define __ASM_SH_CPU_SH5_IRQ_H
+
+/*
+ * include/asm-sh/cpu-sh5/irq.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+
+/*
+ * Encoded IRQs are not considered worth to be supported.
+ * Main reason is that there's no per-encoded-interrupt
+ * enable/disable mechanism (as there was in SH3/4).
+ * An all enabled/all disabled is worth only if there's
+ * a cascaded IC to disable/enable/ack on. Until such
+ * IC is available there's no such support.
+ *
+ * Presumably Encoded IRQs may use extra IRQs beyond 64,
+ * below. Some logic must be added to cope with IRQ_IRL?
+ * in an exclusive way.
+ *
+ * Priorities are set at Platform level, when IRQ_IRL0-3
+ * are set to 0 Encoding is allowed. Otherwise it's not
+ * allowed.
+ */
+
+/* Independent IRQs */
+#define IRQ_IRL0        0
+#define IRQ_IRL1        1
+#define IRQ_IRL2        2
+#define IRQ_IRL3        3
+
+#define IRQ_INTA        4
+#define IRQ_INTB        5
+#define IRQ_INTC        6
+#define IRQ_INTD        7
+
+#define IRQ_SERR        12
+#define IRQ_ERR         13
+#define IRQ_PWR3        14
+#define IRQ_PWR2        15
+#define IRQ_PWR1        16
+#define IRQ_PWR0        17
+
+#define IRQ_DMTE0       18
+#define IRQ_DMTE1       19
+#define IRQ_DMTE2       20
+#define IRQ_DMTE3       21
+#define IRQ_DAERR       22
+
+#define IRQ_TUNI0       32
+#define IRQ_TUNI1       33
+#define IRQ_TUNI2       34
+#define IRQ_TICPI2      35
+
+#define IRQ_ATI         36
+#define IRQ_PRI         37
+#define IRQ_CUI         38
+
+#define IRQ_ERI         39
+#define IRQ_RXI         40
+#define IRQ_BRI         41
+#define IRQ_TXI         42
+
+#define IRQ_ITI         63
+
+#define NR_INTC_IRQS    64
+
+#ifdef CONFIG_SH_CAYMAN
+#define NR_EXT_IRQS     32
+#define START_EXT_IRQS  64
+
+/* PCI bus 2 uses encoded external interrupts on the Cayman board */
+#define IRQ_P2INTA      (START_EXT_IRQS + (3*8) + 0)
+#define IRQ_P2INTB      (START_EXT_IRQS + (3*8) + 1)
+#define IRQ_P2INTC      (START_EXT_IRQS + (3*8) + 2)
+#define IRQ_P2INTD      (START_EXT_IRQS + (3*8) + 3)
+
+#define I8042_KBD_IRQ   (START_EXT_IRQS + 2)
+#define I8042_AUX_IRQ   (START_EXT_IRQS + 6)
+
+#define IRQ_CFCARD      (START_EXT_IRQS + 7)
+#define IRQ_PCMCIA      (0)
+
+#else
+#define NR_EXT_IRQS     0
+#endif
+
+/* Default IRQs, fixed */
+#define TIMER_IRQ       IRQ_TUNI0
+#define RTC_IRQ         IRQ_CUI
+
+/* Default Priorities, Platform may choose differently */
+#define NO_PRIORITY     0       /* Disabled */
+#define TIMER_PRIORITY  2
+#define RTC_PRIORITY    TIMER_PRIORITY
+#define SCIF_PRIORITY   3
+#define INTD_PRIORITY   3
+#define IRL3_PRIORITY   4
+#define INTC_PRIORITY   6
+#define IRL2_PRIORITY   7
+#define INTB_PRIORITY   9
+#define IRL1_PRIORITY   10
+#define INTA_PRIORITY   12
+#define IRL0_PRIORITY   13
+#define TOP_PRIORITY    15
+
+extern int intc_evt_to_irq[(0xE20/0x20)+1];
+int intc_irq_describe(char* p, int irq);
+extern int platform_int_priority[NR_INTC_IRQS];
+
+#endif /* __ASM_SH_CPU_SH5_IRQ_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/mmu_context.h b/arch/sh/include/cpu-sh5/cpu/mmu_context.h
new file mode 100644
index 000000000000..68a1d2cff457
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/mmu_context.h
@@ -0,0 +1,21 @@
+#ifndef __ASM_SH_CPU_SH5_MMU_CONTEXT_H
+#define __ASM_SH_CPU_SH5_MMU_CONTEXT_H
+
+/* Common defines */
+#define TLB_STEP        0x00000010
+#define TLB_PTEH        0x00000000
+#define TLB_PTEL        0x00000008
+
+/* PTEH defines */
+#define PTEH_ASID_SHIFT 2
+#define PTEH_VALID      0x0000000000000001
+#define PTEH_SHARED     0x0000000000000002
+#define PTEH_MATCH_ASID 0x00000000000003ff
+
+#ifndef __ASSEMBLY__
+/* This has to be a common function because the next location to fill
+ * information is shared. */
+extern void __do_tlb_refill(unsigned long address, unsigned long long is_text_not_data, pte_t *pte);
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_SH_CPU_SH5_MMU_CONTEXT_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/registers.h b/arch/sh/include/cpu-sh5/cpu/registers.h
new file mode 100644
index 000000000000..6664ea6f1566
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/registers.h
@@ -0,0 +1,106 @@
+#ifndef __ASM_SH_CPU_SH5_REGISTERS_H
+#define __ASM_SH_CPU_SH5_REGISTERS_H
+
+/*
+ * include/asm-sh/cpu-sh5/registers.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2004  Richard Curnow
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifdef __ASSEMBLY__
+/* =====================================================================
+**
+** Section 1: acts on assembly sources pre-processed by GPP ( <source.S>).
+**            Assigns symbolic names to control & target registers.
+*/
+
+/*
+ * Define some useful aliases for control registers.
+ */
+#define SR      cr0
+#define SSR     cr1
+#define PSSR    cr2
+                        /* cr3 UNDEFINED */
+#define INTEVT  cr4
+#define EXPEVT  cr5
+#define PEXPEVT cr6
+#define TRA     cr7
+#define SPC     cr8
+#define PSPC    cr9
+#define RESVEC  cr10
+#define VBR     cr11
+                        /* cr12 UNDEFINED */
+#define TEA     cr13
+                        /* cr14-cr15 UNDEFINED */
+#define DCR     cr16
+#define KCR0    cr17
+#define KCR1    cr18
+                        /* cr19-cr31 UNDEFINED */
+                        /* cr32-cr61 RESERVED */
+#define CTC     cr62
+#define USR     cr63
+
+/*
+ * ABI dependent registers (general purpose set)
+ */
+#define RET     r2
+#define ARG1    r2
+#define ARG2    r3
+#define ARG3    r4
+#define ARG4    r5
+#define ARG5    r6
+#define ARG6    r7
+#define SP      r15
+#define LINK    r18
+#define ZERO    r63
+
+/*
+ * Status register defines: used only by assembly sources (and
+ *                          syntax independednt)
+ */
+#define SR_RESET_VAL    0x0000000050008000
+#define SR_HARMLESS     0x00000000500080f0      /* Write ignores for most */
+#define SR_ENABLE_FPU   0xffffffffffff7fff      /* AND with this */
+
+#if defined (CONFIG_SH64_SR_WATCH)
+#define SR_ENABLE_MMU   0x0000000084000000      /* OR with this */
+#else
+#define SR_ENABLE_MMU   0x0000000080000000      /* OR with this */
+#endif
+
+#define SR_UNBLOCK_EXC  0xffffffffefffffff      /* AND with this */
+#define SR_BLOCK_EXC    0x0000000010000000      /* OR with this */
+
+#else   /* Not __ASSEMBLY__ syntax */
+
+/*
+** Stringify reg. name
+*/
+#define __str(x)  #x
+
+/* Stringify control register names for use in inline assembly */
+#define __SR __str(SR)
+#define __SSR __str(SSR)
+#define __PSSR __str(PSSR)
+#define __INTEVT __str(INTEVT)
+#define __EXPEVT __str(EXPEVT)
+#define __PEXPEVT __str(PEXPEVT)
+#define __TRA __str(TRA)
+#define __SPC __str(SPC)
+#define __PSPC __str(PSPC)
+#define __RESVEC __str(RESVEC)
+#define __VBR __str(VBR)
+#define __TEA __str(TEA)
+#define __DCR __str(DCR)
+#define __KCR0 __str(KCR0)
+#define __KCR1 __str(KCR1)
+#define __CTC __str(CTC)
+#define __USR __str(USR)
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_SH_CPU_SH5_REGISTERS_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/rtc.h b/arch/sh/include/cpu-sh5/cpu/rtc.h
new file mode 100644
index 000000000000..12ea0ed144e1
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/rtc.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_SH_CPU_SH5_RTC_H
+#define __ASM_SH_CPU_SH5_RTC_H
+
+#define rtc_reg_size            sizeof(u32)
+#define RTC_BIT_INVERTED        0       /* The SH-5 RTC is surprisingly sane! */
+#define RTC_DEF_CAPABILITIES    RTC_CAP_4_DIGIT_YEAR
+
+#endif /* __ASM_SH_CPU_SH5_RTC_H */
diff --git a/arch/sh/include/mach-dreamcast/mach/dma.h b/arch/sh/include/mach-dreamcast/mach/dma.h
new file mode 100644
index 000000000000..ddd68e788705
--- /dev/null
+++ b/arch/sh/include/mach-dreamcast/mach/dma.h
@@ -0,0 +1,34 @@
+/*
+ * include/asm-sh/dreamcast/dma.h
+ *
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_DREAMCAST_DMA_H
+#define __ASM_SH_DREAMCAST_DMA_H
+
+/* Number of DMA channels */
+#define ONCHIP_NR_DMA_CHANNELS  4
+#define G2_NR_DMA_CHANNELS      4
+#define PVR2_NR_DMA_CHANNELS    1
+
+/* Channels for cascading */
+#define PVR2_CASCADE_CHAN       2
+#define G2_CASCADE_CHAN         3
+
+/* PVR2 DMA Registers */
+#define PVR2_DMA_BASE           0xa05f6800
+#define PVR2_DMA_ADDR           (PVR2_DMA_BASE + 0)
+#define PVR2_DMA_COUNT          (PVR2_DMA_BASE + 4)
+#define PVR2_DMA_MODE           (PVR2_DMA_BASE + 8)
+#define PVR2_DMA_LMMODE0        (PVR2_DMA_BASE + 132)
+#define PVR2_DMA_LMMODE1        (PVR2_DMA_BASE + 136)
+
+/* G2 DMA Register */
+#define G2_DMA_BASE             0xa05f7800
+
+#endif /* __ASM_SH_DREAMCAST_DMA_H */
+
diff --git a/arch/sh/include/mach-dreamcast/mach/maple.h b/arch/sh/include/mach-dreamcast/mach/maple.h
new file mode 100644
index 000000000000..51f6a87f1f11
--- /dev/null
+++ b/arch/sh/include/mach-dreamcast/mach/maple.h
@@ -0,0 +1,37 @@
+#ifndef __ASM_MAPLE_H
+#define __ASM_MAPLE_H
+
+#define MAPLE_PORTS 4
+#define MAPLE_PNP_INTERVAL HZ
+#define MAPLE_MAXPACKETS 8
+#define MAPLE_DMA_ORDER 14
+#define MAPLE_DMA_SIZE (1 << MAPLE_DMA_ORDER)
+#define MAPLE_DMA_PAGES ((MAPLE_DMA_ORDER > PAGE_SHIFT) ? \
+                          MAPLE_DMA_ORDER - PAGE_SHIFT : 0)
+
+/* Maple Bus registers */
+#define MAPLE_BASE     0xa05f6c00
+#define MAPLE_DMAADDR  (MAPLE_BASE+0x04)
+#define MAPLE_TRIGTYPE (MAPLE_BASE+0x10)
+#define MAPLE_ENABLE   (MAPLE_BASE+0x14)
+#define MAPLE_STATE    (MAPLE_BASE+0x18)
+#define MAPLE_SPEED    (MAPLE_BASE+0x80)
+#define MAPLE_RESET    (MAPLE_BASE+0x8c)
+
+#define MAPLE_MAGIC    0x6155404f
+#define MAPLE_2MBPS    0
+#define MAPLE_TIMEOUT(n) ((n)<<15)
+
+/* Function codes */
+#define MAPLE_FUNC_CONTROLLER 0x001
+#define MAPLE_FUNC_MEMCARD    0x002
+#define MAPLE_FUNC_LCD        0x004
+#define MAPLE_FUNC_CLOCK      0x008
+#define MAPLE_FUNC_MICROPHONE 0x010
+#define MAPLE_FUNC_ARGUN      0x020
+#define MAPLE_FUNC_KEYBOARD   0x040
+#define MAPLE_FUNC_LIGHTGUN   0x080
+#define MAPLE_FUNC_PURUPURU   0x100
+#define MAPLE_FUNC_MOUSE      0x200
+
+#endif /* __ASM_MAPLE_H */
diff --git a/arch/sh/include/mach-dreamcast/mach/pci.h b/arch/sh/include/mach-dreamcast/mach/pci.h
new file mode 100644
index 000000000000..75fc9009e092
--- /dev/null
+++ b/arch/sh/include/mach-dreamcast/mach/pci.h
@@ -0,0 +1,25 @@
+/*
+ * include/asm-sh/dreamcast/pci.h
+ *
+ * Copyright (C) 2001, 2002  M. R. Brown
+ * Copyright (C) 2002, 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_DREAMCAST_PCI_H
+#define __ASM_SH_DREAMCAST_PCI_H
+
+#include <mach-dreamcast/mach/sysasic.h>
+
+#define GAPSPCI_REGS            0x01001400
+#define GAPSPCI_DMA_BASE        0x01840000
+#define GAPSPCI_DMA_SIZE        32768
+#define GAPSPCI_BBA_CONFIG      0x01001600
+#define GAPSPCI_BBA_CONFIG_SIZE 0x2000
+
+#define GAPSPCI_IRQ             HW_EVENT_EXTERNAL
+
+#endif /* __ASM_SH_DREAMCAST_PCI_H */
+
diff --git a/arch/sh/include/mach-dreamcast/mach/sysasic.h b/arch/sh/include/mach-dreamcast/mach/sysasic.h
new file mode 100644
index 000000000000..f33426608a87
--- /dev/null
+++ b/arch/sh/include/mach-dreamcast/mach/sysasic.h
@@ -0,0 +1,43 @@
+/* include/asm-sh/dreamcast/sysasic.h
+ *
+ * Definitions for the Dreamcast System ASIC and related peripherals.
+ *
+ * Copyright (c) 2001 M. R. Brown <mrbrown@linuxdc.org>
+ * Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org>
+ *
+ * This file is part of the LinuxDC project (www.linuxdc.org)
+ *
+ * Released under the terms of the GNU GPL v2.0.
+ *
+ */
+#ifndef __ASM_SH_DREAMCAST_SYSASIC_H
+#define __ASM_SH_DREAMCAST_SYSASIC_H
+
+#include <asm/irq.h>
+
+/* Hardware events -
+
+   Each of these events correspond to a bit within the Event Mask Registers/
+   Event Status Registers.  Because of the virtual IRQ numbering scheme, a
+   base offset must be used when calculating the virtual IRQ that each event
+   takes.
+*/
+
+#define HW_EVENT_IRQ_BASE  48
+
+/* IRQ 13 */
+#define HW_EVENT_VSYNC     (HW_EVENT_IRQ_BASE +  5) /* VSync */
+#define HW_EVENT_MAPLE_DMA (HW_EVENT_IRQ_BASE + 12) /* Maple DMA complete */
+#define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */
+#define HW_EVENT_G2_DMA    (HW_EVENT_IRQ_BASE + 15) /* G2 DMA complete */
+#define HW_EVENT_PVR2_DMA  (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */
+
+/* IRQ 11 */
+#define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */
+#define HW_EVENT_AICA_SYS  (HW_EVENT_IRQ_BASE + 33) /* AICA-related */
+#define HW_EVENT_EXTERNAL  (HW_EVENT_IRQ_BASE + 35) /* Ext. (expansion) */
+
+#define HW_EVENT_IRQ_MAX (HW_EVENT_IRQ_BASE + 95)
+
+#endif /* __ASM_SH_DREAMCAST_SYSASIC_H */
+
diff --git a/arch/sh/include/mach-landisk/mach/gio.h b/arch/sh/include/mach-landisk/mach/gio.h
new file mode 100644
index 000000000000..35d7368b718a
--- /dev/null
+++ b/arch/sh/include/mach-landisk/mach/gio.h
@@ -0,0 +1,37 @@
+#ifndef __ASM_SH_LANDISK_GIO_H
+#define __ASM_SH_LANDISK_GIO_H
+
+#include <linux/ioctl.h>
+
+/* version */
+#define VERSION_STR     "1.00"
+
+/* Driver name */
+#define GIO_DRIVER_NAME         "/dev/giodrv"
+
+/* Use 'k' as magic number */
+#define GIODRV_IOC_MAGIC  'k'
+
+#define GIODRV_IOCRESET    _IO(GIODRV_IOC_MAGIC, 0)
+/*
+ * S means "Set" through a ptr,
+ * T means "Tell" directly
+ * G means "Get" (to a pointed var)
+ * Q means "Query", response is on the return value
+ * X means "eXchange": G and S atomically
+ * H means "sHift": T and Q atomically
+ */
+#define GIODRV_IOCSGIODATA1   _IOW(GIODRV_IOC_MAGIC,  1, unsigned char *)
+#define GIODRV_IOCGGIODATA1   _IOR(GIODRV_IOC_MAGIC,  2, unsigned char *)
+#define GIODRV_IOCSGIODATA2   _IOW(GIODRV_IOC_MAGIC,  3, unsigned short *)
+#define GIODRV_IOCGGIODATA2   _IOR(GIODRV_IOC_MAGIC,  4, unsigned short *)
+#define GIODRV_IOCSGIODATA4   _IOW(GIODRV_IOC_MAGIC,  5, unsigned long *)
+#define GIODRV_IOCGGIODATA4   _IOR(GIODRV_IOC_MAGIC,  6, unsigned long *)
+#define GIODRV_IOCSGIOSETADDR _IOW(GIODRV_IOC_MAGIC,  7, unsigned long *)
+#define GIODRV_IOCHARDRESET   _IO(GIODRV_IOC_MAGIC, 8) /* debugging tool */
+#define GIODRV_IOC_MAXNR 8
+
+#define GIO_READ 0x00000000
+#define GIO_WRITE 0x00000001
+
+#endif /* __ASM_SH_LANDISK_GIO_H  */
diff --git a/arch/sh/include/mach-landisk/mach/iodata_landisk.h b/arch/sh/include/mach-landisk/mach/iodata_landisk.h
new file mode 100644
index 000000000000..6fb04ab38b9f
--- /dev/null
+++ b/arch/sh/include/mach-landisk/mach/iodata_landisk.h
@@ -0,0 +1,42 @@
+#ifndef __ASM_SH_IODATA_LANDISK_H
+#define __ASM_SH_IODATA_LANDISK_H
+
+/*
+ * linux/include/asm-sh/landisk/iodata_landisk.h
+ *
+ * Copyright (C) 2000  Atom Create Engineering Co., Ltd.
+ *
+ * IO-DATA LANDISK support
+ */
+
+/* Box specific addresses.  */
+
+#define PA_USB          0xa4000000      /* USB Controller M66590 */
+
+#define PA_ATARST       0xb0000000      /* ATA/FATA Access Control Register */
+#define PA_LED          0xb0000001      /* LED Control Register */
+#define PA_STATUS       0xb0000002      /* Switch Status Register */
+#define PA_SHUTDOWN     0xb0000003      /* Shutdown Control Register */
+#define PA_PCIPME       0xb0000004      /* PCI PME Status Register */
+#define PA_IMASK        0xb0000005      /* Interrupt Mask Register */
+/* 2003.10.31 I-O DATA NSD NWG  add.    for shutdown port clear */
+#define PA_PWRINT_CLR   0xb0000006      /* Shutdown Interrupt clear Register */
+
+#define PA_PIDE_OFFSET  0x40            /* CF IDE Offset */
+#define PA_SIDE_OFFSET  0x40            /* HDD IDE Offset */
+
+#define IRQ_PCIINTA     5               /* PCI INTA IRQ */
+#define IRQ_PCIINTB     6               /* PCI INTB IRQ */
+#define IRQ_PCIINDC     7               /* PCI INTC IRQ */
+#define IRQ_PCIINTD     8               /* PCI INTD IRQ */
+#define IRQ_ATA         9               /* ATA IRQ */
+#define IRQ_FATA        10              /* FATA IRQ */
+#define IRQ_POWER       11              /* Power Switch IRQ */
+#define IRQ_BUTTON      12              /* USL-5P Button IRQ */
+#define IRQ_FAULT       13              /* USL-5P Fault  IRQ */
+
+#define __IO_PREFIX landisk
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_IODATA_LANDISK_H */
+
diff --git a/arch/sh/include/mach-se/mach/se.h b/arch/sh/include/mach-se/mach/se.h
new file mode 100644
index 000000000000..eb23000e1bbe
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se.h
@@ -0,0 +1,99 @@
+#ifndef __ASM_SH_HITACHI_SE_H
+#define __ASM_SH_HITACHI_SE_H
+
+/*
+ * linux/include/asm-sh/hitachi_se.h
+ *
+ * Copyright (C) 2000  Kazumoto Kojima
+ *
+ * Hitachi SolutionEngine support
+ */
+
+/* Box specific addresses.  */
+
+#define PA_ROM          0x00000000      /* EPROM */
+#define PA_ROM_SIZE     0x00400000      /* EPROM size 4M byte */
+#define PA_FROM         0x01000000      /* EPROM */
+#define PA_FROM_SIZE    0x00400000      /* EPROM size 4M byte */
+#define PA_EXT1         0x04000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_EXT2         0x08000000
+#define PA_EXT2_SIZE    0x04000000
+#define PA_SDRAM        0x0c000000
+#define PA_SDRAM_SIZE   0x04000000
+
+#define PA_EXT4         0x12000000
+#define PA_EXT4_SIZE    0x02000000
+#define PA_EXT5         0x14000000
+#define PA_EXT5_SIZE    0x04000000
+#define PA_PCIC         0x18000000      /* MR-SHPC-01 PCMCIA */
+
+#define PA_83902        0xb0000000      /* DP83902A */
+#define PA_83902_IF     0xb0040000      /* DP83902A remote io port */
+#define PA_83902_RST    0xb0080000      /* DP83902A reset port */
+
+#define PA_SUPERIO      0xb0400000      /* SMC37C935A super io chip */
+#define PA_DIPSW0       0xb0800000      /* Dip switch 5,6 */
+#define PA_DIPSW1       0xb0800002      /* Dip switch 7,8 */
+#define PA_LED          0xb0c00000      /* LED */
+#if defined(CONFIG_CPU_SUBTYPE_SH7705)
+#define PA_BCR          0xb0e00000
+#else
+#define PA_BCR          0xb1400000      /* FPGA */
+#endif
+
+#define PA_MRSHPC       0xb83fffe0      /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1   0xb8400000      /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2   0xb8500000      /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO    0xb8600000      /* MR-SHPC-01 I/O window base */
+#define MRSHPC_OPTION   (PA_MRSHPC + 6)
+#define MRSHPC_CSR      (PA_MRSHPC + 8)
+#define MRSHPC_ISR      (PA_MRSHPC + 10)
+#define MRSHPC_ICR      (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
+#define MRSHPC_CDCR     (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define BCR_ILCRA       (PA_BCR + 0)
+#define BCR_ILCRB       (PA_BCR + 2)
+#define BCR_ILCRC       (PA_BCR + 4)
+#define BCR_ILCRD       (PA_BCR + 6)
+#define BCR_ILCRE       (PA_BCR + 8)
+#define BCR_ILCRF       (PA_BCR + 10)
+#define BCR_ILCRG       (PA_BCR + 12)
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7705)
+#define IRQ_STNIC       12
+#define IRQ_CFCARD      14
+#else
+#define IRQ_STNIC       10
+#define IRQ_CFCARD      7
+#endif
+
+/* SH Ether support (SH7710/SH7712) */
+/* Base address */
+#define SH_ETH0_BASE 0xA7000000
+#define SH_ETH1_BASE 0xA7000400
+/* PHY ID */
+#if defined(CONFIG_CPU_SUBTYPE_SH7710)
+# define PHY_ID 0x00
+#elif defined(CONFIG_CPU_SUBTYPE_SH7712)
+# define PHY_ID 0x01
+#endif
+/* Ether IRQ */
+#define SH_ETH0_IRQ     80
+#define SH_ETH1_IRQ     81
+#define SH_TSU_IRQ      82
+
+void init_se_IRQ(void);
+
+#define __IO_PREFIX     se
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_HITACHI_SE_H */
diff --git a/arch/sh/include/mach-se/mach/se7206.h b/arch/sh/include/mach-se/mach/se7206.h
new file mode 100644
index 000000000000..698eb80389ab
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7206.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_SH_SE7206_H
+#define __ASM_SH_SE7206_H
+
+#define PA_SMSC         0x30000000
+#define PA_MRSHPC       0x34000000
+#define PA_LED          0x31400000
+
+void init_se7206_IRQ(void);
+
+#define __IO_PREFIX     se7206
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_SE7206_H */
diff --git a/arch/sh/include/mach-se/mach/se7343.h b/arch/sh/include/mach-se/mach/se7343.h
new file mode 100644
index 000000000000..98458460e632
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7343.h
@@ -0,0 +1,149 @@
+#ifndef __ASM_SH_HITACHI_SE7343_H
+#define __ASM_SH_HITACHI_SE7343_H
+
+/*
+ * include/asm-sh/se/se7343.h
+ *
+ * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
+ *
+ * SH-Mobile SolutionEngine 7343 support
+ */
+
+/* Box specific addresses.  */
+
+/* Area 0 */
+#define PA_ROM          0x00000000      /* EPROM */
+#define PA_ROM_SIZE     0x00400000      /* EPROM size 4M byte(Actually 2MB) */
+#define PA_FROM         0x00400000      /* Flash ROM */
+#define PA_FROM_SIZE    0x00400000      /* Flash size 4M byte */
+#define PA_SRAM         0x00800000      /* SRAM */
+#define PA_FROM_SIZE    0x00400000      /* SRAM size 4M byte */
+/* Area 1 */
+#define PA_EXT1         0x04000000
+#define PA_EXT1_SIZE    0x04000000
+/* Area 2 */
+#define PA_EXT2         0x08000000
+#define PA_EXT2_SIZE    0x04000000
+/* Area 3 */
+#define PA_SDRAM        0x0c000000
+#define PA_SDRAM_SIZE   0x04000000
+/* Area 4 */
+#define PA_PCIC         0x10000000      /* MR-SHPC-01 PCMCIA */
+#define PA_MRSHPC       0xb03fffe0      /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1   0xb0400000      /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2   0xb0500000      /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO    0xb0600000      /* MR-SHPC-01 I/O window base */
+#define MRSHPC_OPTION   (PA_MRSHPC + 6)
+#define MRSHPC_CSR      (PA_MRSHPC + 8)
+#define MRSHPC_ISR      (PA_MRSHPC + 10)
+#define MRSHPC_ICR      (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
+#define MRSHPC_CDCR     (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+#define PA_LED          0xb0C00000      /* LED */
+#define LED_SHIFT       0
+#define PA_DIPSW        0xb0900000      /* Dip switch 31 */
+#define PA_CPLD_MODESET 0xb1400004      /* CPLD Mode set register */
+#define PA_CPLD_ST      0xb1400008      /* CPLD Interrupt status register */
+#define PA_CPLD_IMSK    0xb140000a      /* CPLD Interrupt mask register */
+/* Area 5 */
+#define PA_EXT5         0x14000000
+#define PA_EXT5_SIZE    0x04000000
+/* Area 6 */
+#define PA_LCD1         0xb8000000
+#define PA_LCD2         0xb8800000
+
+#define PORT_PACR       0xA4050100
+#define PORT_PBCR       0xA4050102
+#define PORT_PCCR       0xA4050104
+#define PORT_PDCR       0xA4050106
+#define PORT_PECR       0xA4050108
+#define PORT_PFCR       0xA405010A
+#define PORT_PGCR       0xA405010C
+#define PORT_PHCR       0xA405010E
+#define PORT_PJCR       0xA4050110
+#define PORT_PKCR       0xA4050112
+#define PORT_PLCR       0xA4050114
+#define PORT_PMCR       0xA4050116
+#define PORT_PNCR       0xA4050118
+#define PORT_PQCR       0xA405011A
+#define PORT_PRCR       0xA405011C
+#define PORT_PSCR       0xA405011E
+#define PORT_PTCR       0xA4050140
+#define PORT_PUCR       0xA4050142
+#define PORT_PVCR       0xA4050144
+#define PORT_PWCR       0xA4050146
+#define PORT_PYCR       0xA4050148
+#define PORT_PZCR       0xA405014A
+
+#define PORT_PSELA      0xA405014C
+#define PORT_PSELB      0xA405014E
+#define PORT_PSELC      0xA4050150
+#define PORT_PSELD      0xA4050152
+#define PORT_PSELE      0xA4050154
+
+#define PORT_HIZCRA     0xA4050156
+#define PORT_HIZCRB     0xA4050158
+#define PORT_HIZCRC     0xA405015C
+
+#define PORT_DRVCR      0xA4050180
+
+#define PORT_PADR       0xA4050120
+#define PORT_PBDR       0xA4050122
+#define PORT_PCDR       0xA4050124
+#define PORT_PDDR       0xA4050126
+#define PORT_PEDR       0xA4050128
+#define PORT_PFDR       0xA405012A
+#define PORT_PGDR       0xA405012C
+#define PORT_PHDR       0xA405012E
+#define PORT_PJDR       0xA4050130
+#define PORT_PKDR       0xA4050132
+#define PORT_PLDR       0xA4050134
+#define PORT_PMDR       0xA4050136
+#define PORT_PNDR       0xA4050138
+#define PORT_PQDR       0xA405013A
+#define PORT_PRDR       0xA405013C
+#define PORT_PTDR       0xA4050160
+#define PORT_PUDR       0xA4050162
+#define PORT_PVDR       0xA4050164
+#define PORT_PWDR       0xA4050166
+#define PORT_PYDR       0xA4050168
+
+#define FPGA_IN         0xb1400000
+#define FPGA_OUT        0xb1400002
+
+#define __IO_PREFIX     sh7343se
+#include <asm/io_generic.h>
+
+#define IRQ0_IRQ        32
+#define IRQ1_IRQ        33
+#define IRQ4_IRQ        36
+#define IRQ5_IRQ        37
+
+#define SE7343_FPGA_IRQ_MRSHPC0 0
+#define SE7343_FPGA_IRQ_MRSHPC1 1
+#define SE7343_FPGA_IRQ_MRSHPC2 2
+#define SE7343_FPGA_IRQ_MRSHPC3 3
+#define SE7343_FPGA_IRQ_SMC     6       /* EXT_IRQ2 */
+#define SE7343_FPGA_IRQ_USB     8
+
+#define SE7343_FPGA_IRQ_NR      11
+#define SE7343_FPGA_IRQ_BASE    120
+
+#define MRSHPC_IRQ3     (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC3)
+#define MRSHPC_IRQ2     (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC2)
+#define MRSHPC_IRQ1     (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC1)
+#define MRSHPC_IRQ0     (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC0)
+#define SMC_IRQ         (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_SMC)
+#define USB_IRQ         (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_USB)
+
+/* arch/sh/boards/se/7343/irq.c */
+void init_7343se_IRQ(void);
+
+#endif  /* __ASM_SH_HITACHI_SE7343_H */
diff --git a/arch/sh/include/mach-se/mach/se7721.h b/arch/sh/include/mach-se/mach/se7721.h
new file mode 100644
index 000000000000..b957f6041193
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7721.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * Hitachi UL SolutionEngine 7721 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#ifndef __ASM_SH_SE7721_H
+#define __ASM_SH_SE7721_H
+#include <asm/addrspace.h>
+
+/* Box specific addresses. */
+#define SE_AREA0_WIDTH  2               /* Area0: 32bit */
+#define PA_ROM          0xa0000000      /* EPROM */
+#define PA_ROM_SIZE     0x00200000      /* EPROM size 2M byte */
+#define PA_FROM         0xa1000000      /* Flash-ROM */
+#define PA_FROM_SIZE    0x01000000      /* Flash-ROM size 16M byte */
+#define PA_EXT1         0xa4000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_SDRAM        0xaC000000      /* SDRAM(Area3) 64MB */
+#define PA_SDRAM_SIZE   0x04000000
+
+#define PA_EXT4         0xb0000000
+#define PA_EXT4_SIZE    0x04000000
+
+#define PA_PERIPHERAL   0xB8000000
+
+#define PA_PCIC         PA_PERIPHERAL
+#define PA_MRSHPC       (PA_PERIPHERAL + 0x003fffe0)
+#define PA_MRSHPC_MW1   (PA_PERIPHERAL + 0x00400000)
+#define PA_MRSHPC_MW2   (PA_PERIPHERAL + 0x00500000)
+#define PA_MRSHPC_IO    (PA_PERIPHERAL + 0x00600000)
+#define MRSHPC_OPTION   (PA_MRSHPC + 6)
+#define MRSHPC_CSR      (PA_MRSHPC + 8)
+#define MRSHPC_ISR      (PA_MRSHPC + 10)
+#define MRSHPC_ICR      (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
+#define MRSHPC_CDCR     (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO        (PA_MRSHPC + 30)
+
+#define PA_LED          0xB6800000      /* 8bit LED */
+#define PA_FPGA         0xB7000000      /* FPGA base address */
+
+#define MRSHPC_IRQ0     10
+
+#define FPGA_ILSR1      (PA_FPGA + 0x02)
+#define FPGA_ILSR2      (PA_FPGA + 0x03)
+#define FPGA_ILSR3      (PA_FPGA + 0x04)
+#define FPGA_ILSR4      (PA_FPGA + 0x05)
+#define FPGA_ILSR5      (PA_FPGA + 0x06)
+#define FPGA_ILSR6      (PA_FPGA + 0x07)
+#define FPGA_ILSR7      (PA_FPGA + 0x08)
+#define FPGA_ILSR8      (PA_FPGA + 0x09)
+
+void init_se7721_IRQ(void);
+
+#define __IO_PREFIX             se7721
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_SE7721_H */
diff --git a/arch/sh/include/mach-se/mach/se7722.h b/arch/sh/include/mach-se/mach/se7722.h
new file mode 100644
index 000000000000..e971d9a82f4a
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7722.h
@@ -0,0 +1,112 @@
+#ifndef __ASM_SH_SE7722_H
+#define __ASM_SH_SE7722_H
+
+/*
+ * linux/include/asm-sh/se7722.h
+ *
+ * Copyright (C) 2007  Nobuhiro Iwamatsu
+ *
+ * Hitachi UL SolutionEngine 7722 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <asm/addrspace.h>
+
+/* Box specific addresses.  */
+#define SE_AREA0_WIDTH  4               /* Area0: 32bit */
+#define PA_ROM          0xa0000000      /* EPROM */
+#define PA_ROM_SIZE     0x00200000      /* EPROM size 2M byte */
+#define PA_FROM         0xa1000000      /* Flash-ROM */
+#define PA_FROM_SIZE    0x01000000      /* Flash-ROM size 16M byte */
+#define PA_EXT1         0xa4000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_SDRAM        0xaC000000      /* DDR-SDRAM(Area3) 64MB */
+#define PA_SDRAM_SIZE   0x04000000
+
+#define PA_EXT4         0xb0000000
+#define PA_EXT4_SIZE    0x04000000
+
+#define PA_PERIPHERAL   0xB0000000
+
+#define PA_PCIC         PA_PERIPHERAL                   /* MR-SHPC-01 PCMCIA */
+#define PA_MRSHPC       (PA_PERIPHERAL + 0x003fffe0)    /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1   (PA_PERIPHERAL + 0x00400000)    /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2   (PA_PERIPHERAL + 0x00500000)    /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO    (PA_PERIPHERAL + 0x00600000)    /* MR-SHPC-01 I/O window base */
+#define MRSHPC_OPTION   (PA_MRSHPC + 6)
+#define MRSHPC_CSR      (PA_MRSHPC + 8)
+#define MRSHPC_ISR      (PA_MRSHPC + 10)
+#define MRSHPC_ICR      (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
+#define MRSHPC_CDCR     (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define PA_LED          (PA_PERIPHERAL + 0x00800000)    /* 8bit LED */
+#define PA_FPGA         (PA_PERIPHERAL + 0x01800000)    /* FPGA base address */
+
+#define PA_LAN          (PA_AREA6_IO + 0)               /* SMC LAN91C111 */
+/* GPIO */
+#define FPGA_IN         0xb1840000UL
+#define FPGA_OUT        0xb1840004UL
+
+#define PORT_PECR       0xA4050108UL
+#define PORT_PJCR       0xA4050110UL
+#define PORT_PSELD      0xA4050154UL
+#define PORT_PSELB      0xA4050150UL
+
+#define PORT_PSELC      0xA4050152UL
+#define PORT_PKCR       0xA4050112UL
+#define PORT_PHCR       0xA405010EUL
+#define PORT_PLCR       0xA4050114UL
+#define PORT_PMCR       0xA4050116UL
+#define PORT_PRCR       0xA405011CUL
+#define PORT_PXCR       0xA4050148UL
+#define PORT_PSELA      0xA405014EUL
+#define PORT_PYCR       0xA405014AUL
+#define PORT_PZCR       0xA405014CUL
+#define PORT_HIZCRA     0xA4050158UL
+#define PORT_HIZCRC     0xA405015CUL
+
+/* IRQ */
+#define IRQ0_IRQ        32
+#define IRQ1_IRQ        33
+
+#define IRQ01_MODE      0xb1800000
+#define IRQ01_STS       0xb1800004
+#define IRQ01_MASK      0xb1800008
+
+/* Bits in IRQ01_* registers */
+
+#define SE7722_FPGA_IRQ_USB     0 /* IRQ0 */
+#define SE7722_FPGA_IRQ_SMC     1 /* IRQ0 */
+#define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */
+#define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */
+#define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */
+#define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */
+
+#define SE7722_FPGA_IRQ_NR      6
+#define SE7722_FPGA_IRQ_BASE    110
+
+#define MRSHPC_IRQ3     (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC3)
+#define MRSHPC_IRQ2     (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC2)
+#define MRSHPC_IRQ1     (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC1)
+#define MRSHPC_IRQ0     (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC0)
+#define SMC_IRQ         (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_SMC)
+#define USB_IRQ         (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_USB)
+
+/* arch/sh/boards/se/7722/irq.c */
+void init_se7722_IRQ(void);
+
+#define __IO_PREFIX             se7722
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_SE7722_H */
diff --git a/arch/sh/include/mach-se/mach/se7751.h b/arch/sh/include/mach-se/mach/se7751.h
new file mode 100644
index 000000000000..b36792ac5d66
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7751.h
@@ -0,0 +1,73 @@
+#ifndef __ASM_SH_HITACHI_7751SE_H
+#define __ASM_SH_HITACHI_7751SE_H
+
+/*
+ * linux/include/asm-sh/hitachi_7751se.h
+ *
+ * Copyright (C) 2000  Kazumoto Kojima
+ *
+ * Hitachi SolutionEngine support
+
+ * Modified for 7751 Solution Engine by
+ * Ian da Silva and Jeremy Siegel, 2001.
+ */
+
+/* Box specific addresses.  */
+
+#define PA_ROM          0x00000000      /* EPROM */
+#define PA_ROM_SIZE     0x00400000      /* EPROM size 4M byte */
+#define PA_FROM         0x01000000      /* EPROM */
+#define PA_FROM_SIZE    0x00400000      /* EPROM size 4M byte */
+#define PA_EXT1         0x04000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_EXT2         0x08000000
+#define PA_EXT2_SIZE    0x04000000
+#define PA_SDRAM        0x0c000000
+#define PA_SDRAM_SIZE   0x04000000
+
+#define PA_EXT4         0x12000000
+#define PA_EXT4_SIZE    0x02000000
+#define PA_EXT5         0x14000000
+#define PA_EXT5_SIZE    0x04000000
+#define PA_PCIC         0x18000000      /* MR-SHPC-01 PCMCIA */
+
+#define PA_DIPSW0       0xb9000000      /* Dip switch 5,6 */
+#define PA_DIPSW1       0xb9000002      /* Dip switch 7,8 */
+#define PA_LED          0xba000000      /* LED */
+#define PA_BCR          0xbb000000      /* FPGA on the MS7751SE01 */
+
+#define PA_MRSHPC       0xb83fffe0      /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1   0xb8400000      /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2   0xb8500000      /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO    0xb8600000      /* MR-SHPC-01 I/O window base */
+#define MRSHPC_MODE     (PA_MRSHPC + 4)
+#define MRSHPC_OPTION   (PA_MRSHPC + 6)
+#define MRSHPC_CSR      (PA_MRSHPC + 8)
+#define MRSHPC_ISR      (PA_MRSHPC + 10)
+#define MRSHPC_ICR      (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
+#define MRSHPC_CDCR     (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define BCR_ILCRA       (PA_BCR + 0)
+#define BCR_ILCRB       (PA_BCR + 2)
+#define BCR_ILCRC       (PA_BCR + 4)
+#define BCR_ILCRD       (PA_BCR + 6)
+#define BCR_ILCRE       (PA_BCR + 8)
+#define BCR_ILCRF       (PA_BCR + 10)
+#define BCR_ILCRG       (PA_BCR + 12)
+
+#define IRQ_79C973      13
+
+void init_7751se_IRQ(void);
+
+#define __IO_PREFIX     sh7751se
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_HITACHI_7751SE_H */
diff --git a/arch/sh/include/mach-se/mach/se7780.h b/arch/sh/include/mach-se/mach/se7780.h
new file mode 100644
index 000000000000..40e9b41458cd
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7780.h
@@ -0,0 +1,108 @@
+#ifndef __ASM_SH_SE7780_H
+#define __ASM_SH_SE7780_H
+
+/*
+ * linux/include/asm-sh/se7780.h
+ *
+ * Copyright (C) 2006,2007  Nobuhiro Iwamatsu
+ *
+ * Hitachi UL SolutionEngine 7780 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <asm/addrspace.h>
+
+/* Box specific addresses.  */
+#define SE_AREA0_WIDTH  4               /* Area0: 32bit */
+#define PA_ROM          0xa0000000      /* EPROM */
+#define PA_ROM_SIZE     0x00400000      /* EPROM size 4M byte */
+#define PA_FROM         0xa1000000      /* Flash-ROM */
+#define PA_FROM_SIZE    0x01000000      /* Flash-ROM size 16M byte */
+#define PA_EXT1         0xa4000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_SM501        PA_EXT1         /* Graphic IC (SM501) */
+#define PA_SM501_SIZE   PA_EXT1_SIZE    /* Graphic IC (SM501) */
+#define PA_SDRAM        0xa8000000      /* DDR-SDRAM(Area2/3) 128MB */
+#define PA_SDRAM_SIZE   0x08000000
+
+#define PA_EXT4         0xb0000000
+#define PA_EXT4_SIZE    0x04000000
+#define PA_EXT_FLASH    PA_EXT4         /* Expansion Flash-ROM */
+
+#define PA_PERIPHERAL   PA_AREA6_IO     /* SW6-6=ON */
+
+#define PA_LAN          (PA_PERIPHERAL + 0)             /* SMC LAN91C111 */
+#define PA_LED_DISP     (PA_PERIPHERAL + 0x02000000)    /* 8words LED Display */
+#define DISP_CHAR_RAM   (7 << 3)
+#define DISP_SEL0_ADDR  (DISP_CHAR_RAM + 0)
+#define DISP_SEL1_ADDR  (DISP_CHAR_RAM + 1)
+#define DISP_SEL2_ADDR  (DISP_CHAR_RAM + 2)
+#define DISP_SEL3_ADDR  (DISP_CHAR_RAM + 3)
+#define DISP_SEL4_ADDR  (DISP_CHAR_RAM + 4)
+#define DISP_SEL5_ADDR  (DISP_CHAR_RAM + 5)
+#define DISP_SEL6_ADDR  (DISP_CHAR_RAM + 6)
+#define DISP_SEL7_ADDR  (DISP_CHAR_RAM + 7)
+
+#define DISP_UDC_RAM    (5 << 3)
+#define PA_FPGA         (PA_PERIPHERAL + 0x03000000) /* FPGA base address */
+
+/* FPGA register address and bit */
+#define FPGA_SFTRST             (PA_FPGA + 0)   /* Soft reset register */
+#define FPGA_INTMSK1            (PA_FPGA + 2)   /* Interrupt Mask register 1 */
+#define FPGA_INTMSK2            (PA_FPGA + 4)   /* Interrupt Mask register 2 */
+#define FPGA_INTSEL1            (PA_FPGA + 6)   /* Interrupt select register 1 */
+#define FPGA_INTSEL2            (PA_FPGA + 8)   /* Interrupt select register 2 */
+#define FPGA_INTSEL3            (PA_FPGA + 10)  /* Interrupt select register 3 */
+#define FPGA_PCI_INTSEL1        (PA_FPGA + 12)  /* PCI Interrupt select register 1 */
+#define FPGA_PCI_INTSEL2        (PA_FPGA + 14)  /* PCI Interrupt select register 2 */
+#define FPGA_INTSET             (PA_FPGA + 16)  /* IRQ/IRL select register */
+#define FPGA_INTSTS1            (PA_FPGA + 18)  /* Interrupt status register 1 */
+#define FPGA_INTSTS2            (PA_FPGA + 20)  /* Interrupt status register 2 */
+#define FPGA_REQSEL             (PA_FPGA + 22)  /* REQ/GNT select register */
+#define FPGA_DBG_LED            (PA_FPGA + 32)  /* Debug LED(D-LED[8:1] */
+#define PA_LED                  FPGA_DBG_LED
+#define FPGA_IVDRID             (PA_FPGA + 36)  /* iVDR ID Register */
+#define FPGA_IVDRPW             (PA_FPGA + 38)  /* iVDR Power ON Register */
+#define FPGA_MMCID              (PA_FPGA + 40)  /* MMC ID Register */
+
+/* FPGA INTSEL position */
+/* INTSEL1 */
+#define IRQPOS_SMC91CX          (0 * 4)
+#define IRQPOS_SM501            (1 * 4)
+/* INTSEL2 */
+#define IRQPOS_EXTINT1          (0 * 4)
+#define IRQPOS_EXTINT2          (1 * 4)
+#define IRQPOS_EXTINT3          (2 * 4)
+#define IRQPOS_EXTINT4          (3 * 4)
+/* INTSEL3 */
+#define IRQPOS_PCCPW            (0 * 4)
+
+/* IDE interrupt */
+#define IRQ_IDE0                67 /* iVDR */
+
+/* SMC interrupt */
+#define SMC_IRQ                 8
+
+/* SM501 interrupt */
+#define SM501_IRQ               0
+
+/* interrupt pin */
+#define IRQPIN_EXTINT1          0 /* IRQ0 pin */
+#define IRQPIN_EXTINT2          1 /* IRQ1 pin */
+#define IRQPIN_EXTINT3          2 /* IRQ2 pin */
+#define IRQPIN_SMC91CX          3 /* IRQ3 pin */
+#define IRQPIN_EXTINT4          4 /* IRQ4 pin */
+#define IRQPIN_PCC0             5 /* IRQ5 pin */
+#define IRQPIN_PCC2             6 /* IRQ6 pin */
+#define IRQPIN_SM501            7 /* IRQ7 pin */
+#define IRQPIN_PCCPW            7 /* IRQ7 pin */
+
+/* arch/sh/boards/se/7780/irq.c */
+void init_se7780_IRQ(void);
+
+#define __IO_PREFIX             se7780
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_SE7780_H */
diff --git a/arch/sh/include/mach-sh03/mach/io.h b/arch/sh/include/mach-sh03/mach/io.h
new file mode 100644
index 000000000000..c39c785bba94
--- /dev/null
+++ b/arch/sh/include/mach-sh03/mach/io.h
@@ -0,0 +1,25 @@
+/*
+ * include/asm-sh/sh03/io.h
+ *
+ * Copyright 2004 Interface Co.,Ltd. Saito.K
+ *
+ * IO functions for an Interface CTP/PCI-SH03
+ */
+
+#ifndef _ASM_SH_IO_SH03_H
+#define _ASM_SH_IO_SH03_H
+
+#include <linux/time.h>
+
+#define IRL0_IRQ        2
+#define IRL0_PRIORITY   13
+#define IRL1_IRQ        5
+#define IRL1_PRIORITY   10
+#define IRL2_IRQ        8
+#define IRL2_PRIORITY   7
+#define IRL3_IRQ        11
+#define IRL3_PRIORITY   4
+
+void heartbeat_sh03(void);
+
+#endif /* _ASM_SH_IO_SH03_H */
diff --git a/arch/sh/include/mach-sh03/mach/sh03.h b/arch/sh/include/mach-sh03/mach/sh03.h
new file mode 100644
index 000000000000..19c40b80428d
--- /dev/null
+++ b/arch/sh/include/mach-sh03/mach/sh03.h
@@ -0,0 +1,18 @@
+#ifndef __ASM_SH_SH03_H
+#define __ASM_SH_SH03_H
+
+/*
+ * linux/include/asm-sh/sh03/sh03.h
+ *
+ * Copyright (C) 2004  Interface Co., Ltd. Saito.K
+ *
+ * Interface CTP/PCI-SH03 support
+ */
+
+#define PA_PCI_IO       (0xbe240000)    /* PCI I/O space */
+#define PA_PCI_MEM      (0xbd000000)    /* PCI MEM space */
+
+#define PCIPAR          (0xa4000cf8)    /* PCI Config address */
+#define PCIPDR          (0xa4000cfc)    /* PCI Config data    */
+
+#endif  /* __ASM_SH_SH03_H */