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authorLinus Torvalds <torvalds@linux-foundation.org>2009-09-18 12:43:09 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-09-18 12:43:09 -0400
commit515b696b282f856c3ad1679ccd658120faa387d0 (patch)
treed9d7c1185c396617f128ca23463062308d11393b /arch/sh/include
parentfa877c71e2136bd682b45022c96d5e073ced9f58 (diff)
parent064a16dc41be879d12bd5de5d2f9d38d890e0ee7 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (262 commits) sh: mach-ecovec24: Add user debug switch support sh: Kill off unused se_skipped in alignment trap notification code. sh: Wire up HAVE_SYSCALL_TRACEPOINTS. video: sh_mobile_lcdcfb: use both register sets for display panning video: sh_mobile_lcdcfb: implement display panning sh: Fix up sh7705 flush_dcache_page() build. sh: kfr2r09: document the PLL/FLL <-> RF relationship. sh: mach-ecovec24: need asm/clock.h. sh: mach-ecovec24: deassert usb irq on boot. sh: Add KEYSC support for EcoVec24 sh: add kycr2_delay for sh_keysc sh: cpufreq: Include CPU id in info messages. sh: multi-evt support for SH-X3 proto CPU. sh: clkfwk: remove bogus set_bus_parent() from SH7709. sh: Fix the indication point of the liquid crystal of AP-325RXA(AP3300) sh: Add EcoVec24 romImage defconfig sh: USB disable process is needed if romImage boot for EcoVec24 sh: EcoVec24: add HIZA setting for LED sh: EcoVec24: write MAC address in boot sh: Add romImage support for EcoVec24 ...
Diffstat (limited to 'arch/sh/include')
-rw-r--r--arch/sh/include/asm/Kbuild2
-rw-r--r--arch/sh/include/asm/bug.h31
-rw-r--r--arch/sh/include/asm/bugs.h24
-rw-r--r--arch/sh/include/asm/cachectl.h19
-rw-r--r--arch/sh/include/asm/cacheflush.h114
-rw-r--r--arch/sh/include/asm/device.h16
-rw-r--r--arch/sh/include/asm/dma-sh.h1
-rw-r--r--arch/sh/include/asm/dwarf.h398
-rw-r--r--arch/sh/include/asm/entry-macros.S86
-rw-r--r--arch/sh/include/asm/ftrace.h8
-rw-r--r--arch/sh/include/asm/hardirq.h13
-rw-r--r--arch/sh/include/asm/heartbeat.h1
-rw-r--r--arch/sh/include/asm/hwblk.h72
-rw-r--r--arch/sh/include/asm/io.h16
-rw-r--r--arch/sh/include/asm/kdebug.h1
-rw-r--r--arch/sh/include/asm/kgdb.h3
-rw-r--r--arch/sh/include/asm/lmb.h6
-rw-r--r--arch/sh/include/asm/mmu_context.h2
-rw-r--r--arch/sh/include/asm/page.h24
-rw-r--r--arch/sh/include/asm/pgtable.h34
-rw-r--r--arch/sh/include/asm/pgtable_32.h30
-rw-r--r--arch/sh/include/asm/pgtable_64.h5
-rw-r--r--arch/sh/include/asm/processor.h15
-rw-r--r--arch/sh/include/asm/romimage-macros.h73
-rw-r--r--arch/sh/include/asm/sections.h1
-rw-r--r--arch/sh/include/asm/sh_keysc.h1
-rw-r--r--arch/sh/include/asm/stacktrace.h25
-rw-r--r--arch/sh/include/asm/suspend.h9
-rw-r--r--arch/sh/include/asm/syscall_32.h1
-rw-r--r--arch/sh/include/asm/system.h19
-rw-r--r--arch/sh/include/asm/system_32.h43
-rw-r--r--arch/sh/include/asm/system_64.h10
-rw-r--r--arch/sh/include/asm/thread_info.h11
-rw-r--r--arch/sh/include/asm/types.h2
-rw-r--r--arch/sh/include/asm/unistd_32.h2
-rw-r--r--arch/sh/include/asm/unistd_64.h2
-rw-r--r--arch/sh/include/asm/unwinder.h31
-rw-r--r--arch/sh/include/asm/vmlinux.lds.h17
-rw-r--r--arch/sh/include/asm/watchdog.h19
-rw-r--r--arch/sh/include/cpu-common/cpu/cacheflush.h44
-rw-r--r--arch/sh/include/cpu-sh2a/cpu/cacheflush.h34
-rw-r--r--arch/sh/include/cpu-sh3/cpu/cacheflush.h46
-rw-r--r--arch/sh/include/cpu-sh4/cpu/cacheflush.h43
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-sh4a.h3
-rw-r--r--arch/sh/include/cpu-sh4/cpu/freq.h4
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7722.h14
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7723.h17
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7724.h17
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7757.h243
-rw-r--r--arch/sh/include/cpu-sh5/cpu/cacheflush.h33
-rw-r--r--arch/sh/include/mach-common/mach/migor.h64
-rw-r--r--arch/sh/include/mach-common/mach/romimage.h1
-rw-r--r--arch/sh/include/mach-common/mach/sh7785lcr.h2
-rw-r--r--arch/sh/include/mach-ecovec24/mach/partner-jet-setup.txt82
-rw-r--r--arch/sh/include/mach-ecovec24/mach/romimage.h20
-rw-r--r--arch/sh/include/mach-kfr2r09/mach/kfr2r09.h21
-rw-r--r--arch/sh/include/mach-kfr2r09/mach/partner-jet-setup.txt143
-rw-r--r--arch/sh/include/mach-kfr2r09/mach/romimage.h20
-rw-r--r--arch/sh/include/mach-migor/mach/migor.h14
59 files changed, 1629 insertions, 423 deletions
diff --git a/arch/sh/include/asm/Kbuild b/arch/sh/include/asm/Kbuild
index 43910cdf78a5..e121c30f797d 100644
--- a/arch/sh/include/asm/Kbuild
+++ b/arch/sh/include/asm/Kbuild
@@ -1,6 +1,6 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2 2
3header-y += cpu-features.h 3header-y += cachectl.h cpu-features.h
4 4
5unifdef-y += unistd_32.h 5unifdef-y += unistd_32.h
6unifdef-y += unistd_64.h 6unifdef-y += unistd_64.h
diff --git a/arch/sh/include/asm/bug.h b/arch/sh/include/asm/bug.h
index c01718040166..d02c01b3e6b9 100644
--- a/arch/sh/include/asm/bug.h
+++ b/arch/sh/include/asm/bug.h
@@ -2,6 +2,7 @@
2#define __ASM_SH_BUG_H 2#define __ASM_SH_BUG_H
3 3
4#define TRAPA_BUG_OPCODE 0xc33e /* trapa #0x3e */ 4#define TRAPA_BUG_OPCODE 0xc33e /* trapa #0x3e */
5#define BUGFLAG_UNWINDER (1 << 1)
5 6
6#ifdef CONFIG_GENERIC_BUG 7#ifdef CONFIG_GENERIC_BUG
7#define HAVE_ARCH_BUG 8#define HAVE_ARCH_BUG
@@ -72,6 +73,36 @@ do { \
72 unlikely(__ret_warn_on); \ 73 unlikely(__ret_warn_on); \
73}) 74})
74 75
76#define UNWINDER_BUG() \
77do { \
78 __asm__ __volatile__ ( \
79 "1:\t.short %O0\n" \
80 _EMIT_BUG_ENTRY \
81 : \
82 : "n" (TRAPA_BUG_OPCODE), \
83 "i" (__FILE__), \
84 "i" (__LINE__), \
85 "i" (BUGFLAG_UNWINDER), \
86 "i" (sizeof(struct bug_entry))); \
87} while (0)
88
89#define UNWINDER_BUG_ON(x) ({ \
90 int __ret_unwinder_on = !!(x); \
91 if (__builtin_constant_p(__ret_unwinder_on)) { \
92 if (__ret_unwinder_on) \
93 UNWINDER_BUG(); \
94 } else { \
95 if (unlikely(__ret_unwinder_on)) \
96 UNWINDER_BUG(); \
97 } \
98 unlikely(__ret_unwinder_on); \
99})
100
101#else
102
103#define UNWINDER_BUG BUG
104#define UNWINDER_BUG_ON BUG_ON
105
75#endif /* CONFIG_GENERIC_BUG */ 106#endif /* CONFIG_GENERIC_BUG */
76 107
77#include <asm-generic/bug.h> 108#include <asm-generic/bug.h>
diff --git a/arch/sh/include/asm/bugs.h b/arch/sh/include/asm/bugs.h
index 4924ff6f5439..46260fcbdf4b 100644
--- a/arch/sh/include/asm/bugs.h
+++ b/arch/sh/include/asm/bugs.h
@@ -21,25 +21,25 @@ static void __init check_bugs(void)
21 21
22 current_cpu_data.loops_per_jiffy = loops_per_jiffy; 22 current_cpu_data.loops_per_jiffy = loops_per_jiffy;
23 23
24 switch (current_cpu_data.type) { 24 switch (current_cpu_data.family) {
25 case CPU_SH7619: 25 case CPU_FAMILY_SH2:
26 *p++ = '2'; 26 *p++ = '2';
27 break; 27 break;
28 case CPU_SH7201 ... CPU_MXG: 28 case CPU_FAMILY_SH2A:
29 *p++ = '2'; 29 *p++ = '2';
30 *p++ = 'a'; 30 *p++ = 'a';
31 break; 31 break;
32 case CPU_SH7705 ... CPU_SH7729: 32 case CPU_FAMILY_SH3:
33 *p++ = '3'; 33 *p++ = '3';
34 break; 34 break;
35 case CPU_SH7750 ... CPU_SH4_501: 35 case CPU_FAMILY_SH4:
36 *p++ = '4'; 36 *p++ = '4';
37 break; 37 break;
38 case CPU_SH7763 ... CPU_SHX3: 38 case CPU_FAMILY_SH4A:
39 *p++ = '4'; 39 *p++ = '4';
40 *p++ = 'a'; 40 *p++ = 'a';
41 break; 41 break;
42 case CPU_SH7343 ... CPU_SH7366: 42 case CPU_FAMILY_SH4AL_DSP:
43 *p++ = '4'; 43 *p++ = '4';
44 *p++ = 'a'; 44 *p++ = 'a';
45 *p++ = 'l'; 45 *p++ = 'l';
@@ -48,15 +48,15 @@ static void __init check_bugs(void)
48 *p++ = 's'; 48 *p++ = 's';
49 *p++ = 'p'; 49 *p++ = 'p';
50 break; 50 break;
51 case CPU_SH5_101 ... CPU_SH5_103: 51 case CPU_FAMILY_SH5:
52 *p++ = '6'; 52 *p++ = '6';
53 *p++ = '4'; 53 *p++ = '4';
54 break; 54 break;
55 case CPU_SH_NONE: 55 case CPU_FAMILY_UNKNOWN:
56 /* 56 /*
57 * Specifically use CPU_SH_NONE rather than default:, 57 * Specifically use CPU_FAMILY_UNKNOWN rather than
58 * so we're able to have the compiler whine about 58 * default:, so we're able to have the compiler whine
59 * unhandled enumerations. 59 * about unhandled enumerations.
60 */ 60 */
61 break; 61 break;
62 } 62 }
diff --git a/arch/sh/include/asm/cachectl.h b/arch/sh/include/asm/cachectl.h
new file mode 100644
index 000000000000..6ffb4b7a212e
--- /dev/null
+++ b/arch/sh/include/asm/cachectl.h
@@ -0,0 +1,19 @@
1#ifndef _SH_CACHECTL_H
2#define _SH_CACHECTL_H
3
4/* Definitions for the cacheflush system call. */
5
6#define CACHEFLUSH_D_INVAL 0x1 /* invalidate (without write back) */
7#define CACHEFLUSH_D_WB 0x2 /* write back (without invalidate) */
8#define CACHEFLUSH_D_PURGE 0x3 /* writeback and invalidate */
9
10#define CACHEFLUSH_I 0x4
11
12/*
13 * Options for cacheflush system call
14 */
15#define ICACHE CACHEFLUSH_I /* flush instruction cache */
16#define DCACHE CACHEFLUSH_D_PURGE /* writeback and flush data cache */
17#define BCACHE (ICACHE|DCACHE) /* flush both caches */
18
19#endif /* _SH_CACHECTL_H */
diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h
index 4c5462daa74c..c29918f3c819 100644
--- a/arch/sh/include/asm/cacheflush.h
+++ b/arch/sh/include/asm/cacheflush.h
@@ -3,45 +3,65 @@
3 3
4#ifdef __KERNEL__ 4#ifdef __KERNEL__
5 5
6#ifdef CONFIG_CACHE_OFF 6#include <linux/mm.h>
7
7/* 8/*
8 * Nothing to do when the cache is disabled, initial flush and explicit 9 * Cache flushing:
9 * disabling is handled at CPU init time. 10 *
11 * - flush_cache_all() flushes entire cache
12 * - flush_cache_mm(mm) flushes the specified mm context's cache lines
13 * - flush_cache_dup mm(mm) handles cache flushing when forking
14 * - flush_cache_page(mm, vmaddr, pfn) flushes a single page
15 * - flush_cache_range(vma, start, end) flushes a range of pages
10 * 16 *
11 * See arch/sh/kernel/cpu/init.c:cache_init(). 17 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
18 * - flush_icache_range(start, end) flushes(invalidates) a range for icache
19 * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
20 * - flush_cache_sigtramp(vaddr) flushes the signal trampoline
12 */ 21 */
13#define p3_cache_init() do { } while (0) 22extern void (*local_flush_cache_all)(void *args);
14#define flush_cache_all() do { } while (0) 23extern void (*local_flush_cache_mm)(void *args);
15#define flush_cache_mm(mm) do { } while (0) 24extern void (*local_flush_cache_dup_mm)(void *args);
16#define flush_cache_dup_mm(mm) do { } while (0) 25extern void (*local_flush_cache_page)(void *args);
17#define flush_cache_range(vma, start, end) do { } while (0) 26extern void (*local_flush_cache_range)(void *args);
18#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) 27extern void (*local_flush_dcache_page)(void *args);
19#define flush_dcache_page(page) do { } while (0) 28extern void (*local_flush_icache_range)(void *args);
20#define flush_icache_range(start, end) do { } while (0) 29extern void (*local_flush_icache_page)(void *args);
21#define flush_icache_page(vma,pg) do { } while (0) 30extern void (*local_flush_cache_sigtramp)(void *args);
22#define flush_dcache_mmap_lock(mapping) do { } while (0)
23#define flush_dcache_mmap_unlock(mapping) do { } while (0)
24#define flush_cache_sigtramp(vaddr) do { } while (0)
25#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
26#define __flush_wback_region(start, size) do { (void)(start); } while (0)
27#define __flush_purge_region(start, size) do { (void)(start); } while (0)
28#define __flush_invalidate_region(start, size) do { (void)(start); } while (0)
29#else
30#include <cpu/cacheflush.h>
31 31
32/* 32static inline void cache_noop(void *args) { }
33 * Consistent DMA requires that the __flush_xxx() primitives must be set 33
34 * for any of the enabled non-coherent caches (most of the UP CPUs), 34extern void (*__flush_wback_region)(void *start, int size);
35 * regardless of PIPT or VIPT cache configurations. 35extern void (*__flush_purge_region)(void *start, int size);
36 */ 36extern void (*__flush_invalidate_region)(void *start, int size);
37
38extern void flush_cache_all(void);
39extern void flush_cache_mm(struct mm_struct *mm);
40extern void flush_cache_dup_mm(struct mm_struct *mm);
41extern void flush_cache_page(struct vm_area_struct *vma,
42 unsigned long addr, unsigned long pfn);
43extern void flush_cache_range(struct vm_area_struct *vma,
44 unsigned long start, unsigned long end);
45extern void flush_dcache_page(struct page *page);
46extern void flush_icache_range(unsigned long start, unsigned long end);
47extern void flush_icache_page(struct vm_area_struct *vma,
48 struct page *page);
49extern void flush_cache_sigtramp(unsigned long address);
50
51struct flusher_data {
52 struct vm_area_struct *vma;
53 unsigned long addr1, addr2;
54};
37 55
38/* Flush (write-back only) a region (smaller than a page) */ 56#define ARCH_HAS_FLUSH_ANON_PAGE
39extern void __flush_wback_region(void *start, int size); 57extern void __flush_anon_page(struct page *page, unsigned long);
40/* Flush (write-back & invalidate) a region (smaller than a page) */ 58
41extern void __flush_purge_region(void *start, int size); 59static inline void flush_anon_page(struct vm_area_struct *vma,
42/* Flush (invalidate only) a region (smaller than a page) */ 60 struct page *page, unsigned long vmaddr)
43extern void __flush_invalidate_region(void *start, int size); 61{
44#endif 62 if (boot_cpu_data.dcache.n_aliases && PageAnon(page))
63 __flush_anon_page(page, vmaddr);
64}
45 65
46#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE 66#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
47static inline void flush_kernel_dcache_page(struct page *page) 67static inline void flush_kernel_dcache_page(struct page *page)
@@ -49,7 +69,6 @@ static inline void flush_kernel_dcache_page(struct page *page)
49 flush_dcache_page(page); 69 flush_dcache_page(page);
50} 70}
51 71
52#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_CACHE_OFF)
53extern void copy_to_user_page(struct vm_area_struct *vma, 72extern void copy_to_user_page(struct vm_area_struct *vma,
54 struct page *page, unsigned long vaddr, void *dst, const void *src, 73 struct page *page, unsigned long vaddr, void *dst, const void *src,
55 unsigned long len); 74 unsigned long len);
@@ -57,23 +76,20 @@ extern void copy_to_user_page(struct vm_area_struct *vma,
57extern void copy_from_user_page(struct vm_area_struct *vma, 76extern void copy_from_user_page(struct vm_area_struct *vma,
58 struct page *page, unsigned long vaddr, void *dst, const void *src, 77 struct page *page, unsigned long vaddr, void *dst, const void *src,
59 unsigned long len); 78 unsigned long len);
60#else
61#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
62 do { \
63 flush_cache_page(vma, vaddr, page_to_pfn(page));\
64 memcpy(dst, src, len); \
65 flush_icache_user_range(vma, page, vaddr, len); \
66 } while (0)
67
68#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
69 do { \
70 flush_cache_page(vma, vaddr, page_to_pfn(page));\
71 memcpy(dst, src, len); \
72 } while (0)
73#endif
74 79
75#define flush_cache_vmap(start, end) flush_cache_all() 80#define flush_cache_vmap(start, end) flush_cache_all()
76#define flush_cache_vunmap(start, end) flush_cache_all() 81#define flush_cache_vunmap(start, end) flush_cache_all()
77 82
83#define flush_dcache_mmap_lock(mapping) do { } while (0)
84#define flush_dcache_mmap_unlock(mapping) do { } while (0)
85
86void kmap_coherent_init(void);
87void *kmap_coherent(struct page *page, unsigned long addr);
88void kunmap_coherent(void *kvaddr);
89
90#define PG_dcache_dirty PG_arch_1
91
92void cpu_cache_init(void);
93
78#endif /* __KERNEL__ */ 94#endif /* __KERNEL__ */
79#endif /* __ASM_SH_CACHEFLUSH_H */ 95#endif /* __ASM_SH_CACHEFLUSH_H */
diff --git a/arch/sh/include/asm/device.h b/arch/sh/include/asm/device.h
index 8688a88303ee..b16debfe8c1e 100644
--- a/arch/sh/include/asm/device.h
+++ b/arch/sh/include/asm/device.h
@@ -3,7 +3,9 @@
3 * 3 *
4 * This file is released under the GPLv2 4 * This file is released under the GPLv2
5 */ 5 */
6#include <asm-generic/device.h> 6
7struct dev_archdata {
8};
7 9
8struct platform_device; 10struct platform_device;
9/* allocate contiguous memory chunk and fill in struct resource */ 11/* allocate contiguous memory chunk and fill in struct resource */
@@ -12,3 +14,15 @@ int platform_resource_setup_memory(struct platform_device *pdev,
12 14
13void plat_early_device_setup(void); 15void plat_early_device_setup(void);
14 16
17#define PDEV_ARCHDATA_FLAG_INIT 0
18#define PDEV_ARCHDATA_FLAG_IDLE 1
19#define PDEV_ARCHDATA_FLAG_SUSP 2
20
21struct pdev_archdata {
22 int hwblk_id;
23#ifdef CONFIG_PM_RUNTIME
24 unsigned long flags;
25 struct list_head entry;
26 struct mutex mutex;
27#endif
28};
diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h
index 0c8f8e14622a..68a5f4cb0343 100644
--- a/arch/sh/include/asm/dma-sh.h
+++ b/arch/sh/include/asm/dma-sh.h
@@ -16,6 +16,7 @@
16 16
17/* DMAOR contorl: The DMAOR access size is different by CPU.*/ 17/* DMAOR contorl: The DMAOR access size is different by CPU.*/
18#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \ 18#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
19 defined(CONFIG_CPU_SUBTYPE_SH7724) || \
19 defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 20 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
20 defined(CONFIG_CPU_SUBTYPE_SH7785) 21 defined(CONFIG_CPU_SUBTYPE_SH7785)
21#define dmaor_read_reg(n) \ 22#define dmaor_read_reg(n) \
diff --git a/arch/sh/include/asm/dwarf.h b/arch/sh/include/asm/dwarf.h
new file mode 100644
index 000000000000..ced6795891a6
--- /dev/null
+++ b/arch/sh/include/asm/dwarf.h
@@ -0,0 +1,398 @@
1/*
2 * Copyright (C) 2009 Matt Fleming <matt@console-pimps.org>
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 */
9#ifndef __ASM_SH_DWARF_H
10#define __ASM_SH_DWARF_H
11
12#ifdef CONFIG_DWARF_UNWINDER
13
14/*
15 * DWARF expression operations
16 */
17#define DW_OP_addr 0x03
18#define DW_OP_deref 0x06
19#define DW_OP_const1u 0x08
20#define DW_OP_const1s 0x09
21#define DW_OP_const2u 0x0a
22#define DW_OP_const2s 0x0b
23#define DW_OP_const4u 0x0c
24#define DW_OP_const4s 0x0d
25#define DW_OP_const8u 0x0e
26#define DW_OP_const8s 0x0f
27#define DW_OP_constu 0x10
28#define DW_OP_consts 0x11
29#define DW_OP_dup 0x12
30#define DW_OP_drop 0x13
31#define DW_OP_over 0x14
32#define DW_OP_pick 0x15
33#define DW_OP_swap 0x16
34#define DW_OP_rot 0x17
35#define DW_OP_xderef 0x18
36#define DW_OP_abs 0x19
37#define DW_OP_and 0x1a
38#define DW_OP_div 0x1b
39#define DW_OP_minus 0x1c
40#define DW_OP_mod 0x1d
41#define DW_OP_mul 0x1e
42#define DW_OP_neg 0x1f
43#define DW_OP_not 0x20
44#define DW_OP_or 0x21
45#define DW_OP_plus 0x22
46#define DW_OP_plus_uconst 0x23
47#define DW_OP_shl 0x24
48#define DW_OP_shr 0x25
49#define DW_OP_shra 0x26
50#define DW_OP_xor 0x27
51#define DW_OP_skip 0x2f
52#define DW_OP_bra 0x28
53#define DW_OP_eq 0x29
54#define DW_OP_ge 0x2a
55#define DW_OP_gt 0x2b
56#define DW_OP_le 0x2c
57#define DW_OP_lt 0x2d
58#define DW_OP_ne 0x2e
59#define DW_OP_lit0 0x30
60#define DW_OP_lit1 0x31
61#define DW_OP_lit2 0x32
62#define DW_OP_lit3 0x33
63#define DW_OP_lit4 0x34
64#define DW_OP_lit5 0x35
65#define DW_OP_lit6 0x36
66#define DW_OP_lit7 0x37
67#define DW_OP_lit8 0x38
68#define DW_OP_lit9 0x39
69#define DW_OP_lit10 0x3a
70#define DW_OP_lit11 0x3b
71#define DW_OP_lit12 0x3c
72#define DW_OP_lit13 0x3d
73#define DW_OP_lit14 0x3e
74#define DW_OP_lit15 0x3f
75#define DW_OP_lit16 0x40
76#define DW_OP_lit17 0x41
77#define DW_OP_lit18 0x42
78#define DW_OP_lit19 0x43
79#define DW_OP_lit20 0x44
80#define DW_OP_lit21 0x45
81#define DW_OP_lit22 0x46
82#define DW_OP_lit23 0x47
83#define DW_OP_lit24 0x48
84#define DW_OP_lit25 0x49
85#define DW_OP_lit26 0x4a
86#define DW_OP_lit27 0x4b
87#define DW_OP_lit28 0x4c
88#define DW_OP_lit29 0x4d
89#define DW_OP_lit30 0x4e
90#define DW_OP_lit31 0x4f
91#define DW_OP_reg0 0x50
92#define DW_OP_reg1 0x51
93#define DW_OP_reg2 0x52
94#define DW_OP_reg3 0x53
95#define DW_OP_reg4 0x54
96#define DW_OP_reg5 0x55
97#define DW_OP_reg6 0x56
98#define DW_OP_reg7 0x57
99#define DW_OP_reg8 0x58
100#define DW_OP_reg9 0x59
101#define DW_OP_reg10 0x5a
102#define DW_OP_reg11 0x5b
103#define DW_OP_reg12 0x5c
104#define DW_OP_reg13 0x5d
105#define DW_OP_reg14 0x5e
106#define DW_OP_reg15 0x5f
107#define DW_OP_reg16 0x60
108#define DW_OP_reg17 0x61
109#define DW_OP_reg18 0x62
110#define DW_OP_reg19 0x63
111#define DW_OP_reg20 0x64
112#define DW_OP_reg21 0x65
113#define DW_OP_reg22 0x66
114#define DW_OP_reg23 0x67
115#define DW_OP_reg24 0x68
116#define DW_OP_reg25 0x69
117#define DW_OP_reg26 0x6a
118#define DW_OP_reg27 0x6b
119#define DW_OP_reg28 0x6c
120#define DW_OP_reg29 0x6d
121#define DW_OP_reg30 0x6e
122#define DW_OP_reg31 0x6f
123#define DW_OP_breg0 0x70
124#define DW_OP_breg1 0x71
125#define DW_OP_breg2 0x72
126#define DW_OP_breg3 0x73
127#define DW_OP_breg4 0x74
128#define DW_OP_breg5 0x75
129#define DW_OP_breg6 0x76
130#define DW_OP_breg7 0x77
131#define DW_OP_breg8 0x78
132#define DW_OP_breg9 0x79
133#define DW_OP_breg10 0x7a
134#define DW_OP_breg11 0x7b
135#define DW_OP_breg12 0x7c
136#define DW_OP_breg13 0x7d
137#define DW_OP_breg14 0x7e
138#define DW_OP_breg15 0x7f
139#define DW_OP_breg16 0x80
140#define DW_OP_breg17 0x81
141#define DW_OP_breg18 0x82
142#define DW_OP_breg19 0x83
143#define DW_OP_breg20 0x84
144#define DW_OP_breg21 0x85
145#define DW_OP_breg22 0x86
146#define DW_OP_breg23 0x87
147#define DW_OP_breg24 0x88
148#define DW_OP_breg25 0x89
149#define DW_OP_breg26 0x8a
150#define DW_OP_breg27 0x8b
151#define DW_OP_breg28 0x8c
152#define DW_OP_breg29 0x8d
153#define DW_OP_breg30 0x8e
154#define DW_OP_breg31 0x8f
155#define DW_OP_regx 0x90
156#define DW_OP_fbreg 0x91
157#define DW_OP_bregx 0x92
158#define DW_OP_piece 0x93
159#define DW_OP_deref_size 0x94
160#define DW_OP_xderef_size 0x95
161#define DW_OP_nop 0x96
162#define DW_OP_push_object_address 0x97
163#define DW_OP_call2 0x98
164#define DW_OP_call4 0x99
165#define DW_OP_call_ref 0x9a
166#define DW_OP_form_tls_address 0x9b
167#define DW_OP_call_frame_cfa 0x9c
168#define DW_OP_bit_piece 0x9d
169#define DW_OP_lo_user 0xe0
170#define DW_OP_hi_user 0xff
171
172/*
173 * Addresses used in FDE entries in the .eh_frame section may be encoded
174 * using one of the following encodings.
175 */
176#define DW_EH_PE_absptr 0x00
177#define DW_EH_PE_omit 0xff
178#define DW_EH_PE_uleb128 0x01
179#define DW_EH_PE_udata2 0x02
180#define DW_EH_PE_udata4 0x03
181#define DW_EH_PE_udata8 0x04
182#define DW_EH_PE_sleb128 0x09
183#define DW_EH_PE_sdata2 0x0a
184#define DW_EH_PE_sdata4 0x0b
185#define DW_EH_PE_sdata8 0x0c
186#define DW_EH_PE_signed 0x09
187
188#define DW_EH_PE_pcrel 0x10
189
190/*
191 * The architecture-specific register number that contains the return
192 * address in the .debug_frame table.
193 */
194#define DWARF_ARCH_RA_REG 17
195
196#ifndef __ASSEMBLY__
197/*
198 * Read either the frame pointer (r14) or the stack pointer (r15).
199 * NOTE: this MUST be inlined.
200 */
201static __always_inline unsigned long dwarf_read_arch_reg(unsigned int reg)
202{
203 unsigned long value = 0;
204
205 switch (reg) {
206 case 14:
207 __asm__ __volatile__("mov r14, %0\n" : "=r" (value));
208 break;
209 case 15:
210 __asm__ __volatile__("mov r15, %0\n" : "=r" (value));
211 break;
212 default:
213 BUG();
214 }
215
216 return value;
217}
218
219/**
220 * dwarf_cie - Common Information Entry
221 */
222struct dwarf_cie {
223 unsigned long length;
224 unsigned long cie_id;
225 unsigned char version;
226 const char *augmentation;
227 unsigned int code_alignment_factor;
228 int data_alignment_factor;
229
230 /* Which column in the rule table represents return addr of func. */
231 unsigned int return_address_reg;
232
233 unsigned char *initial_instructions;
234 unsigned char *instructions_end;
235
236 unsigned char encoding;
237
238 unsigned long cie_pointer;
239
240 struct list_head link;
241
242 unsigned long flags;
243#define DWARF_CIE_Z_AUGMENTATION (1 << 0)
244};
245
246/**
247 * dwarf_fde - Frame Description Entry
248 */
249struct dwarf_fde {
250 unsigned long length;
251 unsigned long cie_pointer;
252 struct dwarf_cie *cie;
253 unsigned long initial_location;
254 unsigned long address_range;
255 unsigned char *instructions;
256 unsigned char *end;
257 struct list_head link;
258};
259
260/**
261 * dwarf_frame - DWARF information for a frame in the call stack
262 */
263struct dwarf_frame {
264 struct dwarf_frame *prev, *next;
265
266 unsigned long pc;
267
268 struct list_head reg_list;
269
270 unsigned long cfa;
271
272 /* Valid when DW_FRAME_CFA_REG_OFFSET is set in flags */
273 unsigned int cfa_register;
274 unsigned int cfa_offset;
275
276 /* Valid when DW_FRAME_CFA_REG_EXP is set in flags */
277 unsigned char *cfa_expr;
278 unsigned int cfa_expr_len;
279
280 unsigned long flags;
281#define DWARF_FRAME_CFA_REG_OFFSET (1 << 0)
282#define DWARF_FRAME_CFA_REG_EXP (1 << 1)
283
284 unsigned long return_addr;
285};
286
287/**
288 * dwarf_reg - DWARF register
289 * @flags: Describes how to calculate the value of this register
290 */
291struct dwarf_reg {
292 struct list_head link;
293
294 unsigned int number;
295
296 unsigned long addr;
297 unsigned long flags;
298#define DWARF_REG_OFFSET (1 << 0)
299#define DWARF_VAL_OFFSET (1 << 1)
300#define DWARF_UNDEFINED (1 << 2)
301};
302
303/*
304 * Call Frame instruction opcodes.
305 */
306#define DW_CFA_advance_loc 0x40
307#define DW_CFA_offset 0x80
308#define DW_CFA_restore 0xc0
309#define DW_CFA_nop 0x00
310#define DW_CFA_set_loc 0x01
311#define DW_CFA_advance_loc1 0x02
312#define DW_CFA_advance_loc2 0x03
313#define DW_CFA_advance_loc4 0x04
314#define DW_CFA_offset_extended 0x05
315#define DW_CFA_restore_extended 0x06
316#define DW_CFA_undefined 0x07
317#define DW_CFA_same_value 0x08
318#define DW_CFA_register 0x09
319#define DW_CFA_remember_state 0x0a
320#define DW_CFA_restore_state 0x0b
321#define DW_CFA_def_cfa 0x0c
322#define DW_CFA_def_cfa_register 0x0d
323#define DW_CFA_def_cfa_offset 0x0e
324#define DW_CFA_def_cfa_expression 0x0f
325#define DW_CFA_expression 0x10
326#define DW_CFA_offset_extended_sf 0x11
327#define DW_CFA_def_cfa_sf 0x12
328#define DW_CFA_def_cfa_offset_sf 0x13
329#define DW_CFA_val_offset 0x14
330#define DW_CFA_val_offset_sf 0x15
331#define DW_CFA_val_expression 0x16
332#define DW_CFA_lo_user 0x1c
333#define DW_CFA_hi_user 0x3f
334
335/* GNU extension opcodes */
336#define DW_CFA_GNU_args_size 0x2e
337#define DW_CFA_GNU_negative_offset_extended 0x2f
338
339/*
340 * Some call frame instructions encode their operands in the opcode. We
341 * need some helper functions to extract both the opcode and operands
342 * from an instruction.
343 */
344static inline unsigned int DW_CFA_opcode(unsigned long insn)
345{
346 return (insn & 0xc0);
347}
348
349static inline unsigned int DW_CFA_operand(unsigned long insn)
350{
351 return (insn & 0x3f);
352}
353
354#define DW_EH_FRAME_CIE 0 /* .eh_frame CIE IDs are 0 */
355#define DW_CIE_ID 0xffffffff
356#define DW64_CIE_ID 0xffffffffffffffffULL
357
358/*
359 * DWARF FDE/CIE length field values.
360 */
361#define DW_EXT_LO 0xfffffff0
362#define DW_EXT_HI 0xffffffff
363#define DW_EXT_DWARF64 DW_EXT_HI
364
365extern struct dwarf_frame *dwarf_unwind_stack(unsigned long,
366 struct dwarf_frame *);
367#endif /* !__ASSEMBLY__ */
368
369#define CFI_STARTPROC .cfi_startproc
370#define CFI_ENDPROC .cfi_endproc
371#define CFI_DEF_CFA .cfi_def_cfa
372#define CFI_REGISTER .cfi_register
373#define CFI_REL_OFFSET .cfi_rel_offset
374#define CFI_UNDEFINED .cfi_undefined
375
376#else
377
378/*
379 * Use the asm comment character to ignore the rest of the line.
380 */
381#define CFI_IGNORE !
382
383#define CFI_STARTPROC CFI_IGNORE
384#define CFI_ENDPROC CFI_IGNORE
385#define CFI_DEF_CFA CFI_IGNORE
386#define CFI_REGISTER CFI_IGNORE
387#define CFI_REL_OFFSET CFI_IGNORE
388#define CFI_UNDEFINED CFI_IGNORE
389
390#ifndef __ASSEMBLY__
391static inline void dwarf_unwinder_init(void)
392{
393}
394#endif
395
396#endif /* CONFIG_DWARF_UNWINDER */
397
398#endif /* __ASM_SH_DWARF_H */
diff --git a/arch/sh/include/asm/entry-macros.S b/arch/sh/include/asm/entry-macros.S
index 3a4752a65722..cc43a55e1fcf 100644
--- a/arch/sh/include/asm/entry-macros.S
+++ b/arch/sh/include/asm/entry-macros.S
@@ -7,7 +7,7 @@
7 .endm 7 .endm
8 8
9 .macro sti 9 .macro sti
10 mov #0xf0, r11 10 mov #0xfffffff0, r11
11 extu.b r11, r11 11 extu.b r11, r11
12 not r11, r11 12 not r11, r11
13 stc sr, r10 13 stc sr, r10
@@ -31,8 +31,92 @@
31#endif 31#endif
32 .endm 32 .endm
33 33
34#ifdef CONFIG_TRACE_IRQFLAGS
35
36 .macro TRACE_IRQS_ON
37 mov.l r0, @-r15
38 mov.l r1, @-r15
39 mov.l r2, @-r15
40 mov.l r3, @-r15
41 mov.l r4, @-r15
42 mov.l r5, @-r15
43 mov.l r6, @-r15
44 mov.l r7, @-r15
45
46 mov.l 7834f, r0
47 jsr @r0
48 nop
49
50 mov.l @r15+, r7
51 mov.l @r15+, r6
52 mov.l @r15+, r5
53 mov.l @r15+, r4
54 mov.l @r15+, r3
55 mov.l @r15+, r2
56 mov.l @r15+, r1
57 mov.l @r15+, r0
58 mov.l 7834f, r0
59
60 bra 7835f
61 nop
62 .balign 4
637834: .long trace_hardirqs_on
647835:
65 .endm
66 .macro TRACE_IRQS_OFF
67
68 mov.l r0, @-r15
69 mov.l r1, @-r15
70 mov.l r2, @-r15
71 mov.l r3, @-r15
72 mov.l r4, @-r15
73 mov.l r5, @-r15
74 mov.l r6, @-r15
75 mov.l r7, @-r15
76
77 mov.l 7834f, r0
78 jsr @r0
79 nop
80
81 mov.l @r15+, r7
82 mov.l @r15+, r6
83 mov.l @r15+, r5
84 mov.l @r15+, r4
85 mov.l @r15+, r3
86 mov.l @r15+, r2
87 mov.l @r15+, r1
88 mov.l @r15+, r0
89 mov.l 7834f, r0
90
91 bra 7835f
92 nop
93 .balign 4
947834: .long trace_hardirqs_off
957835:
96 .endm
97
98#else
99 .macro TRACE_IRQS_ON
100 .endm
101
102 .macro TRACE_IRQS_OFF
103 .endm
104#endif
105
34#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4) 106#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4)
35# define PREF(x) pref @x 107# define PREF(x) pref @x
36#else 108#else
37# define PREF(x) nop 109# define PREF(x) nop
38#endif 110#endif
111
112 /*
113 * Macro for use within assembly. Because the DWARF unwinder
114 * needs to use the frame register to unwind the stack, we
115 * need to setup r14 with the value of the stack pointer as
116 * the return address is usually on the stack somewhere.
117 */
118 .macro setup_frame_reg
119#ifdef CONFIG_DWARF_UNWINDER
120 mov r15, r14
121#endif
122 .endm
diff --git a/arch/sh/include/asm/ftrace.h b/arch/sh/include/asm/ftrace.h
index 8fea7d8c8258..12f3a31f20af 100644
--- a/arch/sh/include/asm/ftrace.h
+++ b/arch/sh/include/asm/ftrace.h
@@ -4,6 +4,7 @@
4#ifdef CONFIG_FUNCTION_TRACER 4#ifdef CONFIG_FUNCTION_TRACER
5 5
6#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */ 6#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
7#define FTRACE_SYSCALL_MAX NR_syscalls
7 8
8#ifndef __ASSEMBLY__ 9#ifndef __ASSEMBLY__
9extern void mcount(void); 10extern void mcount(void);
@@ -11,10 +12,13 @@ extern void mcount(void);
11#define MCOUNT_ADDR ((long)(mcount)) 12#define MCOUNT_ADDR ((long)(mcount))
12 13
13#ifdef CONFIG_DYNAMIC_FTRACE 14#ifdef CONFIG_DYNAMIC_FTRACE
14#define CALLER_ADDR ((long)(ftrace_caller)) 15#define CALL_ADDR ((long)(ftrace_call))
15#define STUB_ADDR ((long)(ftrace_stub)) 16#define STUB_ADDR ((long)(ftrace_stub))
17#define GRAPH_ADDR ((long)(ftrace_graph_call))
18#define CALLER_ADDR ((long)(ftrace_caller))
16 19
17#define MCOUNT_INSN_OFFSET ((STUB_ADDR - CALLER_ADDR) >> 1) 20#define MCOUNT_INSN_OFFSET ((STUB_ADDR - CALL_ADDR) - 4)
21#define GRAPH_INSN_OFFSET ((CALLER_ADDR - GRAPH_ADDR) - 4)
18 22
19struct dyn_arch_ftrace { 23struct dyn_arch_ftrace {
20 /* No extra data needed on sh */ 24 /* No extra data needed on sh */
diff --git a/arch/sh/include/asm/hardirq.h b/arch/sh/include/asm/hardirq.h
index 715ee237fc77..a5be4afa790b 100644
--- a/arch/sh/include/asm/hardirq.h
+++ b/arch/sh/include/asm/hardirq.h
@@ -1,16 +1,9 @@
1#ifndef __ASM_SH_HARDIRQ_H 1#ifndef __ASM_SH_HARDIRQ_H
2#define __ASM_SH_HARDIRQ_H 2#define __ASM_SH_HARDIRQ_H
3 3
4#include <linux/threads.h>
5#include <linux/irq.h>
6
7/* entry.S is sensitive to the offsets of these fields */
8typedef struct {
9 unsigned int __softirq_pending;
10} ____cacheline_aligned irq_cpustat_t;
11
12#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
13
14extern void ack_bad_irq(unsigned int irq); 4extern void ack_bad_irq(unsigned int irq);
5#define ack_bad_irq ack_bad_irq
6
7#include <asm-generic/hardirq.h>
15 8
16#endif /* __ASM_SH_HARDIRQ_H */ 9#endif /* __ASM_SH_HARDIRQ_H */
diff --git a/arch/sh/include/asm/heartbeat.h b/arch/sh/include/asm/heartbeat.h
index 724a43ed245e..caaafe5a3ef1 100644
--- a/arch/sh/include/asm/heartbeat.h
+++ b/arch/sh/include/asm/heartbeat.h
@@ -11,6 +11,7 @@ struct heartbeat_data {
11 unsigned int nr_bits; 11 unsigned int nr_bits;
12 struct timer_list timer; 12 struct timer_list timer;
13 unsigned int regsize; 13 unsigned int regsize;
14 unsigned int mask;
14 unsigned long flags; 15 unsigned long flags;
15}; 16};
16 17
diff --git a/arch/sh/include/asm/hwblk.h b/arch/sh/include/asm/hwblk.h
new file mode 100644
index 000000000000..5d3ccae4202b
--- /dev/null
+++ b/arch/sh/include/asm/hwblk.h
@@ -0,0 +1,72 @@
1#ifndef __ASM_SH_HWBLK_H
2#define __ASM_SH_HWBLK_H
3
4#include <asm/clock.h>
5#include <asm/io.h>
6
7#define HWBLK_CNT_USAGE 0
8#define HWBLK_CNT_IDLE 1
9#define HWBLK_CNT_DEVICES 2
10#define HWBLK_CNT_NR 3
11
12#define HWBLK_AREA_FLAG_PARENT (1 << 0) /* valid parent */
13
14#define HWBLK_AREA(_flags, _parent) \
15{ \
16 .flags = _flags, \
17 .parent = _parent, \
18}
19
20struct hwblk_area {
21 int cnt[HWBLK_CNT_NR];
22 unsigned char parent;
23 unsigned char flags;
24};
25
26#define HWBLK(_mstp, _bit, _area) \
27{ \
28 .mstp = (void __iomem *)_mstp, \
29 .bit = _bit, \
30 .area = _area, \
31}
32
33struct hwblk {
34 void __iomem *mstp;
35 unsigned char bit;
36 unsigned char area;
37 int cnt[HWBLK_CNT_NR];
38};
39
40struct hwblk_info {
41 struct hwblk_area *areas;
42 int nr_areas;
43 struct hwblk *hwblks;
44 int nr_hwblks;
45};
46
47/* Should be defined by processor-specific code */
48int arch_hwblk_init(void);
49int arch_hwblk_sleep_mode(void);
50
51int hwblk_register(struct hwblk_info *info);
52int hwblk_init(void);
53
54void hwblk_enable(struct hwblk_info *info, int hwblk);
55void hwblk_disable(struct hwblk_info *info, int hwblk);
56
57void hwblk_cnt_inc(struct hwblk_info *info, int hwblk, int cnt);
58void hwblk_cnt_dec(struct hwblk_info *info, int hwblk, int cnt);
59
60/* allow clocks to enable and disable hardware blocks */
61#define SH_HWBLK_CLK(_name, _id, _parent, _hwblk, _flags) \
62{ \
63 .name = _name, \
64 .id = _id, \
65 .parent = _parent, \
66 .arch_flags = _hwblk, \
67 .flags = _flags, \
68}
69
70int sh_hwblk_clk_register(struct clk *clks, int nr);
71
72#endif /* __ASM_SH_HWBLK_H */
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 25348141674b..5be45ea4dfec 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -92,8 +92,12 @@
92 92
93static inline void ctrl_delay(void) 93static inline void ctrl_delay(void)
94{ 94{
95#ifdef P2SEG 95#ifdef CONFIG_CPU_SH4
96 __raw_readw(CCN_PVR);
97#elif defined(P2SEG)
96 __raw_readw(P2SEG); 98 __raw_readw(P2SEG);
99#else
100#error "Need a dummy address for delay"
97#endif 101#endif
98} 102}
99 103
@@ -146,6 +150,7 @@ __BUILD_MEMORY_STRING(q, u64)
146#define readl_relaxed(a) readl(a) 150#define readl_relaxed(a) readl(a)
147#define readq_relaxed(a) readq(a) 151#define readq_relaxed(a) readq(a)
148 152
153#ifndef CONFIG_GENERIC_IOMAP
149/* Simple MMIO */ 154/* Simple MMIO */
150#define ioread8(a) __raw_readb(a) 155#define ioread8(a) __raw_readb(a)
151#define ioread16(a) __raw_readw(a) 156#define ioread16(a) __raw_readw(a)
@@ -166,6 +171,15 @@ __BUILD_MEMORY_STRING(q, u64)
166#define iowrite8_rep(a, s, c) __raw_writesb((a), (s), (c)) 171#define iowrite8_rep(a, s, c) __raw_writesb((a), (s), (c))
167#define iowrite16_rep(a, s, c) __raw_writesw((a), (s), (c)) 172#define iowrite16_rep(a, s, c) __raw_writesw((a), (s), (c))
168#define iowrite32_rep(a, s, c) __raw_writesl((a), (s), (c)) 173#define iowrite32_rep(a, s, c) __raw_writesl((a), (s), (c))
174#endif
175
176#define mmio_insb(p,d,c) __raw_readsb(p,d,c)
177#define mmio_insw(p,d,c) __raw_readsw(p,d,c)
178#define mmio_insl(p,d,c) __raw_readsl(p,d,c)
179
180#define mmio_outsb(p,s,c) __raw_writesb(p,s,c)
181#define mmio_outsw(p,s,c) __raw_writesw(p,s,c)
182#define mmio_outsl(p,s,c) __raw_writesl(p,s,c)
169 183
170/* synco on SH-4A, otherwise a nop */ 184/* synco on SH-4A, otherwise a nop */
171#define mmiowb() wmb() 185#define mmiowb() wmb()
diff --git a/arch/sh/include/asm/kdebug.h b/arch/sh/include/asm/kdebug.h
index 0b9f896f203c..985219f9759e 100644
--- a/arch/sh/include/asm/kdebug.h
+++ b/arch/sh/include/asm/kdebug.h
@@ -4,6 +4,7 @@
4/* Grossly misnamed. */ 4/* Grossly misnamed. */
5enum die_val { 5enum die_val {
6 DIE_TRAP, 6 DIE_TRAP,
7 DIE_NMI,
7 DIE_OOPS, 8 DIE_OOPS,
8}; 9};
9 10
diff --git a/arch/sh/include/asm/kgdb.h b/arch/sh/include/asm/kgdb.h
index 72704ed725e5..4235e228d921 100644
--- a/arch/sh/include/asm/kgdb.h
+++ b/arch/sh/include/asm/kgdb.h
@@ -30,9 +30,6 @@ static inline void arch_kgdb_breakpoint(void)
30 __asm__ __volatile__ ("trapa #0x3c\n"); 30 __asm__ __volatile__ ("trapa #0x3c\n");
31} 31}
32 32
33/* State info */
34extern char in_nmi; /* Debounce flag to prevent NMI reentry*/
35
36#define BUFMAX 2048 33#define BUFMAX 2048
37 34
38#define CACHE_FLUSH_IS_SAFE 1 35#define CACHE_FLUSH_IS_SAFE 1
diff --git a/arch/sh/include/asm/lmb.h b/arch/sh/include/asm/lmb.h
new file mode 100644
index 000000000000..9b437f657ffa
--- /dev/null
+++ b/arch/sh/include/asm/lmb.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_SH_LMB_H
2#define __ASM_SH_LMB_H
3
4#define LMB_REAL_LIMIT 0
5
6#endif /* __ASM_SH_LMB_H */
diff --git a/arch/sh/include/asm/mmu_context.h b/arch/sh/include/asm/mmu_context.h
index 67d8946db193..41080b173a7a 100644
--- a/arch/sh/include/asm/mmu_context.h
+++ b/arch/sh/include/asm/mmu_context.h
@@ -69,7 +69,7 @@ static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu)
69 * We exhaust ASID of this version. 69 * We exhaust ASID of this version.
70 * Flush all TLB and start new cycle. 70 * Flush all TLB and start new cycle.
71 */ 71 */
72 flush_tlb_all(); 72 local_flush_tlb_all();
73 73
74#ifdef CONFIG_SUPERH64 74#ifdef CONFIG_SUPERH64
75 /* 75 /*
diff --git a/arch/sh/include/asm/page.h b/arch/sh/include/asm/page.h
index 49592c780a6e..81bffc0d6860 100644
--- a/arch/sh/include/asm/page.h
+++ b/arch/sh/include/asm/page.h
@@ -50,26 +50,24 @@ extern unsigned long shm_align_mask;
50extern unsigned long max_low_pfn, min_low_pfn; 50extern unsigned long max_low_pfn, min_low_pfn;
51extern unsigned long memory_start, memory_end; 51extern unsigned long memory_start, memory_end;
52 52
53extern void clear_page(void *to); 53static inline unsigned long
54pages_do_alias(unsigned long addr1, unsigned long addr2)
55{
56 return (addr1 ^ addr2) & shm_align_mask;
57}
58
59
60#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
54extern void copy_page(void *to, void *from); 61extern void copy_page(void *to, void *from);
55 62
56#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \
57 (defined(CONFIG_CPU_SH5) || defined(CONFIG_CPU_SH4) || \
58 defined(CONFIG_SH7705_CACHE_32KB))
59struct page; 63struct page;
60struct vm_area_struct; 64struct vm_area_struct;
61extern void clear_user_page(void *to, unsigned long address, struct page *page); 65
62extern void copy_user_page(void *to, void *from, unsigned long address,
63 struct page *page);
64#if defined(CONFIG_CPU_SH4)
65extern void copy_user_highpage(struct page *to, struct page *from, 66extern void copy_user_highpage(struct page *to, struct page *from,
66 unsigned long vaddr, struct vm_area_struct *vma); 67 unsigned long vaddr, struct vm_area_struct *vma);
67#define __HAVE_ARCH_COPY_USER_HIGHPAGE 68#define __HAVE_ARCH_COPY_USER_HIGHPAGE
68#endif 69extern void clear_user_highpage(struct page *page, unsigned long vaddr);
69#else 70#define clear_user_highpage clear_user_highpage
70#define clear_user_page(page, vaddr, pg) clear_page(page)
71#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
72#endif
73 71
74/* 72/*
75 * These are used to make use of C type-checking.. 73 * These are used to make use of C type-checking..
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index 2a011b18090b..4f3efa7d5a64 100644
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -36,6 +36,12 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
36#define NEFF_SIGN (1LL << (NEFF - 1)) 36#define NEFF_SIGN (1LL << (NEFF - 1))
37#define NEFF_MASK (-1LL << NEFF) 37#define NEFF_MASK (-1LL << NEFF)
38 38
39static inline unsigned long long neff_sign_extend(unsigned long val)
40{
41 unsigned long long extended = val;
42 return (extended & NEFF_SIGN) ? (extended | NEFF_MASK) : extended;
43}
44
39#ifdef CONFIG_29BIT 45#ifdef CONFIG_29BIT
40#define NPHYS 29 46#define NPHYS 29
41#else 47#else
@@ -133,27 +139,25 @@ typedef pte_t *pte_addr_t;
133 */ 139 */
134#define pgtable_cache_init() do { } while (0) 140#define pgtable_cache_init() do { } while (0)
135 141
136#if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \
137 defined(CONFIG_SH7705_CACHE_32KB))
138struct mm_struct;
139#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
140pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
141#endif
142
143struct vm_area_struct; 142struct vm_area_struct;
144extern void update_mmu_cache(struct vm_area_struct * vma, 143
145 unsigned long address, pte_t pte); 144extern void __update_cache(struct vm_area_struct *vma,
145 unsigned long address, pte_t pte);
146extern void __update_tlb(struct vm_area_struct *vma,
147 unsigned long address, pte_t pte);
148
149static inline void
150update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
151{
152 __update_cache(vma, address, pte);
153 __update_tlb(vma, address, pte);
154}
155
146extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 156extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
147extern void paging_init(void); 157extern void paging_init(void);
148extern void page_table_range_init(unsigned long start, unsigned long end, 158extern void page_table_range_init(unsigned long start, unsigned long end,
149 pgd_t *pgd); 159 pgd_t *pgd);
150 160
151#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_CPU_SH4) && defined(CONFIG_MMU)
152extern void kmap_coherent_init(void);
153#else
154#define kmap_coherent_init() do { } while (0)
155#endif
156
157/* arch/sh/mm/mmap.c */ 161/* arch/sh/mm/mmap.c */
158#define HAVE_ARCH_UNMAPPED_AREA 162#define HAVE_ARCH_UNMAPPED_AREA
159#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 163#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
diff --git a/arch/sh/include/asm/pgtable_32.h b/arch/sh/include/asm/pgtable_32.h
index 72ea209195bd..c0d359ce337b 100644
--- a/arch/sh/include/asm/pgtable_32.h
+++ b/arch/sh/include/asm/pgtable_32.h
@@ -20,7 +20,7 @@
20 * - Bit 9 is reserved by everyone and used by _PAGE_PROTNONE. 20 * - Bit 9 is reserved by everyone and used by _PAGE_PROTNONE.
21 * 21 *
22 * - Bits 10 and 11 are low bits of the PPN that are reserved on >= 4K pages. 22 * - Bits 10 and 11 are low bits of the PPN that are reserved on >= 4K pages.
23 * Bit 10 is used for _PAGE_ACCESSED, bit 11 remains unused. 23 * Bit 10 is used for _PAGE_ACCESSED, and bit 11 is used for _PAGE_SPECIAL.
24 * 24 *
25 * - On 29 bit platforms, bits 31 to 29 are used for the space attributes 25 * - On 29 bit platforms, bits 31 to 29 are used for the space attributes
26 * and timing control which (together with bit 0) are moved into the 26 * and timing control which (together with bit 0) are moved into the
@@ -52,6 +52,7 @@
52#define _PAGE_PROTNONE 0x200 /* software: if not present */ 52#define _PAGE_PROTNONE 0x200 /* software: if not present */
53#define _PAGE_ACCESSED 0x400 /* software: page referenced */ 53#define _PAGE_ACCESSED 0x400 /* software: page referenced */
54#define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */ 54#define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */
55#define _PAGE_SPECIAL 0x800 /* software: special page */
55 56
56#define _PAGE_SZ_MASK (_PAGE_SZ0 | _PAGE_SZ1) 57#define _PAGE_SZ_MASK (_PAGE_SZ0 | _PAGE_SZ1)
57#define _PAGE_PR_MASK (_PAGE_RW | _PAGE_USER) 58#define _PAGE_PR_MASK (_PAGE_RW | _PAGE_USER)
@@ -86,6 +87,14 @@
86#define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */ 87#define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */
87#define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */ 88#define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */
88 89
90#ifndef CONFIG_X2TLB
91/* copy the ptea attributes */
92static inline unsigned long copy_ptea_attributes(unsigned long x)
93{
94 return ((x >> 28) & 0xe) | (x & 0x1);
95}
96#endif
97
89/* Mask which drops unused bits from the PTEL value */ 98/* Mask which drops unused bits from the PTEL value */
90#if defined(CONFIG_CPU_SH3) 99#if defined(CONFIG_CPU_SH3)
91#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED| \ 100#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED| \
@@ -148,8 +157,12 @@
148# define _PAGE_SZHUGE (_PAGE_FLAGS_HARD) 157# define _PAGE_SZHUGE (_PAGE_FLAGS_HARD)
149#endif 158#endif
150 159
160/*
161 * Mask of bits that are to be preserved accross pgprot changes.
162 */
151#define _PAGE_CHG_MASK \ 163#define _PAGE_CHG_MASK \
152 (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY) 164 (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | \
165 _PAGE_DIRTY | _PAGE_SPECIAL)
153 166
154#ifndef __ASSEMBLY__ 167#ifndef __ASSEMBLY__
155 168
@@ -328,7 +341,7 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
328#define pte_dirty(pte) ((pte).pte_low & _PAGE_DIRTY) 341#define pte_dirty(pte) ((pte).pte_low & _PAGE_DIRTY)
329#define pte_young(pte) ((pte).pte_low & _PAGE_ACCESSED) 342#define pte_young(pte) ((pte).pte_low & _PAGE_ACCESSED)
330#define pte_file(pte) ((pte).pte_low & _PAGE_FILE) 343#define pte_file(pte) ((pte).pte_low & _PAGE_FILE)
331#define pte_special(pte) (0) 344#define pte_special(pte) ((pte).pte_low & _PAGE_SPECIAL)
332 345
333#ifdef CONFIG_X2TLB 346#ifdef CONFIG_X2TLB
334#define pte_write(pte) ((pte).pte_high & _PAGE_EXT_USER_WRITE) 347#define pte_write(pte) ((pte).pte_high & _PAGE_EXT_USER_WRITE)
@@ -358,8 +371,9 @@ PTE_BIT_FUNC(low, mkclean, &= ~_PAGE_DIRTY);
358PTE_BIT_FUNC(low, mkdirty, |= _PAGE_DIRTY); 371PTE_BIT_FUNC(low, mkdirty, |= _PAGE_DIRTY);
359PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED); 372PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED);
360PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED); 373PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
374PTE_BIT_FUNC(low, mkspecial, |= _PAGE_SPECIAL);
361 375
362static inline pte_t pte_mkspecial(pte_t pte) { return pte; } 376#define __HAVE_ARCH_PTE_SPECIAL
363 377
364/* 378/*
365 * Macro and implementation to make a page protection as uncachable. 379 * Macro and implementation to make a page protection as uncachable.
@@ -394,13 +408,19 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
394 408
395/* to find an entry in a page-table-directory. */ 409/* to find an entry in a page-table-directory. */
396#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 410#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
397#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address)) 411#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
412#define __pgd_offset(address) pgd_index(address)
398 413
399/* to find an entry in a kernel page-table-directory */ 414/* to find an entry in a kernel page-table-directory */
400#define pgd_offset_k(address) pgd_offset(&init_mm, address) 415#define pgd_offset_k(address) pgd_offset(&init_mm, address)
401 416
417#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
418#define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
419
402/* Find an entry in the third-level page table.. */ 420/* Find an entry in the third-level page table.. */
403#define pte_index(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 421#define pte_index(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
422#define __pte_offset(address) pte_index(address)
423
404#define pte_offset_kernel(dir, address) \ 424#define pte_offset_kernel(dir, address) \
405 ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address)) 425 ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address))
406#define pte_offset_map(dir, address) pte_offset_kernel(dir, address) 426#define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
diff --git a/arch/sh/include/asm/pgtable_64.h b/arch/sh/include/asm/pgtable_64.h
index c78990cda557..17cdbecc3adc 100644
--- a/arch/sh/include/asm/pgtable_64.h
+++ b/arch/sh/include/asm/pgtable_64.h
@@ -60,6 +60,9 @@ static __inline__ void pmd_set(pmd_t *pmdp,pte_t *ptep)
60/* To find an entry in a kernel PGD. */ 60/* To find an entry in a kernel PGD. */
61#define pgd_offset_k(address) pgd_offset(&init_mm, address) 61#define pgd_offset_k(address) pgd_offset(&init_mm, address)
62 62
63#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
64#define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
65
63/* 66/*
64 * PMD level access routines. Same notes as above. 67 * PMD level access routines. Same notes as above.
65 */ 68 */
@@ -80,6 +83,8 @@ static __inline__ void pmd_set(pmd_t *pmdp,pte_t *ptep)
80#define pte_index(address) \ 83#define pte_index(address) \
81 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 84 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
82 85
86#define __pte_offset(address) pte_index(address)
87
83#define pte_offset_kernel(dir, addr) \ 88#define pte_offset_kernel(dir, addr) \
84 ((pte_t *) ((pmd_val(*(dir))) & PAGE_MASK) + pte_index((addr))) 89 ((pte_t *) ((pmd_val(*(dir))) & PAGE_MASK) + pte_index((addr)))
85 90
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index ff7daaf9a620..017e0c1807b2 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -32,7 +32,7 @@ enum cpu_type {
32 32
33 /* SH-4A types */ 33 /* SH-4A types */
34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, 34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
35 CPU_SH7723, CPU_SH7724, CPU_SHX3, 35 CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3,
36 36
37 /* SH4AL-DSP types */ 37 /* SH4AL-DSP types */
38 CPU_SH7343, CPU_SH7722, CPU_SH7366, 38 CPU_SH7343, CPU_SH7722, CPU_SH7366,
@@ -44,6 +44,17 @@ enum cpu_type {
44 CPU_SH_NONE 44 CPU_SH_NONE
45}; 45};
46 46
47enum cpu_family {
48 CPU_FAMILY_SH2,
49 CPU_FAMILY_SH2A,
50 CPU_FAMILY_SH3,
51 CPU_FAMILY_SH4,
52 CPU_FAMILY_SH4A,
53 CPU_FAMILY_SH4AL_DSP,
54 CPU_FAMILY_SH5,
55 CPU_FAMILY_UNKNOWN,
56};
57
47/* 58/*
48 * TLB information structure 59 * TLB information structure
49 * 60 *
@@ -61,7 +72,7 @@ struct tlb_info {
61}; 72};
62 73
63struct sh_cpuinfo { 74struct sh_cpuinfo {
64 unsigned int type; 75 unsigned int type, family;
65 int cut_major, cut_minor; 76 int cut_major, cut_minor;
66 unsigned long loops_per_jiffy; 77 unsigned long loops_per_jiffy;
67 unsigned long asid_cache; 78 unsigned long asid_cache;
diff --git a/arch/sh/include/asm/romimage-macros.h b/arch/sh/include/asm/romimage-macros.h
new file mode 100644
index 000000000000..ae17a150bb58
--- /dev/null
+++ b/arch/sh/include/asm/romimage-macros.h
@@ -0,0 +1,73 @@
1#ifndef __ROMIMAGE_MACRO_H
2#define __ROMIMAGE_MACRO_H
3
4/* The LIST command is used to include comments in the script */
5.macro LIST comment
6.endm
7
8/* The ED command is used to write a 32-bit word */
9.macro ED, addr, data
10 mov.l 1f, r1
11 mov.l 2f, r0
12 mov.l r0, @r1
13 bra 3f
14 nop
15 .align 2
161 : .long \addr
172 : .long \data
183 :
19.endm
20
21/* The EW command is used to write a 16-bit word */
22.macro EW, addr, data
23 mov.l 1f, r1
24 mov.l 2f, r0
25 mov.w r0, @r1
26 bra 3f
27 nop
28 .align 2
291 : .long \addr
302 : .long \data
313 :
32.endm
33
34/* The EB command is used to write an 8-bit word */
35.macro EB, addr, data
36 mov.l 1f, r1
37 mov.l 2f, r0
38 mov.b r0, @r1
39 bra 3f
40 nop
41 .align 2
421 : .long \addr
432 : .long \data
443 :
45.endm
46
47/* The WAIT command is used to delay the execution */
48.macro WAIT, time
49 mov.l 2f, r3
501 :
51 nop
52 tst r3, r3
53 bf/s 1b
54 dt r3
55 bra 3f
56 nop
57 .align 2
582 : .long \time * 100
593 :
60.endm
61
62/* The DD command is used to read a 32-bit word */
63.macro DD, addr, addr2, nr
64 mov.l 1f, r1
65 mov.l @r1, r0
66 bra 2f
67 nop
68 .align 2
691 : .long \addr
702 :
71.endm
72
73#endif /* __ROMIMAGE_MACRO_H */
diff --git a/arch/sh/include/asm/sections.h b/arch/sh/include/asm/sections.h
index 01a4076a3719..a78701da775b 100644
--- a/arch/sh/include/asm/sections.h
+++ b/arch/sh/include/asm/sections.h
@@ -7,6 +7,7 @@ extern void __nosave_begin, __nosave_end;
7extern long __machvec_start, __machvec_end; 7extern long __machvec_start, __machvec_end;
8extern char __uncached_start, __uncached_end; 8extern char __uncached_start, __uncached_end;
9extern char _ebss[]; 9extern char _ebss[];
10extern char __start_eh_frame[], __stop_eh_frame[];
10 11
11#endif /* __ASM_SH_SECTIONS_H */ 12#endif /* __ASM_SH_SECTIONS_H */
12 13
diff --git a/arch/sh/include/asm/sh_keysc.h b/arch/sh/include/asm/sh_keysc.h
index b5a4dd5a9729..4a65b1e40eab 100644
--- a/arch/sh/include/asm/sh_keysc.h
+++ b/arch/sh/include/asm/sh_keysc.h
@@ -7,6 +7,7 @@ struct sh_keysc_info {
7 enum { SH_KEYSC_MODE_1, SH_KEYSC_MODE_2, SH_KEYSC_MODE_3 } mode; 7 enum { SH_KEYSC_MODE_1, SH_KEYSC_MODE_2, SH_KEYSC_MODE_3 } mode;
8 int scan_timing; /* 0 -> 7, see KYCR1, SCN[2:0] */ 8 int scan_timing; /* 0 -> 7, see KYCR1, SCN[2:0] */
9 int delay; 9 int delay;
10 int kycr2_delay;
10 int keycodes[SH_KEYSC_MAXKEYS]; 11 int keycodes[SH_KEYSC_MAXKEYS];
11}; 12};
12 13
diff --git a/arch/sh/include/asm/stacktrace.h b/arch/sh/include/asm/stacktrace.h
new file mode 100644
index 000000000000..797018213718
--- /dev/null
+++ b/arch/sh/include/asm/stacktrace.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 2009 Matt Fleming
3 *
4 * Based on:
5 * The x86 implementation - arch/x86/include/asm/stacktrace.h
6 */
7#ifndef _ASM_SH_STACKTRACE_H
8#define _ASM_SH_STACKTRACE_H
9
10/* Generic stack tracer with callbacks */
11
12struct stacktrace_ops {
13 void (*warning)(void *data, char *msg);
14 /* msg must contain %s for the symbol */
15 void (*warning_symbol)(void *data, char *msg, unsigned long symbol);
16 void (*address)(void *data, unsigned long address, int reliable);
17 /* On negative return stop dumping */
18 int (*stack)(void *data, char *name);
19};
20
21void dump_trace(struct task_struct *tsk, struct pt_regs *regs,
22 unsigned long *stack,
23 const struct stacktrace_ops *ops, void *data);
24
25#endif /* _ASM_SH_STACKTRACE_H */
diff --git a/arch/sh/include/asm/suspend.h b/arch/sh/include/asm/suspend.h
index b1b995370e79..5c8ea28ff7a4 100644
--- a/arch/sh/include/asm/suspend.h
+++ b/arch/sh/include/asm/suspend.h
@@ -10,6 +10,15 @@ struct swsusp_arch_regs {
10 struct pt_regs user_regs; 10 struct pt_regs user_regs;
11 unsigned long bank1_regs[8]; 11 unsigned long bank1_regs[8];
12}; 12};
13
14void sh_mobile_call_standby(unsigned long mode);
15
16#ifdef CONFIG_CPU_IDLE
17void sh_mobile_setup_cpuidle(void);
18#else
19static inline void sh_mobile_setup_cpuidle(void) {}
20#endif
21
13#endif 22#endif
14 23
15/* flags passed to assembly suspend code */ 24/* flags passed to assembly suspend code */
diff --git a/arch/sh/include/asm/syscall_32.h b/arch/sh/include/asm/syscall_32.h
index 6f83f2cc45c1..7d80df4f09cb 100644
--- a/arch/sh/include/asm/syscall_32.h
+++ b/arch/sh/include/asm/syscall_32.h
@@ -65,6 +65,7 @@ static inline void syscall_get_arguments(struct task_struct *task,
65 case 3: args[2] = regs->regs[6]; 65 case 3: args[2] = regs->regs[6];
66 case 2: args[1] = regs->regs[5]; 66 case 2: args[1] = regs->regs[5];
67 case 1: args[0] = regs->regs[4]; 67 case 1: args[0] = regs->regs[4];
68 case 0:
68 break; 69 break;
69 default: 70 default:
70 BUG(); 71 BUG();
diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h
index ab79e1f4fbe0..b5c5acdc8c0e 100644
--- a/arch/sh/include/asm/system.h
+++ b/arch/sh/include/asm/system.h
@@ -14,18 +14,6 @@
14 14
15#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */ 15#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
16 16
17#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
18#define __icbi() \
19{ \
20 unsigned long __addr; \
21 __addr = 0xa8000000; \
22 __asm__ __volatile__( \
23 "icbi %0\n\t" \
24 : /* no output */ \
25 : "m" (__m(__addr))); \
26}
27#endif
28
29/* 17/*
30 * A brief note on ctrl_barrier(), the control register write barrier. 18 * A brief note on ctrl_barrier(), the control register write barrier.
31 * 19 *
@@ -44,7 +32,7 @@
44#define mb() __asm__ __volatile__ ("synco": : :"memory") 32#define mb() __asm__ __volatile__ ("synco": : :"memory")
45#define rmb() mb() 33#define rmb() mb()
46#define wmb() __asm__ __volatile__ ("synco": : :"memory") 34#define wmb() __asm__ __volatile__ ("synco": : :"memory")
47#define ctrl_barrier() __icbi() 35#define ctrl_barrier() __icbi(0xa8000000)
48#define read_barrier_depends() do { } while(0) 36#define read_barrier_depends() do { } while(0)
49#else 37#else
50#define mb() __asm__ __volatile__ ("": : :"memory") 38#define mb() __asm__ __volatile__ ("": : :"memory")
@@ -181,6 +169,11 @@ BUILD_TRAP_HANDLER(breakpoint);
181BUILD_TRAP_HANDLER(singlestep); 169BUILD_TRAP_HANDLER(singlestep);
182BUILD_TRAP_HANDLER(fpu_error); 170BUILD_TRAP_HANDLER(fpu_error);
183BUILD_TRAP_HANDLER(fpu_state_restore); 171BUILD_TRAP_HANDLER(fpu_state_restore);
172BUILD_TRAP_HANDLER(nmi);
173
174#ifdef CONFIG_BUG
175extern void handle_BUG(struct pt_regs *);
176#endif
184 177
185#define arch_align_stack(x) (x) 178#define arch_align_stack(x) (x)
186 179
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h
index 6c68a51f1cc5..607d413f6168 100644
--- a/arch/sh/include/asm/system_32.h
+++ b/arch/sh/include/asm/system_32.h
@@ -14,12 +14,12 @@ do { \
14 (u32 *)&tsk->thread.dsp_status; \ 14 (u32 *)&tsk->thread.dsp_status; \
15 __asm__ __volatile__ ( \ 15 __asm__ __volatile__ ( \
16 ".balign 4\n\t" \ 16 ".balign 4\n\t" \
17 "movs.l @r2+, a0\n\t" \
17 "movs.l @r2+, a1\n\t" \ 18 "movs.l @r2+, a1\n\t" \
18 "movs.l @r2+, a0g\n\t" \ 19 "movs.l @r2+, a0g\n\t" \
19 "movs.l @r2+, a1g\n\t" \ 20 "movs.l @r2+, a1g\n\t" \
20 "movs.l @r2+, m0\n\t" \ 21 "movs.l @r2+, m0\n\t" \
21 "movs.l @r2+, m1\n\t" \ 22 "movs.l @r2+, m1\n\t" \
22 "movs.l @r2+, a0\n\t" \
23 "movs.l @r2+, x0\n\t" \ 23 "movs.l @r2+, x0\n\t" \
24 "movs.l @r2+, x1\n\t" \ 24 "movs.l @r2+, x1\n\t" \
25 "movs.l @r2+, y0\n\t" \ 25 "movs.l @r2+, y0\n\t" \
@@ -39,20 +39,20 @@ do { \
39 \ 39 \
40 __asm__ __volatile__ ( \ 40 __asm__ __volatile__ ( \
41 ".balign 4\n\t" \ 41 ".balign 4\n\t" \
42 "stc.l mod, @-r2\n\t" \ 42 "stc.l mod, @-r2\n\t" \
43 "stc.l re, @-r2\n\t" \ 43 "stc.l re, @-r2\n\t" \
44 "stc.l rs, @-r2\n\t" \ 44 "stc.l rs, @-r2\n\t" \
45 "sts.l dsr, @-r2\n\t" \ 45 "sts.l dsr, @-r2\n\t" \
46 "sts.l y1, @-r2\n\t" \ 46 "movs.l y1, @-r2\n\t" \
47 "sts.l y0, @-r2\n\t" \ 47 "movs.l y0, @-r2\n\t" \
48 "sts.l x1, @-r2\n\t" \ 48 "movs.l x1, @-r2\n\t" \
49 "sts.l x0, @-r2\n\t" \ 49 "movs.l x0, @-r2\n\t" \
50 "sts.l a0, @-r2\n\t" \ 50 "movs.l m1, @-r2\n\t" \
51 ".word 0xf653 ! movs.l a1, @-r2\n\t" \ 51 "movs.l m0, @-r2\n\t" \
52 ".word 0xf6f3 ! movs.l a0g, @-r2\n\t" \ 52 "movs.l a1g, @-r2\n\t" \
53 ".word 0xf6d3 ! movs.l a1g, @-r2\n\t" \ 53 "movs.l a0g, @-r2\n\t" \
54 ".word 0xf6c3 ! movs.l m0, @-r2\n\t" \ 54 "movs.l a1, @-r2\n\t" \
55 ".word 0xf6e3 ! movs.l m1, @-r2\n\t" \ 55 "movs.l a0, @-r2\n\t" \
56 : : "r" (__ts2)); \ 56 : : "r" (__ts2)); \
57} while (0) 57} while (0)
58 58
@@ -63,6 +63,16 @@ do { \
63#define __restore_dsp(tsk) do { } while (0) 63#define __restore_dsp(tsk) do { } while (0)
64#endif 64#endif
65 65
66#if defined(CONFIG_CPU_SH4A)
67#define __icbi(addr) __asm__ __volatile__ ( "icbi @%0\n\t" : : "r" (addr))
68#else
69#define __icbi(addr) mb()
70#endif
71
72#define __ocbp(addr) __asm__ __volatile__ ( "ocbp @%0\n\t" : : "r" (addr))
73#define __ocbi(addr) __asm__ __volatile__ ( "ocbi @%0\n\t" : : "r" (addr))
74#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb @%0\n\t" : : "r" (addr))
75
66struct task_struct *__switch_to(struct task_struct *prev, 76struct task_struct *__switch_to(struct task_struct *prev,
67 struct task_struct *next); 77 struct task_struct *next);
68 78
@@ -198,8 +208,13 @@ do { \
198}) 208})
199#endif 209#endif
200 210
211static inline reg_size_t register_align(void *val)
212{
213 return (unsigned long)(signed long)val;
214}
215
201int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, 216int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
202 struct mem_access *ma); 217 struct mem_access *ma, int);
203 218
204asmlinkage void do_address_error(struct pt_regs *regs, 219asmlinkage void do_address_error(struct pt_regs *regs,
205 unsigned long writeaccess, 220 unsigned long writeaccess,
diff --git a/arch/sh/include/asm/system_64.h b/arch/sh/include/asm/system_64.h
index 943acf5ea07c..8e4a03e7966c 100644
--- a/arch/sh/include/asm/system_64.h
+++ b/arch/sh/include/asm/system_64.h
@@ -37,4 +37,14 @@ do { \
37#define jump_to_uncached() do { } while (0) 37#define jump_to_uncached() do { } while (0)
38#define back_to_cached() do { } while (0) 38#define back_to_cached() do { } while (0)
39 39
40#define __icbi(addr) __asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr))
41#define __ocbp(addr) __asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr))
42#define __ocbi(addr) __asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr))
43#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb %0, 0\n\t" : : "r" (addr))
44
45static inline reg_size_t register_align(void *val)
46{
47 return (unsigned long long)(signed long long)(signed long)val;
48}
49
40#endif /* __ASM_SH_SYSTEM_64_H */ 50#endif /* __ASM_SH_SYSTEM_64_H */
diff --git a/arch/sh/include/asm/thread_info.h b/arch/sh/include/asm/thread_info.h
index d570ac2e5cb9..bdeb9d46d17d 100644
--- a/arch/sh/include/asm/thread_info.h
+++ b/arch/sh/include/asm/thread_info.h
@@ -97,7 +97,7 @@ static inline struct thread_info *current_thread_info(void)
97 97
98extern struct thread_info *alloc_thread_info(struct task_struct *tsk); 98extern struct thread_info *alloc_thread_info(struct task_struct *tsk);
99extern void free_thread_info(struct thread_info *ti); 99extern void free_thread_info(struct thread_info *ti);
100 100
101#endif /* THREAD_SHIFT < PAGE_SHIFT */ 101#endif /* THREAD_SHIFT < PAGE_SHIFT */
102 102
103#endif /* __ASSEMBLY__ */ 103#endif /* __ASSEMBLY__ */
@@ -116,6 +116,7 @@ extern void free_thread_info(struct thread_info *ti);
116#define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */ 116#define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */
117#define TIF_SECCOMP 6 /* secure computing */ 117#define TIF_SECCOMP 6 /* secure computing */
118#define TIF_NOTIFY_RESUME 7 /* callback before returning to user */ 118#define TIF_NOTIFY_RESUME 7 /* callback before returning to user */
119#define TIF_SYSCALL_TRACEPOINT 8 /* for ftrace syscall instrumentation */
119#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ 120#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
120#define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ 121#define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */
121#define TIF_MEMDIE 18 122#define TIF_MEMDIE 18
@@ -129,25 +130,27 @@ extern void free_thread_info(struct thread_info *ti);
129#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) 130#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
130#define _TIF_SECCOMP (1 << TIF_SECCOMP) 131#define _TIF_SECCOMP (1 << TIF_SECCOMP)
131#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) 132#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
133#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT)
132#define _TIF_USEDFPU (1 << TIF_USEDFPU) 134#define _TIF_USEDFPU (1 << TIF_USEDFPU)
133#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) 135#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG)
134#define _TIF_FREEZE (1 << TIF_FREEZE) 136#define _TIF_FREEZE (1 << TIF_FREEZE)
135 137
136/* 138/*
137 * _TIF_ALLWORK_MASK and _TIF_WORK_MASK need to fit within a byte, or we 139 * _TIF_ALLWORK_MASK and _TIF_WORK_MASK need to fit within 2 bytes, or we
138 * blow the tst immediate size constraints and need to fix up 140 * blow the tst immediate size constraints and need to fix up
139 * arch/sh/kernel/entry-common.S. 141 * arch/sh/kernel/entry-common.S.
140 */ 142 */
141 143
142/* work to do in syscall trace */ 144/* work to do in syscall trace */
143#define _TIF_WORK_SYSCALL_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \ 145#define _TIF_WORK_SYSCALL_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \
144 _TIF_SYSCALL_AUDIT | _TIF_SECCOMP) 146 _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
147 _TIF_SYSCALL_TRACEPOINT)
145 148
146/* work to do on any return to u-space */ 149/* work to do on any return to u-space */
147#define _TIF_ALLWORK_MASK (_TIF_SYSCALL_TRACE | _TIF_SIGPENDING | \ 150#define _TIF_ALLWORK_MASK (_TIF_SYSCALL_TRACE | _TIF_SIGPENDING | \
148 _TIF_NEED_RESCHED | _TIF_SYSCALL_AUDIT | \ 151 _TIF_NEED_RESCHED | _TIF_SYSCALL_AUDIT | \
149 _TIF_SINGLESTEP | _TIF_RESTORE_SIGMASK | \ 152 _TIF_SINGLESTEP | _TIF_RESTORE_SIGMASK | \
150 _TIF_NOTIFY_RESUME) 153 _TIF_NOTIFY_RESUME | _TIF_SYSCALL_TRACEPOINT)
151 154
152/* work to do on interrupt/exception return */ 155/* work to do on interrupt/exception return */
153#define _TIF_WORK_MASK (_TIF_ALLWORK_MASK & ~(_TIF_SYSCALL_TRACE | \ 156#define _TIF_WORK_MASK (_TIF_ALLWORK_MASK & ~(_TIF_SYSCALL_TRACE | \
diff --git a/arch/sh/include/asm/types.h b/arch/sh/include/asm/types.h
index c7f3c94837dd..f8421f7ad63a 100644
--- a/arch/sh/include/asm/types.h
+++ b/arch/sh/include/asm/types.h
@@ -11,8 +11,10 @@
11 11
12#ifdef CONFIG_SUPERH32 12#ifdef CONFIG_SUPERH32
13typedef u16 insn_size_t; 13typedef u16 insn_size_t;
14typedef u32 reg_size_t;
14#else 15#else
15typedef u32 insn_size_t; 16typedef u32 insn_size_t;
17typedef u64 reg_size_t;
16#endif 18#endif
17 19
18#endif /* __ASSEMBLY__ */ 20#endif /* __ASSEMBLY__ */
diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h
index 61d6ad93d786..925dd40d9d55 100644
--- a/arch/sh/include/asm/unistd_32.h
+++ b/arch/sh/include/asm/unistd_32.h
@@ -132,7 +132,7 @@
132#define __NR_clone 120 132#define __NR_clone 120
133#define __NR_setdomainname 121 133#define __NR_setdomainname 121
134#define __NR_uname 122 134#define __NR_uname 122
135#define __NR_modify_ldt 123 135#define __NR_cacheflush 123
136#define __NR_adjtimex 124 136#define __NR_adjtimex 124
137#define __NR_mprotect 125 137#define __NR_mprotect 125
138#define __NR_sigprocmask 126 138#define __NR_sigprocmask 126
diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h
index a751699afda3..2b84bc916bc5 100644
--- a/arch/sh/include/asm/unistd_64.h
+++ b/arch/sh/include/asm/unistd_64.h
@@ -137,7 +137,7 @@
137#define __NR_clone 120 137#define __NR_clone 120
138#define __NR_setdomainname 121 138#define __NR_setdomainname 121
139#define __NR_uname 122 139#define __NR_uname 122
140#define __NR_modify_ldt 123 140#define __NR_cacheflush 123
141#define __NR_adjtimex 124 141#define __NR_adjtimex 124
142#define __NR_mprotect 125 142#define __NR_mprotect 125
143#define __NR_sigprocmask 126 143#define __NR_sigprocmask 126
diff --git a/arch/sh/include/asm/unwinder.h b/arch/sh/include/asm/unwinder.h
new file mode 100644
index 000000000000..1e65c07b3e18
--- /dev/null
+++ b/arch/sh/include/asm/unwinder.h
@@ -0,0 +1,31 @@
1#ifndef _LINUX_UNWINDER_H
2#define _LINUX_UNWINDER_H
3
4#include <asm/stacktrace.h>
5
6struct unwinder {
7 const char *name;
8 struct list_head list;
9 int rating;
10 void (*dump)(struct task_struct *, struct pt_regs *,
11 unsigned long *, const struct stacktrace_ops *, void *);
12};
13
14extern int unwinder_init(void);
15extern int unwinder_register(struct unwinder *);
16
17extern void unwind_stack(struct task_struct *, struct pt_regs *,
18 unsigned long *, const struct stacktrace_ops *,
19 void *);
20
21extern void stack_reader_dump(struct task_struct *, struct pt_regs *,
22 unsigned long *, const struct stacktrace_ops *,
23 void *);
24
25/*
26 * Used by fault handling code to signal to the unwinder code that it
27 * should switch to a different unwinder.
28 */
29extern int unwinder_faulted;
30
31#endif /* _LINUX_UNWINDER_H */
diff --git a/arch/sh/include/asm/vmlinux.lds.h b/arch/sh/include/asm/vmlinux.lds.h
new file mode 100644
index 000000000000..244ec4ad9a79
--- /dev/null
+++ b/arch/sh/include/asm/vmlinux.lds.h
@@ -0,0 +1,17 @@
1#ifndef __ASM_SH_VMLINUX_LDS_H
2#define __ASM_SH_VMLINUX_LDS_H
3
4#include <asm-generic/vmlinux.lds.h>
5
6#ifdef CONFIG_DWARF_UNWINDER
7#define DWARF_EH_FRAME \
8 .eh_frame : AT(ADDR(.eh_frame) - LOAD_OFFSET) { \
9 VMLINUX_SYMBOL(__start_eh_frame) = .; \
10 *(.eh_frame) \
11 VMLINUX_SYMBOL(__stop_eh_frame) = .; \
12 }
13#else
14#define DWARF_EH_FRAME
15#endif
16
17#endif /* __ASM_SH_VMLINUX_LDS_H */
diff --git a/arch/sh/include/asm/watchdog.h b/arch/sh/include/asm/watchdog.h
index f024fed00a72..2fe7cee9e43a 100644
--- a/arch/sh/include/asm/watchdog.h
+++ b/arch/sh/include/asm/watchdog.h
@@ -13,10 +13,18 @@
13#ifdef __KERNEL__ 13#ifdef __KERNEL__
14 14
15#include <linux/types.h> 15#include <linux/types.h>
16#include <linux/io.h>
17
18#define WTCNT_HIGH 0x5a
19#define WTCSR_HIGH 0xa5
20
21#define WTCSR_CKS2 0x04
22#define WTCSR_CKS1 0x02
23#define WTCSR_CKS0 0x01
24
16#include <cpu/watchdog.h> 25#include <cpu/watchdog.h>
17#include <asm/io.h>
18 26
19/* 27/*
20 * See cpu-sh2/watchdog.h for explanation of this stupidity.. 28 * See cpu-sh2/watchdog.h for explanation of this stupidity..
21 */ 29 */
22#ifndef WTCNT_R 30#ifndef WTCNT_R
@@ -27,13 +35,6 @@
27# define WTCSR_R WTCSR 35# define WTCSR_R WTCSR
28#endif 36#endif
29 37
30#define WTCNT_HIGH 0x5a
31#define WTCSR_HIGH 0xa5
32
33#define WTCSR_CKS2 0x04
34#define WTCSR_CKS1 0x02
35#define WTCSR_CKS0 0x01
36
37/* 38/*
38 * CKS0-2 supports a number of clock division ratios. At the time the watchdog 39 * CKS0-2 supports a number of clock division ratios. At the time the watchdog
39 * is enabled, it defaults to a 41 usec overflow period .. we overload this to 40 * is enabled, it defaults to a 41 usec overflow period .. we overload this to
diff --git a/arch/sh/include/cpu-common/cpu/cacheflush.h b/arch/sh/include/cpu-common/cpu/cacheflush.h
deleted file mode 100644
index c3db00b73605..000000000000
--- a/arch/sh/include/cpu-common/cpu/cacheflush.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh2/cacheflush.h
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_CACHEFLUSH_H
11#define __ASM_CPU_SH2_CACHEFLUSH_H
12
13/*
14 * Cache flushing:
15 *
16 * - flush_cache_all() flushes entire cache
17 * - flush_cache_mm(mm) flushes the specified mm context's cache lines
18 * - flush_cache_dup mm(mm) handles cache flushing when forking
19 * - flush_cache_page(mm, vmaddr, pfn) flushes a single page
20 * - flush_cache_range(vma, start, end) flushes a range of pages
21 *
22 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
23 * - flush_icache_range(start, end) flushes(invalidates) a range for icache
24 * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
25 *
26 * Caches are indexed (effectively) by physical address on SH-2, so
27 * we don't need them.
28 */
29#define flush_cache_all() do { } while (0)
30#define flush_cache_mm(mm) do { } while (0)
31#define flush_cache_dup_mm(mm) do { } while (0)
32#define flush_cache_range(vma, start, end) do { } while (0)
33#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
34#define flush_dcache_page(page) do { } while (0)
35#define flush_dcache_mmap_lock(mapping) do { } while (0)
36#define flush_dcache_mmap_unlock(mapping) do { } while (0)
37#define flush_icache_range(start, end) do { } while (0)
38#define flush_icache_page(vma,pg) do { } while (0)
39#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
40#define flush_cache_sigtramp(vaddr) do { } while (0)
41
42#define p3_cache_init() do { } while (0)
43
44#endif /* __ASM_CPU_SH2_CACHEFLUSH_H */
diff --git a/arch/sh/include/cpu-sh2a/cpu/cacheflush.h b/arch/sh/include/cpu-sh2a/cpu/cacheflush.h
deleted file mode 100644
index 3d3b9205d2ac..000000000000
--- a/arch/sh/include/cpu-sh2a/cpu/cacheflush.h
+++ /dev/null
@@ -1,34 +0,0 @@
1#ifndef __ASM_CPU_SH2A_CACHEFLUSH_H
2#define __ASM_CPU_SH2A_CACHEFLUSH_H
3
4/*
5 * Cache flushing:
6 *
7 * - flush_cache_all() flushes entire cache
8 * - flush_cache_mm(mm) flushes the specified mm context's cache lines
9 * - flush_cache_dup mm(mm) handles cache flushing when forking
10 * - flush_cache_page(mm, vmaddr, pfn) flushes a single page
11 * - flush_cache_range(vma, start, end) flushes a range of pages
12 *
13 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
14 * - flush_icache_range(start, end) flushes(invalidates) a range for icache
15 * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
16 *
17 * Caches are indexed (effectively) by physical address on SH-2, so
18 * we don't need them.
19 */
20#define flush_cache_all() do { } while (0)
21#define flush_cache_mm(mm) do { } while (0)
22#define flush_cache_dup_mm(mm) do { } while (0)
23#define flush_cache_range(vma, start, end) do { } while (0)
24#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
25#define flush_dcache_page(page) do { } while (0)
26#define flush_dcache_mmap_lock(mapping) do { } while (0)
27#define flush_dcache_mmap_unlock(mapping) do { } while (0)
28void flush_icache_range(unsigned long start, unsigned long end);
29#define flush_icache_page(vma,pg) do { } while (0)
30#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
31#define flush_cache_sigtramp(vaddr) do { } while (0)
32
33#define p3_cache_init() do { } while (0)
34#endif /* __ASM_CPU_SH2A_CACHEFLUSH_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/cacheflush.h b/arch/sh/include/cpu-sh3/cpu/cacheflush.h
deleted file mode 100644
index 1ac27aae6700..000000000000
--- a/arch/sh/include/cpu-sh3/cpu/cacheflush.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/cacheflush.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_CACHEFLUSH_H
11#define __ASM_CPU_SH3_CACHEFLUSH_H
12
13#if defined(CONFIG_SH7705_CACHE_32KB)
14/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the
15 * SH4. Unlike the SH4 this is a unified cache so we need to do some work
16 * in mmap when 'exec'ing a new binary
17 */
18 /* 32KB cache, 4kb PAGE sizes need to check bit 12 */
19#define CACHE_ALIAS 0x00001000
20
21#define PG_mapped PG_arch_1
22
23void flush_cache_all(void);
24void flush_cache_mm(struct mm_struct *mm);
25#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
26void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
27 unsigned long end);
28void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
29void flush_dcache_page(struct page *pg);
30void flush_icache_range(unsigned long start, unsigned long end);
31void flush_icache_page(struct vm_area_struct *vma, struct page *page);
32
33#define flush_dcache_mmap_lock(mapping) do { } while (0)
34#define flush_dcache_mmap_unlock(mapping) do { } while (0)
35
36/* SH3 has unified cache so no special action needed here */
37#define flush_cache_sigtramp(vaddr) do { } while (0)
38#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
39
40#define p3_cache_init() do { } while (0)
41
42#else
43#include <cpu-common/cpu/cacheflush.h>
44#endif
45
46#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/cacheflush.h b/arch/sh/include/cpu-sh4/cpu/cacheflush.h
deleted file mode 100644
index 065306d376eb..000000000000
--- a/arch/sh/include/cpu-sh4/cpu/cacheflush.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/cacheflush.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_CPU_SH4_CACHEFLUSH_H
12#define __ASM_CPU_SH4_CACHEFLUSH_H
13
14/*
15 * Caches are broken on SH-4 (unless we use write-through
16 * caching; in which case they're only semi-broken),
17 * so we need them.
18 */
19void flush_cache_all(void);
20void flush_dcache_all(void);
21void flush_cache_mm(struct mm_struct *mm);
22#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
23void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
24 unsigned long end);
25void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
26 unsigned long pfn);
27void flush_dcache_page(struct page *pg);
28
29#define flush_dcache_mmap_lock(mapping) do { } while (0)
30#define flush_dcache_mmap_unlock(mapping) do { } while (0)
31
32void flush_icache_range(unsigned long start, unsigned long end);
33void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
34 unsigned long addr, int len);
35
36#define flush_icache_page(vma,pg) do { } while (0)
37
38/* Initialization of P3 area for copy_user_page */
39void p3_cache_init(void);
40
41#define PG_mapped PG_arch_1
42
43#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
index 0ed5178fed69..f0886bc880e0 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
@@ -16,7 +16,8 @@
16#define DMAE0_IRQ 38 16#define DMAE0_IRQ 38
17#define SH_DMAC_BASE0 0xFF608020 17#define SH_DMAC_BASE0 0xFF608020
18#define SH_DMARS_BASE 0xFF609000 18#define SH_DMARS_BASE 0xFF609000
19#elif defined(CONFIG_CPU_SUBTYPE_SH7723) 19#elif defined(CONFIG_CPU_SUBTYPE_SH7723) || \
20 defined(CONFIG_CPU_SUBTYPE_SH7724)
20#define DMTE0_IRQ 48 /* DMAC0A*/ 21#define DMTE0_IRQ 48 /* DMAC0A*/
21#define DMTE4_IRQ 40 /* DMAC0B */ 22#define DMTE4_IRQ 40 /* DMAC0B */
22#define DMTE6_IRQ 42 23#define DMTE6_IRQ 42
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index ccf1d999db6d..e1e90960ee9a 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -22,6 +22,10 @@
22#define MSTPCR0 0xa4150030 22#define MSTPCR0 0xa4150030
23#define MSTPCR1 0xa4150034 23#define MSTPCR1 0xa4150034
24#define MSTPCR2 0xa4150038 24#define MSTPCR2 0xa4150038
25#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
26#define FRQCR 0xffc80000
27#define OSCCR 0xffc80018
28#define PLLCR 0xffc80024
25#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 29#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
26 defined(CONFIG_CPU_SUBTYPE_SH7780) 30 defined(CONFIG_CPU_SUBTYPE_SH7780)
27#define FRQCR 0xffc80000 31#define FRQCR 0xffc80000
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7722.h b/arch/sh/include/cpu-sh4/cpu/sh7722.h
index 738ea43c5038..48560407cbe1 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7722.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7722.h
@@ -221,4 +221,18 @@ enum {
221 GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4_IN6, GPIO_FN_KEYOUT5_IN5, 221 GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4_IN6, GPIO_FN_KEYOUT5_IN5,
222}; 222};
223 223
224enum {
225 HWBLK_UNKNOWN = 0,
226 HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_URAM, HWBLK_XYMEM,
227 HWBLK_INTC, HWBLK_DMAC, HWBLK_SHYWAY, HWBLK_HUDI,
228 HWBLK_UBC, HWBLK_TMU, HWBLK_CMT, HWBLK_RWDT, HWBLK_FLCTL,
229 HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, HWBLK_SIO,
230 HWBLK_SIOF0, HWBLK_SIOF1, HWBLK_IIC, HWBLK_RTC,
231 HWBLK_TPU, HWBLK_IRDA, HWBLK_SDHI, HWBLK_SIM, HWBLK_KEYSC,
232 HWBLK_TSIF, HWBLK_USBF, HWBLK_2DG, HWBLK_SIU, HWBLK_VOU,
233 HWBLK_JPU, HWBLK_BEU, HWBLK_CEU, HWBLK_VEU, HWBLK_VPU,
234 HWBLK_LCDC,
235 HWBLK_NR,
236};
237
224#endif /* __ASM_SH7722_H__ */ 238#endif /* __ASM_SH7722_H__ */
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7723.h b/arch/sh/include/cpu-sh4/cpu/sh7723.h
index 14c8ca936781..9b36fae72324 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7723.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7723.h
@@ -265,4 +265,21 @@ enum {
265 GPIO_FN_IDEA1, GPIO_FN_IDEA0, 265 GPIO_FN_IDEA1, GPIO_FN_IDEA0,
266}; 266};
267 267
268enum {
269 HWBLK_UNKNOWN = 0,
270 HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_L2C, HWBLK_ILMEM, HWBLK_FPU,
271 HWBLK_INTC, HWBLK_DMAC0, HWBLK_SHYWAY,
272 HWBLK_HUDI, HWBLK_DBG, HWBLK_UBC, HWBLK_SUBC,
273 HWBLK_TMU0, HWBLK_CMT, HWBLK_RWDT, HWBLK_DMAC1, HWBLK_TMU1,
274 HWBLK_FLCTL,
275 HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2,
276 HWBLK_SCIF3, HWBLK_SCIF4, HWBLK_SCIF5,
277 HWBLK_MSIOF0, HWBLK_MSIOF1, HWBLK_MERAM, HWBLK_IIC, HWBLK_RTC,
278 HWBLK_ATAPI, HWBLK_ADC, HWBLK_TPU, HWBLK_IRDA, HWBLK_TSIF, HWBLK_ICB,
279 HWBLK_SDHI0, HWBLK_SDHI1, HWBLK_KEYSC, HWBLK_USB,
280 HWBLK_2DG, HWBLK_SIU, HWBLK_VEU2H1, HWBLK_VOU, HWBLK_BEU, HWBLK_CEU,
281 HWBLK_VEU2H0, HWBLK_VPU, HWBLK_LCDC,
282 HWBLK_NR,
283};
284
268#endif /* __ASM_SH7723_H__ */ 285#endif /* __ASM_SH7723_H__ */
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7724.h b/arch/sh/include/cpu-sh4/cpu/sh7724.h
index 66fd1184359e..0cd1f71a1116 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7724.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7724.h
@@ -266,4 +266,21 @@ enum {
266 GPIO_FN_INTC_IRQ1, GPIO_FN_INTC_IRQ0, 266 GPIO_FN_INTC_IRQ1, GPIO_FN_INTC_IRQ0,
267}; 267};
268 268
269enum {
270 HWBLK_UNKNOWN = 0,
271 HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_RSMEM, HWBLK_ILMEM, HWBLK_L2C,
272 HWBLK_FPU, HWBLK_INTC, HWBLK_DMAC0, HWBLK_SHYWAY,
273 HWBLK_HUDI, HWBLK_DBG, HWBLK_UBC,
274 HWBLK_TMU0, HWBLK_CMT, HWBLK_RWDT, HWBLK_DMAC1, HWBLK_TMU1,
275 HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, HWBLK_SCIF3,
276 HWBLK_SCIF4, HWBLK_SCIF5, HWBLK_MSIOF0, HWBLK_MSIOF1,
277 HWBLK_KEYSC, HWBLK_RTC, HWBLK_IIC0, HWBLK_IIC1,
278 HWBLK_MMC, HWBLK_ETHER, HWBLK_ATAPI, HWBLK_TPU, HWBLK_IRDA,
279 HWBLK_TSIF, HWBLK_USB1, HWBLK_USB0, HWBLK_2DG,
280 HWBLK_SDHI0, HWBLK_SDHI1, HWBLK_VEU1, HWBLK_CEU1, HWBLK_BEU1,
281 HWBLK_2DDMAC, HWBLK_SPU, HWBLK_JPU, HWBLK_VOU,
282 HWBLK_BEU0, HWBLK_CEU0, HWBLK_VEU0, HWBLK_VPU, HWBLK_LCDC,
283 HWBLK_NR,
284};
285
269#endif /* __ASM_SH7724_H__ */ 286#endif /* __ASM_SH7724_H__ */
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7757.h b/arch/sh/include/cpu-sh4/cpu/sh7757.h
new file mode 100644
index 000000000000..f4d267efad71
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7757.h
@@ -0,0 +1,243 @@
1#ifndef __ASM_SH7757_H__
2#define __ASM_SH7757_H__
3
4enum {
5 /* PTA */
6 GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
7 GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
8
9 /* PTB */
10 GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
11 GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
12
13 /* PTC */
14 GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4,
15 GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0,
16
17 /* PTD */
18 GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
19 GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
20
21 /* PTE */
22 GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4,
23 GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0,
24
25 /* PTF */
26 GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4,
27 GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0,
28
29 /* PTG */
30 GPIO_PTG7, GPIO_PTG6, GPIO_PTG5, GPIO_PTG4,
31 GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0,
32
33 /* PTH */
34 GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4,
35 GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
36
37 /* PTI */
38 GPIO_PTI7, GPIO_PTI6, GPIO_PTI5, GPIO_PTI4,
39 GPIO_PTI3, GPIO_PTI2, GPIO_PTI1, GPIO_PTI0,
40
41 /* PTJ */
42 GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ4,
43 GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0,
44
45 /* PTK */
46 GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4,
47 GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
48
49 /* PTL */
50 GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4,
51 GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0,
52
53 /* PTM */
54 GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
55 GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
56
57 /* PTN */
58 GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4,
59 GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,
60
61 /* PTO */
62 GPIO_PTO7, GPIO_PTO6, GPIO_PTO5, GPIO_PTO4,
63 GPIO_PTO3, GPIO_PTO2, GPIO_PTO1, GPIO_PTO0,
64
65 /* PTP */
66 GPIO_PTP6, GPIO_PTP5, GPIO_PTP4,
67 GPIO_PTP3, GPIO_PTP2, GPIO_PTP1, GPIO_PTP0,
68
69 /* PTQ */
70 GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,
71 GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,
72
73 /* PTR */
74 GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4,
75 GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
76
77 /* PTS */
78 GPIO_PTS7, GPIO_PTS6, GPIO_PTS5, GPIO_PTS4,
79 GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
80
81 /* PTT */
82 GPIO_PTT5, GPIO_PTT4,
83 GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0,
84
85 /* PTU */
86 GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4,
87 GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0,
88
89 /* PTV */
90 GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4,
91 GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
92
93 /* PTW */
94 GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4,
95 GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0,
96
97 /* PTX */
98 GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4,
99 GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0,
100
101 /* PTY */
102 GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4,
103 GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0,
104
105 /* PTZ */
106 GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4,
107 GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0,
108
109
110 /* PTA (mobule: LBSC, CPG, LPC) */
111 GPIO_FN_BS, GPIO_FN_RDWR, GPIO_FN_WE1, GPIO_FN_RDY,
112 GPIO_FN_MD10, GPIO_FN_MD9, GPIO_FN_MD8,
113 GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4,
114 GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0,
115
116 /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
117 GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
118 GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
119 GPIO_FN_ET0_MDC, GPIO_FN_ET0_MDIO,
120 GPIO_FN_ET1_MDC, GPIO_FN_ET1_MDIO,
121 GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST,
122 GPIO_FN_WPSZ1, GPIO_FN_WPSZ0, GPIO_FN_FWID, GPIO_FN_FLSHSZ,
123 GPIO_FN_LPC_SPIEN, GPIO_FN_BASEL,
124
125 /* PTC (mobule: SD) */
126 GPIO_FN_SD_WP, GPIO_FN_SD_CD, GPIO_FN_SD_CLK, GPIO_FN_SD_CMD,
127 GPIO_FN_SD_D3, GPIO_FN_SD_D2, GPIO_FN_SD_D1, GPIO_FN_SD_D0,
128
129 /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */
130 GPIO_FN_IRQ7, GPIO_FN_IRQ6, GPIO_FN_IRQ5, GPIO_FN_IRQ4,
131 GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0,
132 GPIO_FN_MD6, GPIO_FN_MD5, GPIO_FN_MD3, GPIO_FN_MD2,
133 GPIO_FN_MD1, GPIO_FN_MD0, GPIO_FN_ADTRG1, GPIO_FN_ADTRG0,
134
135 /* PTE (mobule: EtherC) */
136 GPIO_FN_ET0_CRS_DV, GPIO_FN_ET0_TXD1,
137 GPIO_FN_ET0_TXD0, GPIO_FN_ET0_TX_EN,
138 GPIO_FN_ET0_REF_CLK, GPIO_FN_ET0_RXD1,
139 GPIO_FN_ET0_RXD0, GPIO_FN_ET0_RX_ER,
140
141 /* PTF (mobule: EtherC) */
142 GPIO_FN_ET1_CRS_DV, GPIO_FN_ET1_TXD1,
143 GPIO_FN_ET1_TXD0, GPIO_FN_ET1_TX_EN,
144 GPIO_FN_ET1_REF_CLK, GPIO_FN_ET1_RXD1,
145 GPIO_FN_ET1_RXD0, GPIO_FN_ET1_RX_ER,
146
147 /* PTG (mobule: SYSTEM, PWMX, LPC) */
148 GPIO_FN_STATUS0, GPIO_FN_STATUS1,
149 GPIO_FN_PWX0, GPIO_FN_PWX1, GPIO_FN_PWX2, GPIO_FN_PWX3,
150 GPIO_FN_SERIRQ, GPIO_FN_CLKRUN, GPIO_FN_LPCPD, GPIO_FN_LDRQ,
151
152 /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */
153 GPIO_FN_TCLK, GPIO_FN_RXD4, GPIO_FN_TXD4,
154 GPIO_FN_SP1_MOSI, GPIO_FN_SP1_MISO,
155 GPIO_FN_SP1_SCK, GPIO_FN_SP1_SCK_FB,
156 GPIO_FN_SP1_SS0, GPIO_FN_SP1_SS1,
157 GPIO_FN_SP0_SS1,
158
159 /* PTI (mobule: INTC) */
160 GPIO_FN_IRQ15, GPIO_FN_IRQ14, GPIO_FN_IRQ13, GPIO_FN_IRQ12,
161 GPIO_FN_IRQ11, GPIO_FN_IRQ10, GPIO_FN_IRQ9, GPIO_FN_IRQ8,
162
163 /* PTJ (mobule: SCIF234, SERMUX) */
164 GPIO_FN_RXD3, GPIO_FN_TXD3, GPIO_FN_RXD2, GPIO_FN_TXD2,
165 GPIO_FN_COM1_TXD, GPIO_FN_COM1_RXD,
166 GPIO_FN_COM1_RTS, GPIO_FN_COM1_CTS,
167
168 /* PTK (mobule: SERMUX) */
169 GPIO_FN_COM2_TXD, GPIO_FN_COM2_RXD,
170 GPIO_FN_COM2_RTS, GPIO_FN_COM2_CTS,
171 GPIO_FN_COM2_DTR, GPIO_FN_COM2_DSR,
172 GPIO_FN_COM2_DCD, GPIO_FN_COM2_RI,
173
174 /* PTL (mobule: SERMUX) */
175 GPIO_FN_RAC_TXD, GPIO_FN_RAC_RXD,
176 GPIO_FN_RAC_RTS, GPIO_FN_RAC_CTS,
177 GPIO_FN_RAC_DTR, GPIO_FN_RAC_DSR,
178 GPIO_FN_RAC_DCD, GPIO_FN_RAC_RI,
179
180 /* PTM (mobule: IIC, LPC) */
181 GPIO_FN_SDA6, GPIO_FN_SCL6, GPIO_FN_SDA7, GPIO_FN_SCL7,
182 GPIO_FN_WP, GPIO_FN_FMS0, GPIO_FN_FMS1,
183
184 /* PTN (mobule: SCIF234, EVC) */
185 GPIO_FN_SCK2, GPIO_FN_RTS4, GPIO_FN_RTS3, GPIO_FN_RTS2,
186 GPIO_FN_CTS4, GPIO_FN_CTS3, GPIO_FN_CTS2,
187 GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_EVENT5, GPIO_FN_EVENT4,
188 GPIO_FN_EVENT3, GPIO_FN_EVENT2, GPIO_FN_EVENT1, GPIO_FN_EVENT0,
189
190 /* PTO (mobule: SGPIO) */
191 GPIO_FN_SGPIO0_CLK, GPIO_FN_SGPIO0_LOAD,
192 GPIO_FN_SGPIO0_DI, GPIO_FN_SGPIO0_DO,
193 GPIO_FN_SGPIO1_CLK, GPIO_FN_SGPIO1_LOAD,
194 GPIO_FN_SGPIO1_DI, GPIO_FN_SGPIO1_DO,
195
196 /* PTP (mobule: JMC, SCIF234) */
197 GPIO_FN_JMCTCK, GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI,
198 GPIO_FN_JMCRST, GPIO_FN_SCK4, GPIO_FN_SCK3,
199
200 /* PTQ (mobule: LPC) */
201 GPIO_FN_LAD3, GPIO_FN_LAD2, GPIO_FN_LAD1, GPIO_FN_LAD0,
202 GPIO_FN_LFRAME, GPIO_FN_LRESET, GPIO_FN_LCLK,
203
204 /* PTR (mobule: GRA, IIC) */
205 GPIO_FN_DDC3, GPIO_FN_DDC2,
206 GPIO_FN_SDA8, GPIO_FN_SCL8, GPIO_FN_SDA2, GPIO_FN_SCL2,
207 GPIO_FN_SDA1, GPIO_FN_SCL1, GPIO_FN_SDA0, GPIO_FN_SCL0,
208
209 /* PTS (mobule: GRA, IIC) */
210 GPIO_FN_DDC1, GPIO_FN_DDC0,
211 GPIO_FN_SDA9, GPIO_FN_SCL9, GPIO_FN_SDA5, GPIO_FN_SCL5,
212 GPIO_FN_SDA4, GPIO_FN_SCL4, GPIO_FN_SDA3, GPIO_FN_SCL3,
213
214 /* PTT (mobule: SYSTEM, PWMX) */
215 GPIO_FN_AUDSYNC, GPIO_FN_AUDCK,
216 GPIO_FN_AUDATA3, GPIO_FN_AUDATA2,
217 GPIO_FN_AUDATA1, GPIO_FN_AUDATA0,
218 GPIO_FN_PWX7, GPIO_FN_PWX6, GPIO_FN_PWX5, GPIO_FN_PWX4,
219
220 /* PTU (mobule: LBSC, DMAC) */
221 GPIO_FN_CS6, GPIO_FN_CS5, GPIO_FN_CS4, GPIO_FN_CS0,
222 GPIO_FN_RD, GPIO_FN_WE0, GPIO_FN_A25, GPIO_FN_A24,
223 GPIO_FN_DREQ0, GPIO_FN_DACK0,
224
225 /* PTV (mobule: LBSC, DMAC) */
226 GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20,
227 GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16,
228 GPIO_FN_TEND0, GPIO_FN_DREQ1, GPIO_FN_DACK1, GPIO_FN_TEND1,
229
230 /* PTW (mobule: LBSC) */
231 GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12,
232 GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8,
233
234 /* PTX (mobule: LBSC) */
235 GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4,
236 GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0,
237
238 /* PTY (mobule: LBSC) */
239 GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
240 GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
241};
242
243#endif /* __ASM_SH7757_H__ */
diff --git a/arch/sh/include/cpu-sh5/cpu/cacheflush.h b/arch/sh/include/cpu-sh5/cpu/cacheflush.h
deleted file mode 100644
index 5a11f0b7e66a..000000000000
--- a/arch/sh/include/cpu-sh5/cpu/cacheflush.h
+++ /dev/null
@@ -1,33 +0,0 @@
1#ifndef __ASM_SH_CPU_SH5_CACHEFLUSH_H
2#define __ASM_SH_CPU_SH5_CACHEFLUSH_H
3
4#ifndef __ASSEMBLY__
5
6struct vm_area_struct;
7struct page;
8struct mm_struct;
9
10extern void flush_cache_all(void);
11extern void flush_cache_mm(struct mm_struct *mm);
12extern void flush_cache_sigtramp(unsigned long vaddr);
13extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
14 unsigned long end);
15extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
16extern void flush_dcache_page(struct page *pg);
17extern void flush_icache_range(unsigned long start, unsigned long end);
18extern void flush_icache_user_range(struct vm_area_struct *vma,
19 struct page *page, unsigned long addr,
20 int len);
21
22#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
23
24#define flush_dcache_mmap_lock(mapping) do { } while (0)
25#define flush_dcache_mmap_unlock(mapping) do { } while (0)
26
27#define flush_icache_page(vma, page) do { } while (0)
28void p3_cache_init(void);
29
30#endif /* __ASSEMBLY__ */
31
32#endif /* __ASM_SH_CPU_SH5_CACHEFLUSH_H */
33
diff --git a/arch/sh/include/mach-common/mach/migor.h b/arch/sh/include/mach-common/mach/migor.h
deleted file mode 100644
index e451f0229e00..000000000000
--- a/arch/sh/include/mach-common/mach/migor.h
+++ /dev/null
@@ -1,64 +0,0 @@
1#ifndef __ASM_SH_MIGOR_H
2#define __ASM_SH_MIGOR_H
3
4/*
5 * linux/include/asm-sh/migor.h
6 *
7 * Copyright (C) 2008 Renesas Solutions
8 *
9 * Portions Copyright (C) 2007 Nobuhiro Iwamatsu
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 *
15 */
16#include <asm/addrspace.h>
17
18/* GPIO */
19#define PORT_PACR 0xa4050100
20#define PORT_PDCR 0xa4050106
21#define PORT_PECR 0xa4050108
22#define PORT_PHCR 0xa405010e
23#define PORT_PJCR 0xa4050110
24#define PORT_PKCR 0xa4050112
25#define PORT_PLCR 0xa4050114
26#define PORT_PMCR 0xa4050116
27#define PORT_PRCR 0xa405011c
28#define PORT_PTCR 0xa4050140
29#define PORT_PUCR 0xa4050142
30#define PORT_PVCR 0xa4050144
31#define PORT_PWCR 0xa4050146
32#define PORT_PXCR 0xa4050148
33#define PORT_PYCR 0xa405014a
34#define PORT_PZCR 0xa405014c
35#define PORT_PADR 0xa4050120
36#define PORT_PHDR 0xa405012e
37#define PORT_PTDR 0xa4050160
38#define PORT_PWDR 0xa4050166
39
40#define PORT_HIZCRA 0xa4050158
41#define PORT_HIZCRC 0xa405015c
42
43#define PORT_MSELCRB 0xa4050182
44
45#define PORT_PSELA 0xa405014e
46#define PORT_PSELB 0xa4050150
47#define PORT_PSELC 0xa4050152
48#define PORT_PSELD 0xa4050154
49#define PORT_PSELE 0xa4050156
50
51#define PORT_HIZCRA 0xa4050158
52#define PORT_HIZCRB 0xa405015a
53#define PORT_HIZCRC 0xa405015c
54
55#define BSC_CS4BCR 0xfec10010
56#define BSC_CS6ABCR 0xfec1001c
57#define BSC_CS4WCR 0xfec10030
58
59#include <video/sh_mobile_lcdc.h>
60
61int migor_lcd_qvga_setup(void *board_data, void *sys_ops_handle,
62 struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
63
64#endif /* __ASM_SH_MIGOR_H */
diff --git a/arch/sh/include/mach-common/mach/romimage.h b/arch/sh/include/mach-common/mach/romimage.h
new file mode 100644
index 000000000000..267e24112d82
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/romimage.h
@@ -0,0 +1 @@
/* do nothing here by default */
diff --git a/arch/sh/include/mach-common/mach/sh7785lcr.h b/arch/sh/include/mach-common/mach/sh7785lcr.h
index 90011d435f30..1292ae5c21b3 100644
--- a/arch/sh/include/mach-common/mach/sh7785lcr.h
+++ b/arch/sh/include/mach-common/mach/sh7785lcr.h
@@ -35,6 +35,8 @@
35#define PCA9564_ADDR 0x06000000 /* I2C */ 35#define PCA9564_ADDR 0x06000000 /* I2C */
36#define PCA9564_SIZE 0x00000100 36#define PCA9564_SIZE 0x00000100
37 37
38#define PCA9564_PROTO_32BIT_ADDR 0x14000000
39
38#define SM107_MEM_ADDR 0x10000000 40#define SM107_MEM_ADDR 0x10000000
39#define SM107_MEM_SIZE 0x00e00000 41#define SM107_MEM_SIZE 0x00e00000
40#define SM107_REG_ADDR 0x13e00000 42#define SM107_REG_ADDR 0x13e00000
diff --git a/arch/sh/include/mach-ecovec24/mach/partner-jet-setup.txt b/arch/sh/include/mach-ecovec24/mach/partner-jet-setup.txt
new file mode 100644
index 000000000000..8b8e4fa1fee9
--- /dev/null
+++ b/arch/sh/include/mach-ecovec24/mach/partner-jet-setup.txt
@@ -0,0 +1,82 @@
1LIST "partner-jet-setup.txt"
2LIST "(C) Copyright 2009 Renesas Solutions Corp"
3LIST "Kuninori Morimoto <morimoto.kuninori@renesas.com>"
4LIST "--------------------------------"
5LIST "zImage (RAM boot)"
6LIST "This script can be used to boot the kernel from RAM via JTAG:"
7LIST "> < partner-jet-setup.txt"
8LIST "> RD zImage, 0xa8800000"
9LIST "> G=0xa8800000"
10LIST "--------------------------------"
11LIST "romImage (Flash boot)"
12LIST "Use the following command to burn the zImage to flash via JTAG:"
13LIST "> RD romImage, 0"
14LIST "--------------------------------"
15
16LIST "disable watchdog"
17EW 0xa4520004, 0xa507
18
19LIST "MMU"
20ED 0xff000010, 0x00000004
21
22LIST "setup clocks"
23ED 0xa4150024, 0x00004000
24ED 0xa4150000, 0x8E003508
25ED 0xa4150004, 0x00000000
26
27WAIT 1
28
29LIST "BSC"
30ED 0xff800020, 0xa5a50000
31ED 0xfec10000, 0x00000013
32ED 0xfec10004, 0x11110400
33ED 0xfec10024, 0x00000440
34
35WAIT 1
36
37LIST "setup sdram"
38ED 0xfd000108, 0x00000181
39ED 0xfd000020, 0x015B0002
40ED 0xfd000030, 0x03061502
41ED 0xfd000034, 0x02020102
42ED 0xfd000038, 0x01090305
43ED 0xfd00003c, 0x00000002
44ED 0xfd000008, 0x00000005
45ED 0xfd000018, 0x00000001
46
47WAIT 1
48
49ED 0xfd000014, 0x00000002
50ED 0xfd000060, 0x00020000
51ED 0xfd000060, 0x00030000
52ED 0xfd000060, 0x00010040
53ED 0xfd000060, 0x00000532
54ED 0xfd000014, 0x00000002
55ED 0xfd000014, 0x00000004
56ED 0xfd000014, 0x00000004
57ED 0xfd000060, 0x00000432
58ED 0xfd000060, 0x000103C0
59ED 0xfd000060, 0x00010040
60
61WAIT 1
62
63ED 0xfd000010, 0x00000001
64ED 0xfd000044, 0x00000613
65ED 0xfd000048, 0x238C003A
66ED 0xfd000014, 0x00000002
67
68LIST "Dummy read"
69DD 0x0c400000, 0x0c400000
70
71ED 0xfd000014, 0x00000002
72ED 0xfd000014, 0x00000004
73ED 0xfd000108, 0x00000080
74ED 0xfd000040, 0x00010000
75
76WAIT 1
77
78LIST "setup cache"
79ED 0xff00001c, 0x0000090b
80
81LIST "disable USB"
82EW 0xA4D80000, 0x0000
diff --git a/arch/sh/include/mach-ecovec24/mach/romimage.h b/arch/sh/include/mach-ecovec24/mach/romimage.h
new file mode 100644
index 000000000000..1c8787ecb1c1
--- /dev/null
+++ b/arch/sh/include/mach-ecovec24/mach/romimage.h
@@ -0,0 +1,20 @@
1/* EcoVec board specific boot code:
2 * converts the "partner-jet-script.txt" script into assembly
3 * the assembly code is the first code to be executed in the romImage
4 */
5
6#include <asm/romimage-macros.h>
7#include "partner-jet-setup.txt"
8
9 /* execute icbi after enabling cache */
10 mov.l 1f, r0
11 icbi @r0
12
13 /* jump to cached area */
14 mova 2f, r0
15 jmp @r0
16 nop
17
18 .align 2
191 : .long 0xa8000000
202 :
diff --git a/arch/sh/include/mach-kfr2r09/mach/kfr2r09.h b/arch/sh/include/mach-kfr2r09/mach/kfr2r09.h
new file mode 100644
index 000000000000..174374e19547
--- /dev/null
+++ b/arch/sh/include/mach-kfr2r09/mach/kfr2r09.h
@@ -0,0 +1,21 @@
1#ifndef __ASM_SH_KFR2R09_H
2#define __ASM_SH_KFR2R09_H
3
4#include <video/sh_mobile_lcdc.h>
5
6#ifdef CONFIG_FB_SH_MOBILE_LCDC
7void kfr2r09_lcd_on(void *board_data);
8void kfr2r09_lcd_off(void *board_data);
9int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle,
10 struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
11#else
12static inline void kfr2r09_lcd_on(void *board_data) {}
13static inline void kfr2r09_lcd_off(void *board_data) {}
14static inline int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle,
15 struct sh_mobile_lcdc_sys_bus_ops *sys_ops)
16{
17 return -ENODEV;
18}
19#endif
20
21#endif /* __ASM_SH_KFR2R09_H */
diff --git a/arch/sh/include/mach-kfr2r09/mach/partner-jet-setup.txt b/arch/sh/include/mach-kfr2r09/mach/partner-jet-setup.txt
new file mode 100644
index 000000000000..3a65503714ee
--- /dev/null
+++ b/arch/sh/include/mach-kfr2r09/mach/partner-jet-setup.txt
@@ -0,0 +1,143 @@
1LIST "partner-jet-setup.txt - 20090729 Magnus Damm"
2LIST "set up enough of the kfr2r09 hardware to boot the kernel"
3
4LIST "zImage (RAM boot)"
5LIST "This script can be used to boot the kernel from RAM via JTAG:"
6LIST "> < partner-jet-setup.txt"
7LIST "> RD zImage, 0xa8800000"
8LIST "> G=0xa8800000"
9
10LIST "romImage (Flash boot)"
11LIST "Use the following command to burn the zImage to flash via JTAG:"
12LIST "> RD romImage, 0"
13
14LIST "--------------------------------"
15
16LIST "disable watchdog"
17EW 0xa4520004, 0xa507
18
19LIST "invalidate instruction cache"
20ED 0xff00001c, 0x00000800
21
22LIST "invalidate TLBs"
23ED 0xff000010, 0x00000004
24
25LIST "select mode for cs5 + cs6"
26ED 0xff800020, 0xa5a50001
27ED 0xfec10000, 0x0000001b
28
29LIST "setup clocks"
30LIST "The PLL and FLL values are updated here for the optimal"
31LIST "RF frequency and improved reception sensitivity."
32ED 0xa4150004, 0x00000050
33ED 0xa4150000, 0x91053508
34WAIT 1
35ED 0xa4150050, 0x00000340
36ED 0xa4150024, 0x00005000
37
38LIST "setup pins"
39EB 0xa4050120, 0x00
40EB 0xa4050122, 0x00
41EB 0xa4050124, 0x00
42EB 0xa4050126, 0x00
43EB 0xa4050128, 0xA0
44EB 0xa405012A, 0x10
45EB 0xa405012C, 0x00
46EB 0xa405012E, 0x00
47EB 0xa4050130, 0x00
48EB 0xa4050132, 0x00
49EB 0xa4050134, 0x01
50EB 0xa4050136, 0x40
51EB 0xa4050138, 0x00
52EB 0xa405013A, 0x00
53EB 0xa405013C, 0x00
54EB 0xa405013E, 0x20
55EB 0xa4050160, 0x00
56EB 0xa4050162, 0x40
57EB 0xa4050164, 0x03
58EB 0xa4050166, 0x00
59EB 0xa4050168, 0x00
60EB 0xa405016A, 0x00
61EB 0xa405016C, 0x00
62
63EW 0xa405014E, 0x5660
64EW 0xa4050150, 0x0145
65EW 0xa4050152, 0x1550
66EW 0xa4050154, 0x0200
67EW 0xa4050156, 0x0040
68
69EW 0xa4050158, 0x0000
70EW 0xa405015a, 0x0000
71EW 0xa405015c, 0x0000
72EW 0xa405015e, 0x0000
73
74EW 0xa4050180, 0x0000
75EW 0xa4050182, 0x8002
76EW 0xa4050184, 0x0000
77
78EW 0xa405018a, 0x9991
79EW 0xa405018c, 0x8011
80EW 0xa405018e, 0x9550
81
82EW 0xa4050100, 0x0000
83EW 0xa4050102, 0x5540
84EW 0xa4050104, 0x0000
85EW 0xa4050106, 0x0000
86EW 0xa4050108, 0x4550
87EW 0xa405010a, 0x0130
88EW 0xa405010c, 0x0555
89EW 0xa405010e, 0x0000
90EW 0xa4050110, 0x0000
91EW 0xa4050112, 0xAAA8
92EW 0xa4050114, 0x8305
93EW 0xa4050116, 0x10F0
94EW 0xa4050118, 0x0F50
95EW 0xa405011a, 0x0000
96EW 0xa405011c, 0x0000
97EW 0xa405011e, 0x0555
98EW 0xa4050140, 0x0000
99EW 0xa4050142, 0x5141
100EW 0xa4050144, 0x5005
101EW 0xa4050146, 0xAAA9
102EW 0xa4050148, 0xFAA9
103EW 0xa405014a, 0x3000
104EW 0xa405014c, 0x0000
105
106LIST "setup sdram"
107ED 0xFD000108, 0x40000301
108ED 0xFD000020, 0x011B0002
109ED 0xFD000030, 0x03060E02
110ED 0xFD000034, 0x01020102
111ED 0xFD000038, 0x01090406
112ED 0xFD000008, 0x00000004
113ED 0xFD000040, 0x00000001
114ED 0xFD000040, 0x00000000
115ED 0xFD000018, 0x00000001
116
117WAIT 1
118
119ED 0xFD000014, 0x00000002
120ED 0xFD000060, 0x00000032
121ED 0xFD000060, 0x00020000
122ED 0xFD000014, 0x00000004
123ED 0xFD000014, 0x00000004
124ED 0xFD000010, 0x00000001
125ED 0xFD000044, 0x000004AF
126ED 0xFD000048, 0x20CF0037
127
128LIST "read 16 bytes from sdram"
129DD 0xa8000000, 0xa8000000, 1
130DD 0xa8000004, 0xa8000004, 1
131DD 0xa8000008, 0xa8000008, 1
132DD 0xa800000c, 0xa800000c, 1
133
134ED 0xFD000014, 0x00000002
135ED 0xFD000014, 0x00000004
136ED 0xFD000108, 0x40000300
137ED 0xFD000040, 0x00010000
138
139LIST "write to internal ram"
140ED 0xfd8007fc, 0
141
142LIST "setup cache"
143ED 0xff00001c, 0x0000090b
diff --git a/arch/sh/include/mach-kfr2r09/mach/romimage.h b/arch/sh/include/mach-kfr2r09/mach/romimage.h
new file mode 100644
index 000000000000..a110823f2bde
--- /dev/null
+++ b/arch/sh/include/mach-kfr2r09/mach/romimage.h
@@ -0,0 +1,20 @@
1/* kfr2r09 board specific boot code:
2 * converts the "partner-jet-script.txt" script into assembly
3 * the assembly code is the first code to be executed in the romImage
4 */
5
6#include <asm/romimage-macros.h>
7#include "partner-jet-setup.txt"
8
9 /* execute icbi after enabling cache */
10 mov.l 1f, r0
11 icbi @r0
12
13 /* jump to cached area */
14 mova 2f, r0
15 jmp @r0
16 nop
17
18 .align 2
191: .long 0xa8000000
202:
diff --git a/arch/sh/include/mach-migor/mach/migor.h b/arch/sh/include/mach-migor/mach/migor.h
new file mode 100644
index 000000000000..cee6cb88e020
--- /dev/null
+++ b/arch/sh/include/mach-migor/mach/migor.h
@@ -0,0 +1,14 @@
1#ifndef __ASM_SH_MIGOR_H
2#define __ASM_SH_MIGOR_H
3
4#define PORT_MSELCRB 0xa4050182
5#define BSC_CS4BCR 0xfec10010
6#define BSC_CS6ABCR 0xfec1001c
7#define BSC_CS4WCR 0xfec10030
8
9#include <video/sh_mobile_lcdc.h>
10
11int migor_lcd_qvga_setup(void *board_data, void *sys_ops_handle,
12 struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
13
14#endif /* __ASM_SH_MIGOR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 04:48:37 -0500