aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh/include
diff options
context:
space:
mode:
authorPaul Mundt <lethal@linux-sh.org>2008-10-01 03:13:54 -0400
committerPaul Mundt <lethal@linux-sh.org>2008-10-01 03:13:54 -0400
commitbbfbd8b151fe35c9a1180a7f5254c5d6b8387cc0 (patch)
treee39f364221492d64c7f8fd80c1ceb2065350c4d7 /arch/sh/include
parent7ff731aeba1cdac473c818a9884eb94ddad18e7f (diff)
sh: Move the shared INTC code out to drivers/sh/
The INTC code will be re-used across different architectures, so move this out to drivers/sh/ and include/linux/sh_intc.h respectively. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include')
-rw-r--r--arch/sh/include/asm/hw_irq.h92
1 files changed, 2 insertions, 90 deletions
diff --git a/arch/sh/include/asm/hw_irq.h b/arch/sh/include/asm/hw_irq.h
index d557b00111bf..603cdde813d1 100644
--- a/arch/sh/include/asm/hw_irq.h
+++ b/arch/sh/include/asm/hw_irq.h
@@ -2,6 +2,7 @@
2#define __ASM_SH_HW_IRQ_H 2#define __ASM_SH_HW_IRQ_H
3 3
4#include <linux/init.h> 4#include <linux/init.h>
5#include <linux/sh_intc.h>
5#include <asm/atomic.h> 6#include <asm/atomic.h>
6 7
7extern atomic_t irq_err_count; 8extern atomic_t irq_err_count;
@@ -23,101 +24,12 @@ struct ipr_desc {
23 24
24void register_ipr_controller(struct ipr_desc *); 25void register_ipr_controller(struct ipr_desc *);
25 26
26typedef unsigned char intc_enum;
27
28struct intc_vect {
29 intc_enum enum_id;
30 unsigned short vect;
31};
32
33#define INTC_VECT(enum_id, vect) { enum_id, vect }
34#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
35
36struct intc_group {
37 intc_enum enum_id;
38 intc_enum enum_ids[32];
39};
40
41#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
42
43struct intc_mask_reg {
44 unsigned long set_reg, clr_reg, reg_width;
45 intc_enum enum_ids[32];
46#ifdef CONFIG_SMP
47 unsigned long smp;
48#endif
49};
50
51struct intc_prio_reg {
52 unsigned long set_reg, clr_reg, reg_width, field_width;
53 intc_enum enum_ids[16];
54#ifdef CONFIG_SMP
55 unsigned long smp;
56#endif
57};
58
59struct intc_sense_reg {
60 unsigned long reg, reg_width, field_width;
61 intc_enum enum_ids[16];
62};
63
64#ifdef CONFIG_SMP
65#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8)
66#else
67#define INTC_SMP(stride, nr)
68#endif
69
70struct intc_desc {
71 struct intc_vect *vectors;
72 unsigned int nr_vectors;
73 struct intc_group *groups;
74 unsigned int nr_groups;
75 struct intc_mask_reg *mask_regs;
76 unsigned int nr_mask_regs;
77 struct intc_prio_reg *prio_regs;
78 unsigned int nr_prio_regs;
79 struct intc_sense_reg *sense_regs;
80 unsigned int nr_sense_regs;
81 char *name;
82#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
83 struct intc_mask_reg *ack_regs;
84 unsigned int nr_ack_regs;
85#endif
86};
87
88#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
89#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
90 mask_regs, prio_regs, sense_regs) \
91struct intc_desc symbol __initdata = { \
92 _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
93 _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
94 _INTC_ARRAY(sense_regs), \
95 chipname, \
96}
97
98#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
99#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \
100 mask_regs, prio_regs, sense_regs, ack_regs) \
101struct intc_desc symbol __initdata = { \
102 _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
103 _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
104 _INTC_ARRAY(sense_regs), \
105 chipname, \
106 _INTC_ARRAY(ack_regs), \
107}
108#endif
109
110void __init register_intc_controller(struct intc_desc *desc);
111int intc_set_priority(unsigned int irq, unsigned int prio);
112
113void __init plat_irq_setup(void); 27void __init plat_irq_setup(void);
114#ifdef CONFIG_CPU_SH3
115void __init plat_irq_setup_sh3(void); 28void __init plat_irq_setup_sh3(void);
116#endif 29void __init plat_irq_setup_pins(int mode);
117 30
118enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210, 31enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
119 IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK, 32 IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
120 IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 }; 33 IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
121void __init plat_irq_setup_pins(int mode);
122 34
123#endif /* __ASM_SH_HW_IRQ_H */ 35#endif /* __ASM_SH_HW_IRQ_H */