Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (26 commits)
  sh: Convert sh to use read/update_persistent_clock
  sh: Move PMB debugfs entry initialization to later stage
  sh: Fix up flush_cache_vmap() on SMP.
  sh: fix up MMU reset with variable PMB mapping sizes.
  sh: establish PMB mappings for NUMA nodes.
  sh: check for existing mappings for bolted PMB entries.
  sh: fixed virt/phys mapping helpers for PMB.
  sh: make pmb iomapping configurable.
  sh: reworked dynamic PMB mapping.
  sh: Fix up cpumask_of_pcibus() for the NUMA build.
  serial: sh-sci: Tidy up build warnings.
  sh: Fix up ctrl_read/write stragglers in migor setup.
  serial: sh-sci: Add DMA support.
  dmaengine: shdma: extend .device_terminate_all() to record partial transfer
  sh: merge sh7722 and sh7724 DMA register definitions
  sh: activate runtime PM for dmaengine on sh7722 and sh7724
  dmaengine: shdma: add runtime PM support.
  dmaengine: shdma: separate DMA headers.
  dmaengine: shdma: convert to platform device resources
  dmaengine: shdma: fix DMA error handling.
  ...

14 files changed, 339 insertions, 234 deletions

diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h
index da3ebec921a7..1f4e562c5e8c 100644
--- a/arch/sh/include/asm/cacheflush.h
+++ b/arch/sh/include/asm/cacheflush.h
@@ -86,8 +86,8 @@ extern void copy_from_user_page(struct vm_area_struct *vma,
         struct page *page, unsigned long vaddr, void *dst, const void *src,
         unsigned long len);
 
-#define flush_cache_vmap(start, end)            flush_cache_all()
-#define flush_cache_vunmap(start, end)          flush_cache_all()
+#define flush_cache_vmap(start, end)            local_flush_cache_all(NULL)
+#define flush_cache_vunmap(start, end)          local_flush_cache_all(NULL)
 
 #define flush_dcache_mmap_lock(mapping)         do { } while (0)
 #define flush_dcache_mmap_unlock(mapping)       do { } while (0)
diff --git a/arch/sh/include/asm/dma-register.h b/arch/sh/include/asm/dma-register.h
new file mode 100644
index 000000000000..51cd78feacff
--- /dev/null
+++ b/arch/sh/include/asm/dma-register.h
@@ -0,0 +1,51 @@
+/*
+ * Common header for the legacy SH DMA driver and the new dmaengine driver
+ *
+ * extracted from arch/sh/include/asm/dma-sh.h:
+ *
+ * Copyright (C) 2000  Takashi YOSHII
+ * Copyright (C) 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef DMA_REGISTER_H
+#define DMA_REGISTER_H
+
+/* DMA register */
+#define SAR     0x00
+#define DAR     0x04
+#define TCR     0x08
+#define CHCR    0x0C
+#define DMAOR   0x40
+
+/* DMAOR definitions */
+#define DMAOR_AE        0x00000004
+#define DMAOR_NMIF      0x00000002
+#define DMAOR_DME       0x00000001
+
+/* Definitions for the SuperH DMAC */
+#define REQ_L   0x00000000
+#define REQ_E   0x00080000
+#define RACK_H  0x00000000
+#define RACK_L  0x00040000
+#define ACK_R   0x00000000
+#define ACK_W   0x00020000
+#define ACK_H   0x00000000
+#define ACK_L   0x00010000
+#define DM_INC  0x00004000
+#define DM_DEC  0x00008000
+#define DM_FIX  0x0000c000
+#define SM_INC  0x00001000
+#define SM_DEC  0x00002000
+#define SM_FIX  0x00003000
+#define RS_IN   0x00000200
+#define RS_OUT  0x00000300
+#define TS_BLK  0x00000040
+#define TM_BUR  0x00000020
+#define CHCR_DE 0x00000001
+#define CHCR_TE 0x00000002
+#define CHCR_IE 0x00000004
+
+#endif
diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h
index e934a2e66651..f3acb8e34c6b 100644
--- a/arch/sh/include/asm/dma-sh.h
+++ b/arch/sh/include/asm/dma-sh.h
@@ -11,7 +11,8 @@
 #ifndef __DMA_SH_H
 #define __DMA_SH_H
 
-#include <asm/dma.h>
+#include <asm/dma-register.h>
+#include <cpu/dma-register.h>
 #include <cpu/dma.h>
 
 /* DMAOR contorl: The DMAOR access size is different by CPU.*/
@@ -53,34 +54,6 @@ static int dmte_irq_map[] __maybe_unused = {
 #endif
 };
 
-/* Definitions for the SuperH DMAC */
-#define REQ_L   0x00000000
-#define REQ_E   0x00080000
-#define RACK_H  0x00000000
-#define RACK_L  0x00040000
-#define ACK_R   0x00000000
-#define ACK_W   0x00020000
-#define ACK_H   0x00000000
-#define ACK_L   0x00010000
-#define DM_INC  0x00004000
-#define DM_DEC  0x00008000
-#define DM_FIX  0x0000c000
-#define SM_INC  0x00001000
-#define SM_DEC  0x00002000
-#define SM_FIX  0x00003000
-#define RS_IN   0x00000200
-#define RS_OUT  0x00000300
-#define TS_BLK  0x00000040
-#define TM_BUR  0x00000020
-#define CHCR_DE 0x00000001
-#define CHCR_TE 0x00000002
-#define CHCR_IE 0x00000004
-
-/* DMAOR definitions */
-#define DMAOR_AE        0x00000004
-#define DMAOR_NMIF      0x00000002
-#define DMAOR_DME       0x00000001
-
 /*
  * Define the default configuration for dual address memory-memory transfer.
  * The 0x400 value represents auto-request, external->external.
@@ -111,61 +84,4 @@ static u32 dma_base_addr[] __maybe_unused = {
 #endif
 };
 
-/* DMA register */
-#define SAR     0x00
-#define DAR     0x04
-#define TCR     0x08
-#define CHCR    0x0C
-#define DMAOR   0x40
-
-/*
- * for dma engine
- *
- * SuperH DMA mode
- */
-#define SHDMA_MIX_IRQ   (1 << 1)
-#define SHDMA_DMAOR1    (1 << 2)
-#define SHDMA_DMAE1     (1 << 3)
-
-enum sh_dmae_slave_chan_id {
-        SHDMA_SLAVE_SCIF0_TX,
-        SHDMA_SLAVE_SCIF0_RX,
-        SHDMA_SLAVE_SCIF1_TX,
-        SHDMA_SLAVE_SCIF1_RX,
-        SHDMA_SLAVE_SCIF2_TX,
-        SHDMA_SLAVE_SCIF2_RX,
-        SHDMA_SLAVE_SCIF3_TX,
-        SHDMA_SLAVE_SCIF3_RX,
-        SHDMA_SLAVE_SCIF4_TX,
-        SHDMA_SLAVE_SCIF4_RX,
-        SHDMA_SLAVE_SCIF5_TX,
-        SHDMA_SLAVE_SCIF5_RX,
-        SHDMA_SLAVE_SIUA_TX,
-        SHDMA_SLAVE_SIUA_RX,
-        SHDMA_SLAVE_SIUB_TX,
-        SHDMA_SLAVE_SIUB_RX,
-        SHDMA_SLAVE_NUMBER,     /* Must stay last */
-};
-
-struct sh_dmae_slave_config {
-        enum sh_dmae_slave_chan_id      slave_id;
-        dma_addr_t                      addr;
-        u32                             chcr;
-        char                            mid_rid;
-};
-
-struct sh_dmae_pdata {
-        unsigned int mode;
-        struct sh_dmae_slave_config *config;
-        int config_num;
-};
-
-struct device;
-
-struct sh_dmae_slave {
-        enum sh_dmae_slave_chan_id      slave_id; /* Set by the platform */
-        struct device                   *dma_dev; /* Set by the platform */
-        struct sh_dmae_slave_config     *config;  /* Set by the driver */
-};
-
 #endif /* __DMA_SH_H */
diff --git a/arch/sh/include/asm/dmaengine.h b/arch/sh/include/asm/dmaengine.h
new file mode 100644
index 000000000000..bf2f30cf0a27
--- /dev/null
+++ b/arch/sh/include/asm/dmaengine.h
@@ -0,0 +1,93 @@
+/*
+ * Header for the new SH dmaengine driver
+ *
+ * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef ASM_DMAENGINE_H
+#define ASM_DMAENGINE_H
+
+#include <linux/dmaengine.h>
+#include <linux/list.h>
+
+#include <asm/dma-register.h>
+
+#define SH_DMAC_MAX_CHANNELS    6
+
+enum sh_dmae_slave_chan_id {
+        SHDMA_SLAVE_SCIF0_TX,
+        SHDMA_SLAVE_SCIF0_RX,
+        SHDMA_SLAVE_SCIF1_TX,
+        SHDMA_SLAVE_SCIF1_RX,
+        SHDMA_SLAVE_SCIF2_TX,
+        SHDMA_SLAVE_SCIF2_RX,
+        SHDMA_SLAVE_SCIF3_TX,
+        SHDMA_SLAVE_SCIF3_RX,
+        SHDMA_SLAVE_SCIF4_TX,
+        SHDMA_SLAVE_SCIF4_RX,
+        SHDMA_SLAVE_SCIF5_TX,
+        SHDMA_SLAVE_SCIF5_RX,
+        SHDMA_SLAVE_SIUA_TX,
+        SHDMA_SLAVE_SIUA_RX,
+        SHDMA_SLAVE_SIUB_TX,
+        SHDMA_SLAVE_SIUB_RX,
+        SHDMA_SLAVE_NUMBER,     /* Must stay last */
+};
+
+struct sh_dmae_slave_config {
+        enum sh_dmae_slave_chan_id      slave_id;
+        dma_addr_t                      addr;
+        u32                             chcr;
+        char                            mid_rid;
+};
+
+struct sh_dmae_channel {
+        unsigned int    offset;
+        unsigned int    dmars;
+        unsigned int    dmars_bit;
+};
+
+struct sh_dmae_pdata {
+        struct sh_dmae_slave_config *slave;
+        int slave_num;
+        struct sh_dmae_channel *channel;
+        int channel_num;
+        unsigned int ts_low_shift;
+        unsigned int ts_low_mask;
+        unsigned int ts_high_shift;
+        unsigned int ts_high_mask;
+        unsigned int *ts_shift;
+        int ts_shift_num;
+        u16 dmaor_init;
+};
+
+struct device;
+
+/* Used by slave DMA clients to request DMA to/from a specific peripheral */
+struct sh_dmae_slave {
+        enum sh_dmae_slave_chan_id      slave_id; /* Set by the platform */
+        struct device                   *dma_dev; /* Set by the platform */
+        struct sh_dmae_slave_config     *config;  /* Set by the driver */
+};
+
+struct sh_dmae_regs {
+        u32 sar; /* SAR / source address */
+        u32 dar; /* DAR / destination address */
+        u32 tcr; /* TCR / transfer count */
+};
+
+struct sh_desc {
+        struct sh_dmae_regs hw;
+        struct list_head node;
+        struct dma_async_tx_descriptor async_tx;
+        enum dma_data_direction direction;
+        dma_cookie_t cookie;
+        size_t partial;
+        int chunks;
+        int mark;
+};
+
+#endif
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 7dab7b23a5ec..f689554e17c1 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -291,21 +291,21 @@ unsigned long long poke_real_address_q(unsigned long long addr,
  * doesn't exist, so everything must go through page tables.
  */
 #ifdef CONFIG_MMU
-void __iomem *__ioremap_caller(unsigned long offset, unsigned long size,
+void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size,
                                pgprot_t prot, void *caller);
 void __iounmap(void __iomem *addr);
 
 static inline void __iomem *
-__ioremap(unsigned long offset, unsigned long size, pgprot_t prot)
+__ioremap(phys_addr_t offset, unsigned long size, pgprot_t prot)
 {
         return __ioremap_caller(offset, size, prot, __builtin_return_address(0));
 }
 
 static inline void __iomem *
-__ioremap_29bit(unsigned long offset, unsigned long size, pgprot_t prot)
+__ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot)
 {
 #ifdef CONFIG_29BIT
-        unsigned long last_addr = offset + size - 1;
+        phys_addr_t last_addr = offset + size - 1;
 
         /*
          * For P1 and P2 space this is trivial, as everything is already
@@ -329,7 +329,7 @@ __ioremap_29bit(unsigned long offset, unsigned long size, pgprot_t prot)
 }
 
 static inline void __iomem *
-__ioremap_mode(unsigned long offset, unsigned long size, pgprot_t prot)
+__ioremap_mode(phys_addr_t offset, unsigned long size, pgprot_t prot)
 {
         void __iomem *ret;
 
@@ -349,35 +349,32 @@ __ioremap_mode(unsigned long offset, unsigned long size, pgprot_t prot)
 #define __iounmap(addr)                         do { } while (0)
 #endif /* CONFIG_MMU */
 
-static inline void __iomem *
-ioremap(unsigned long offset, unsigned long size)
+static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
 {
         return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE);
 }
 
 static inline void __iomem *
-ioremap_cache(unsigned long offset, unsigned long size)
+ioremap_cache(phys_addr_t offset, unsigned long size)
 {
         return __ioremap_mode(offset, size, PAGE_KERNEL);
 }
 
 #ifdef CONFIG_HAVE_IOREMAP_PROT
 static inline void __iomem *
-ioremap_prot(resource_size_t offset, unsigned long size, unsigned long flags)
+ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long flags)
 {
         return __ioremap_mode(offset, size, __pgprot(flags));
 }
 #endif
 
 #ifdef CONFIG_IOREMAP_FIXED
-extern void __iomem *ioremap_fixed(resource_size_t, unsigned long,
-                                   unsigned long, pgprot_t);
+extern void __iomem *ioremap_fixed(phys_addr_t, unsigned long, pgprot_t);
 extern int iounmap_fixed(void __iomem *);
 extern void ioremap_fixed_init(void);
 #else
 static inline void __iomem *
-ioremap_fixed(resource_size_t phys_addr, unsigned long offset,
-              unsigned long size, pgprot_t prot)
+ioremap_fixed(phys_addr_t phys_addr, unsigned long size, pgprot_t prot)
 {
         BUG();
         return NULL;
diff --git a/arch/sh/include/asm/mmu.h b/arch/sh/include/asm/mmu.h
index 15a05b615ba7..19fe84550b49 100644
--- a/arch/sh/include/asm/mmu.h
+++ b/arch/sh/include/asm/mmu.h
@@ -55,19 +55,29 @@ typedef struct {
 
 #ifdef CONFIG_PMB
 /* arch/sh/mm/pmb.c */
-long pmb_remap(unsigned long virt, unsigned long phys,
-               unsigned long size, pgprot_t prot);
-void pmb_unmap(unsigned long addr);
-void pmb_init(void);
 bool __in_29bit_mode(void);
+
+void pmb_init(void);
+int pmb_bolt_mapping(unsigned long virt, phys_addr_t phys,
+                     unsigned long size, pgprot_t prot);
+void __iomem *pmb_remap_caller(phys_addr_t phys, unsigned long size,
+                               pgprot_t prot, void *caller);
+int pmb_unmap(void __iomem *addr);
+
 #else
-static inline long pmb_remap(unsigned long virt, unsigned long phys,
-                             unsigned long size, pgprot_t prot)
+
+static inline void __iomem *
+pmb_remap_caller(phys_addr_t phys, unsigned long size,
+                 pgprot_t prot, void *caller)
+{
+        return NULL;
+}
+
+static inline int pmb_unmap(void __iomem *addr)
 {
         return -EINVAL;
 }
 
-#define pmb_unmap(addr)         do { } while (0)
 #define pmb_init(addr)          do { } while (0)
 
 #ifdef CONFIG_29BIT
@@ -77,6 +87,13 @@ static inline long pmb_remap(unsigned long virt, unsigned long phys,
 #endif
 
 #endif /* CONFIG_PMB */
+
+static inline void __iomem *
+pmb_remap(phys_addr_t phys, unsigned long size, pgprot_t prot)
+{
+        return pmb_remap_caller(phys, size, prot, __builtin_return_address(0));
+}
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __MMU_H */
diff --git a/arch/sh/include/asm/siu.h b/arch/sh/include/asm/siu.h
index 57565a3b551f..f1b1e6944a5f 100644
--- a/arch/sh/include/asm/siu.h
+++ b/arch/sh/include/asm/siu.h
@@ -11,7 +11,7 @@
 #ifndef ASM_SIU_H
 #define ASM_SIU_H
 
-#include <asm/dma-sh.h>
+#include <asm/dmaengine.h>
 
 struct device;
 
diff --git a/arch/sh/include/asm/topology.h b/arch/sh/include/asm/topology.h
index 37cdadd975ac..88e734069fa6 100644
--- a/arch/sh/include/asm/topology.h
+++ b/arch/sh/include/asm/topology.h
@@ -35,7 +35,7 @@
 
 #define pcibus_to_node(bus)     ((void)(bus), -1)
 #define cpumask_of_pcibus(bus)  (pcibus_to_node(bus) == -1 ? \
-                                        CPU_MASK_ALL_PTR : \
+                                        cpu_all_mask : \
                                         cpumask_of_node(pcibus_to_node(bus)))
 
 #endif
diff --git a/arch/sh/include/cpu-sh3/cpu/dma-register.h b/arch/sh/include/cpu-sh3/cpu/dma-register.h
new file mode 100644
index 000000000000..2349e488c9a6
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/dma-register.h
@@ -0,0 +1,41 @@
+/*
+ * SH3 CPU-specific DMA definitions, used by both DMA drivers
+ *
+ * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef CPU_DMA_REGISTER_H
+#define CPU_DMA_REGISTER_H
+
+#define CHCR_TS_LOW_MASK        0x18
+#define CHCR_TS_LOW_SHIFT       3
+#define CHCR_TS_HIGH_MASK       0
+#define CHCR_TS_HIGH_SHIFT      0
+
+#define DMAOR_INIT      DMAOR_DME
+
+/*
+ * The SuperH DMAC supports a number of transmit sizes, we list them here,
+ * with their respective values as they appear in the CHCR registers.
+ */
+enum {
+        XMIT_SZ_8BIT,
+        XMIT_SZ_16BIT,
+        XMIT_SZ_32BIT,
+        XMIT_SZ_128BIT,
+};
+
+/* log2(size / 8) - used to calculate number of transfers */
+#define TS_SHIFT {                      \
+        [XMIT_SZ_8BIT]          = 0,    \
+        [XMIT_SZ_16BIT]         = 1,    \
+        [XMIT_SZ_32BIT]         = 2,    \
+        [XMIT_SZ_128BIT]        = 4,    \
+}
+
+#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT)
+
+#endif
diff --git a/arch/sh/include/cpu-sh3/cpu/dma.h b/arch/sh/include/cpu-sh3/cpu/dma.h
index 207811a7a650..24e28b91c9d5 100644
--- a/arch/sh/include/cpu-sh3/cpu/dma.h
+++ b/arch/sh/include/cpu-sh3/cpu/dma.h
@@ -20,31 +20,4 @@
 #define TS_32           0x00000010
 #define TS_128          0x00000018
 
-#define CHCR_TS_LOW_MASK        0x18
-#define CHCR_TS_LOW_SHIFT       3
-#define CHCR_TS_HIGH_MASK       0
-#define CHCR_TS_HIGH_SHIFT      0
-
-#define DMAOR_INIT      DMAOR_DME
-
-/*
- * The SuperH DMAC supports a number of transmit sizes, we list them here,
- * with their respective values as they appear in the CHCR registers.
- */
-enum {
-        XMIT_SZ_8BIT,
-        XMIT_SZ_16BIT,
-        XMIT_SZ_32BIT,
-        XMIT_SZ_128BIT,
-};
-
-#define TS_SHIFT {                      \
-        [XMIT_SZ_8BIT]          = 0,    \
-        [XMIT_SZ_16BIT]         = 1,    \
-        [XMIT_SZ_32BIT]         = 2,    \
-        [XMIT_SZ_128BIT]        = 4,    \
-}
-
-#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT)
-
 #endif /* __ASM_CPU_SH3_DMA_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-register.h b/arch/sh/include/cpu-sh4/cpu/dma-register.h
new file mode 100644
index 000000000000..55f9fec082d4
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/dma-register.h
@@ -0,0 +1,112 @@
+/*
+ * SH4 CPU-specific DMA definitions, used by both DMA drivers
+ *
+ * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef CPU_DMA_REGISTER_H
+#define CPU_DMA_REGISTER_H
+
+/* SH7751/7760/7780 DMA IRQ sources */
+
+#ifdef CONFIG_CPU_SH4A
+
+#define DMAOR_INIT      DMAOR_DME
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
+        defined(CONFIG_CPU_SUBTYPE_SH7730)
+#define CHCR_TS_LOW_MASK        0x00000018
+#define CHCR_TS_LOW_SHIFT       3
+#define CHCR_TS_HIGH_MASK       0
+#define CHCR_TS_HIGH_SHIFT      0
+#elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \
+        defined(CONFIG_CPU_SUBTYPE_SH7724)
+#define CHCR_TS_LOW_MASK        0x00000018
+#define CHCR_TS_LOW_SHIFT       3
+#define CHCR_TS_HIGH_MASK       0x00300000
+#define CHCR_TS_HIGH_SHIFT      (20 - 2)        /* 2 bits for shifted low TS */
+#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
+        defined(CONFIG_CPU_SUBTYPE_SH7764)
+#define CHCR_TS_LOW_MASK        0x00000018
+#define CHCR_TS_LOW_SHIFT       3
+#define CHCR_TS_HIGH_MASK       0
+#define CHCR_TS_HIGH_SHIFT      0
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+#define CHCR_TS_LOW_MASK        0x00000018
+#define CHCR_TS_LOW_SHIFT       3
+#define CHCR_TS_HIGH_MASK       0
+#define CHCR_TS_HIGH_SHIFT      0
+#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
+#define CHCR_TS_LOW_MASK        0x00000018
+#define CHCR_TS_LOW_SHIFT       3
+#define CHCR_TS_HIGH_MASK       0
+#define CHCR_TS_HIGH_SHIFT      0
+#else /* SH7785 */
+#define CHCR_TS_LOW_MASK        0x00000018
+#define CHCR_TS_LOW_SHIFT       3
+#define CHCR_TS_HIGH_MASK       0
+#define CHCR_TS_HIGH_SHIFT      0
+#endif
+
+/* Transmit sizes and respective CHCR register values */
+enum {
+        XMIT_SZ_8BIT            = 0,
+        XMIT_SZ_16BIT           = 1,
+        XMIT_SZ_32BIT           = 2,
+        XMIT_SZ_64BIT           = 7,
+        XMIT_SZ_128BIT          = 3,
+        XMIT_SZ_256BIT          = 4,
+        XMIT_SZ_128BIT_BLK      = 0xb,
+        XMIT_SZ_256BIT_BLK      = 0xc,
+};
+
+/* log2(size / 8) - used to calculate number of transfers */
+#define TS_SHIFT {                      \
+        [XMIT_SZ_8BIT]          = 0,    \
+        [XMIT_SZ_16BIT]         = 1,    \
+        [XMIT_SZ_32BIT]         = 2,    \
+        [XMIT_SZ_64BIT]         = 3,    \
+        [XMIT_SZ_128BIT]        = 4,    \
+        [XMIT_SZ_256BIT]        = 5,    \
+        [XMIT_SZ_128BIT_BLK]    = 4,    \
+        [XMIT_SZ_256BIT_BLK]    = 5,    \
+}
+
+#define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
+                         ((((i) >> 2) & 3) << CHCR_TS_HIGH_SHIFT))
+
+#else /* CONFIG_CPU_SH4A */
+
+#define DMAOR_INIT      (0x8000 | DMAOR_DME)
+
+#define CHCR_TS_LOW_MASK        0x70
+#define CHCR_TS_LOW_SHIFT       4
+#define CHCR_TS_HIGH_MASK       0
+#define CHCR_TS_HIGH_SHIFT      0
+
+/* Transmit sizes and respective CHCR register values */
+enum {
+        XMIT_SZ_8BIT    = 1,
+        XMIT_SZ_16BIT   = 2,
+        XMIT_SZ_32BIT   = 3,
+        XMIT_SZ_64BIT   = 0,
+        XMIT_SZ_256BIT  = 4,
+};
+
+/* log2(size / 8) - used to calculate number of transfers */
+#define TS_SHIFT {                      \
+        [XMIT_SZ_8BIT]          = 0,    \
+        [XMIT_SZ_16BIT]         = 1,    \
+        [XMIT_SZ_32BIT]         = 2,    \
+        [XMIT_SZ_64BIT]         = 3,    \
+        [XMIT_SZ_256BIT]        = 5,    \
+}
+
+#define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT)
+
+#endif /* CONFIG_CPU_SH4A */
+
+#endif
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
index e734ea47d8a0..9647e681fd27 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
@@ -8,20 +8,12 @@
 #define DMAE0_IRQ       78      /* DMA Error IRQ*/
 #define SH_DMAC_BASE0   0xFE008020
 #define SH_DMARS_BASE0  0xFE009000
-#define CHCR_TS_LOW_MASK        0x00000018
-#define CHCR_TS_LOW_SHIFT       3
-#define CHCR_TS_HIGH_MASK       0
-#define CHCR_TS_HIGH_SHIFT      0
 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
 #define DMTE0_IRQ       48
 #define DMTE4_IRQ       76
 #define DMAE0_IRQ       78      /* DMA Error IRQ*/
 #define SH_DMAC_BASE0   0xFE008020
 #define SH_DMARS_BASE0  0xFE009000
-#define CHCR_TS_LOW_MASK        0x00000018
-#define CHCR_TS_LOW_SHIFT       3
-#define CHCR_TS_HIGH_MASK       0x00300000
-#define CHCR_TS_HIGH_SHIFT      20
 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
         defined(CONFIG_CPU_SUBTYPE_SH7764)
 #define DMTE0_IRQ       34
@@ -29,10 +21,6 @@
 #define DMAE0_IRQ       38
 #define SH_DMAC_BASE0   0xFF608020
 #define SH_DMARS_BASE0  0xFF609000
-#define CHCR_TS_LOW_MASK        0x00000018
-#define CHCR_TS_LOW_SHIFT       3
-#define CHCR_TS_HIGH_MASK       0
-#define CHCR_TS_HIGH_SHIFT      0
 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
 #define DMTE0_IRQ       48      /* DMAC0A*/
 #define DMTE4_IRQ       76      /* DMAC0B */
@@ -46,10 +34,6 @@
 #define SH_DMAC_BASE0   0xFE008020
 #define SH_DMAC_BASE1   0xFDC08020
 #define SH_DMARS_BASE0  0xFDC09000
-#define CHCR_TS_LOW_MASK        0x00000018
-#define CHCR_TS_LOW_SHIFT       3
-#define CHCR_TS_HIGH_MASK       0
-#define CHCR_TS_HIGH_SHIFT      0
 #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
 #define DMTE0_IRQ       48      /* DMAC0A*/
 #define DMTE4_IRQ       76      /* DMAC0B */
@@ -64,10 +48,6 @@
 #define SH_DMAC_BASE1   0xFDC08020
 #define SH_DMARS_BASE0  0xFE009000
 #define SH_DMARS_BASE1  0xFDC09000
-#define CHCR_TS_LOW_MASK        0x00000018
-#define CHCR_TS_LOW_SHIFT       3
-#define CHCR_TS_HIGH_MASK       0x00600000
-#define CHCR_TS_HIGH_SHIFT      21
 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 #define DMTE0_IRQ       34
 #define DMTE4_IRQ       44
@@ -80,10 +60,6 @@
 #define SH_DMAC_BASE0   0xFC808020
 #define SH_DMAC_BASE1   0xFC818020
 #define SH_DMARS_BASE0  0xFC809000
-#define CHCR_TS_LOW_MASK        0x00000018
-#define CHCR_TS_LOW_SHIFT       3
-#define CHCR_TS_HIGH_MASK       0
-#define CHCR_TS_HIGH_SHIFT      0
 #else /* SH7785 */
 #define DMTE0_IRQ       33
 #define DMTE4_IRQ       37
@@ -97,10 +73,6 @@
 #define SH_DMAC_BASE0   0xFC808020
 #define SH_DMAC_BASE1   0xFCC08020
 #define SH_DMARS_BASE0  0xFC809000
-#define CHCR_TS_LOW_MASK        0x00000018
-#define CHCR_TS_LOW_SHIFT       3
-#define CHCR_TS_HIGH_MASK       0
-#define CHCR_TS_HIGH_SHIFT      0
 #endif
 
 #define REQ_HE          0x000000C0
@@ -108,38 +80,4 @@
 #define REQ_LE          0x00000040
 #define TM_BURST        0x00000020
 
-/*
- * The SuperH DMAC supports a number of transmit sizes, we list them here,
- * with their respective values as they appear in the CHCR registers.
- *
- * Defaults to a 64-bit transfer size.
- */
-enum {
-        XMIT_SZ_8BIT            = 0,
-        XMIT_SZ_16BIT           = 1,
-        XMIT_SZ_32BIT           = 2,
-        XMIT_SZ_64BIT           = 7,
-        XMIT_SZ_128BIT          = 3,
-        XMIT_SZ_256BIT          = 4,
-        XMIT_SZ_128BIT_BLK      = 0xb,
-        XMIT_SZ_256BIT_BLK      = 0xc,
-};
-
-/*
- * The DMA count is defined as the number of bytes to transfer.
- */
-#define TS_SHIFT {                      \
-        [XMIT_SZ_8BIT]          = 0,    \
-        [XMIT_SZ_16BIT]         = 1,    \
-        [XMIT_SZ_32BIT]         = 2,    \
-        [XMIT_SZ_64BIT]         = 3,    \
-        [XMIT_SZ_128BIT]        = 4,    \
-        [XMIT_SZ_256BIT]        = 5,    \
-        [XMIT_SZ_128BIT_BLK]    = 4,    \
-        [XMIT_SZ_256BIT_BLK]    = 5,    \
-}
-
-#define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
-                         ((((i) >> 2) & 3) << CHCR_TS_HIGH_SHIFT))
-
 #endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma.h b/arch/sh/include/cpu-sh4/cpu/dma.h
index 114a369705bc..ca747e93c2ed 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma.h
@@ -5,9 +5,8 @@
 
 #ifdef CONFIG_CPU_SH4A
 
-#define DMAOR_INIT      (DMAOR_DME)
-
 #include <cpu/dma-sh4a.h>
+
 #else /* CONFIG_CPU_SH4A */
 /*
  * SH7750/SH7751/SH7760
@@ -17,7 +16,6 @@
 #define DMTE6_IRQ       46
 #define DMAE0_IRQ       38
 
-#define DMAOR_INIT      (0x8000|DMAOR_DME)
 #define SH_DMAC_BASE0   0xffa00000
 #define SH_DMAC_BASE1   0xffa00070
 /* Definitions for the SuperH DMAC */
@@ -27,40 +25,8 @@
 #define TS_32           0x00000030
 #define TS_64           0x00000000
 
-#define CHCR_TS_LOW_MASK        0x70
-#define CHCR_TS_LOW_SHIFT       4
-#define CHCR_TS_HIGH_MASK       0
-#define CHCR_TS_HIGH_SHIFT      0
-
 #define DMAOR_COD       0x00000008
 
-/*
- * The SuperH DMAC supports a number of transmit sizes, we list them here,
- * with their respective values as they appear in the CHCR registers.
- *
- * Defaults to a 64-bit transfer size.
- */
-enum {
-        XMIT_SZ_8BIT    = 1,
-        XMIT_SZ_16BIT   = 2,
-        XMIT_SZ_32BIT   = 3,
-        XMIT_SZ_64BIT   = 0,
-        XMIT_SZ_256BIT  = 4,
-};
-
-/*
- * The DMA count is defined as the number of bytes to transfer.
- */
-#define TS_SHIFT {                      \
-        [XMIT_SZ_8BIT]          = 0,    \
-        [XMIT_SZ_16BIT]         = 1,    \
-        [XMIT_SZ_32BIT]         = 2,    \
-        [XMIT_SZ_64BIT]         = 3,    \
-        [XMIT_SZ_256BIT]        = 5,    \
-}
-
-#define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT)
-
 #endif
 
 #endif /* __ASM_CPU_SH4_DMA_H */
diff --git a/arch/sh/include/mach-migor/mach/migor.h b/arch/sh/include/mach-migor/mach/migor.h
index cee6cb88e020..42fccf93412e 100644
--- a/arch/sh/include/mach-migor/mach/migor.h
+++ b/arch/sh/include/mach-migor/mach/migor.h
@@ -1,6 +1,7 @@
 #ifndef __ASM_SH_MIGOR_H
 #define __ASM_SH_MIGOR_H
 
+#define PORT_MSELCRA 0xa4050180
 #define PORT_MSELCRB 0xa4050182
 #define BSC_CS4BCR 0xfec10010
 #define BSC_CS6ABCR 0xfec1001c