sh: default to extended TLB support.

All SH-X2 and SH-X3 parts support an extended TLB mode, which has been
left as experimental since support was originally merged. Now that it's
had some time to stabilize and get some exposure to various platforms,
we can drop it as an option and default enable it across the board.

This is also good future proofing for newer parts that will drop support
for the legacy TLB mode completely.

This will also force 3-level page tables for all newer parts, which is
necessary both for the varying page sizes and larger memories.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

4 files changed, 11 insertions, 9 deletions

diff --git a/arch/sh/include/asm/pgalloc.h b/arch/sh/include/asm/pgalloc.h
index f8982f4e0405..8c00785c60d5 100644
--- a/arch/sh/include/asm/pgalloc.h
+++ b/arch/sh/include/asm/pgalloc.h
@@ -9,7 +9,7 @@
 extern pgd_t *pgd_alloc(struct mm_struct *);
 extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
 
-#ifdef CONFIG_PGTABLE_LEVELS_3
+#if PAGETABLE_LEVELS > 2
 extern void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd);
 extern pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address);
 extern void pmd_free(struct mm_struct *mm, pmd_t *pmd);
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index 78598ec33d0a..856ece07d31b 100644
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -12,7 +12,7 @@
 #ifndef __ASM_SH_PGTABLE_H
 #define __ASM_SH_PGTABLE_H
 
-#ifdef CONFIG_PGTABLE_LEVELS_3
+#ifdef CONFIG_X2TLB
 #include <asm/pgtable_pmd.h>
 #else
 #include <asm/pgtable_nopmd.h>
diff --git a/arch/sh/include/asm/pgtable_nopmd.h b/arch/sh/include/asm/pgtable_nopmd.h
index f0b525b3cb4a..b8355e4057cf 100644
--- a/arch/sh/include/asm/pgtable_nopmd.h
+++ b/arch/sh/include/asm/pgtable_nopmd.h
@@ -6,17 +6,18 @@
 /*
  * traditional two-level paging structure
  */
+#define PAGETABLE_LEVELS        2
 
 /* PTE bits */
-#define PTE_MAGNITUDE   2       /* 32-bit PTEs */
+#define PTE_MAGNITUDE           2       /* 32-bit PTEs */
 
-#define PTE_SHIFT       PAGE_SHIFT
-#define PTE_BITS        (PTE_SHIFT - PTE_MAGNITUDE)
+#define PTE_SHIFT               PAGE_SHIFT
+#define PTE_BITS                (PTE_SHIFT - PTE_MAGNITUDE)
 
 /* PGD bits */
-#define PGDIR_SHIFT     (PTE_SHIFT + PTE_BITS)
+#define PGDIR_SHIFT             (PTE_SHIFT + PTE_BITS)
 
-#define PTRS_PER_PGD    (PAGE_SIZE / (1 << PTE_MAGNITUDE))
+#define PTRS_PER_PGD            (PAGE_SIZE / (1 << PTE_MAGNITUDE))
 #define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
 
 #endif /* __ASM_SH_PGTABLE_NOPMD_H */
diff --git a/arch/sh/include/asm/pgtable_pmd.h b/arch/sh/include/asm/pgtable_pmd.h
index 42a180e534a8..587b05e1d04f 100644
--- a/arch/sh/include/asm/pgtable_pmd.h
+++ b/arch/sh/include/asm/pgtable_pmd.h
@@ -7,11 +7,12 @@
  * Some cores need a 3-level page table layout, for example when using
  * 64-bit PTEs and 4K pages.
  */
+#define PAGETABLE_LEVELS        3
 
-#define PTE_MAGNITUDE   3       /* 64-bit PTEs on extended mode SH-X2 TLB */
+#define PTE_MAGNITUDE           3       /* 64-bit PTEs on SH-X2 TLB */
 
 /* PGD bits */
-#define PGDIR_SHIFT     30
+#define PGDIR_SHIFT             30
 
 #define PTRS_PER_PGD            4
 #define USER_PTRS_PER_PGD       2