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authorPaul Mundt <lethal@linux-sh.org>2009-05-22 00:29:37 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-05-22 00:29:37 -0400
commit5f8371cec93b94a24a55ba1de642ce6eade6d62c (patch)
tree61b6d2acb10226b3c0f2d31bda3a49288e540eba /arch/sh/include
parent8e9bb19ef97d6594e735bee64b6d72103e350854 (diff)
parentd8586ba6e1415150e1bab89f0a05447bb6f2d6d5 (diff)
Merge branches 'sh/stable-updates' and 'sh/sparseirq'
Diffstat (limited to 'arch/sh/include')
-rw-r--r--arch/sh/include/asm/cacheflush.h2
-rw-r--r--arch/sh/include/asm/clock.h4
-rw-r--r--arch/sh/include/asm/device.h2
-rw-r--r--arch/sh/include/asm/hd64461.h148
-rw-r--r--arch/sh/include/asm/io.h22
-rw-r--r--arch/sh/include/asm/kprobes.h2
-rw-r--r--arch/sh/include/asm/pci.h98
-rw-r--r--arch/sh/include/asm/pgtable.h4
-rw-r--r--arch/sh/include/asm/processor.h2
-rw-r--r--arch/sh/include/asm/ptrace.h5
-rw-r--r--arch/sh/include/asm/rtc.h11
-rw-r--r--arch/sh/include/asm/swab.h12
-rw-r--r--arch/sh/include/asm/system_32.h2
-rw-r--r--arch/sh/include/asm/timer.h44
-rw-r--r--arch/sh/include/asm/types.h4
-rw-r--r--arch/sh/include/asm/ubc.h11
-rw-r--r--arch/sh/include/cpu-sh2a/cpu/ubc.h29
-rw-r--r--arch/sh/include/cpu-sh3/cpu/timer.h67
-rw-r--r--arch/sh/include/cpu-sh4/cpu/freq.h18
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7724.h255
-rw-r--r--arch/sh/include/cpu-sh4/cpu/timer.h60
-rw-r--r--arch/sh/include/cpu-sh5/cpu/irq.h1
-rw-r--r--arch/sh/include/mach-common/mach/sh7785lcr.h10
-rw-r--r--arch/sh/include/mach-dreamcast/mach/pci.h2
24 files changed, 490 insertions, 325 deletions
diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h
index 09acbc32d6c7..4c5462daa74c 100644
--- a/arch/sh/include/asm/cacheflush.h
+++ b/arch/sh/include/asm/cacheflush.h
@@ -75,7 +75,5 @@ extern void copy_from_user_page(struct vm_area_struct *vma,
75#define flush_cache_vmap(start, end) flush_cache_all() 75#define flush_cache_vmap(start, end) flush_cache_all()
76#define flush_cache_vunmap(start, end) flush_cache_all() 76#define flush_cache_vunmap(start, end) flush_cache_all()
77 77
78#define HAVE_ARCH_UNMAPPED_AREA
79
80#endif /* __KERNEL__ */ 78#endif /* __KERNEL__ */
81#endif /* __ASM_SH_CACHEFLUSH_H */ 79#endif /* __ASM_SH_CACHEFLUSH_H */
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index 2f6c9627bc1f..b1f29199e4bd 100644
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -1,7 +1,6 @@
1#ifndef __ASM_SH_CLOCK_H 1#ifndef __ASM_SH_CLOCK_H
2#define __ASM_SH_CLOCK_H 2#define __ASM_SH_CLOCK_H
3 3
4#include <linux/kref.h>
5#include <linux/list.h> 4#include <linux/list.h>
6#include <linux/seq_file.h> 5#include <linux/seq_file.h>
7#include <linux/clk.h> 6#include <linux/clk.h>
@@ -28,7 +27,7 @@ struct clk {
28 struct clk *parent; 27 struct clk *parent;
29 struct clk_ops *ops; 28 struct clk_ops *ops;
30 29
31 struct kref kref; 30 int usecount;
32 31
33 unsigned long rate; 32 unsigned long rate;
34 unsigned long flags; 33 unsigned long flags;
@@ -37,6 +36,7 @@ struct clk {
37 36
38#define CLK_ALWAYS_ENABLED (1 << 0) 37#define CLK_ALWAYS_ENABLED (1 << 0)
39#define CLK_RATE_PROPAGATES (1 << 1) 38#define CLK_RATE_PROPAGATES (1 << 1)
39#define CLK_NEEDS_INIT (1 << 2)
40 40
41/* Should be defined by processor-specific code */ 41/* Should be defined by processor-specific code */
42void arch_init_clk_ops(struct clk_ops **, int type); 42void arch_init_clk_ops(struct clk_ops **, int type);
diff --git a/arch/sh/include/asm/device.h b/arch/sh/include/asm/device.h
index efd511d0803a..8688a88303ee 100644
--- a/arch/sh/include/asm/device.h
+++ b/arch/sh/include/asm/device.h
@@ -10,3 +10,5 @@ struct platform_device;
10int platform_resource_setup_memory(struct platform_device *pdev, 10int platform_resource_setup_memory(struct platform_device *pdev,
11 char *name, unsigned long memsize); 11 char *name, unsigned long memsize);
12 12
13void plat_early_device_setup(void);
14
diff --git a/arch/sh/include/asm/hd64461.h b/arch/sh/include/asm/hd64461.h
index 52b4b6238277..977355f0a483 100644
--- a/arch/sh/include/asm/hd64461.h
+++ b/arch/sh/include/asm/hd64461.h
@@ -13,18 +13,20 @@
13#define HD64461_PCC_WINDOW 0x01000000 13#define HD64461_PCC_WINDOW 0x01000000
14 14
15/* Area 6 - Slot 0 - memory and/or IO card */ 15/* Area 6 - Slot 0 - memory and/or IO card */
16#define HD64461_PCC0_BASE (CONFIG_HD64461_IOBASE + 0x8000000) 16#define HD64461_IOBASE 0xb0000000
17#define HD64461_IO_OFFSET(x) (HD64461_IOBASE + (x))
18#define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000)
17#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */ 19#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
18#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */ 20#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
19#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */ 21#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */
20 22
21/* Area 5 - Slot 1 - memory card only */ 23/* Area 5 - Slot 1 - memory card only */
22#define HD64461_PCC1_BASE (CONFIG_HD64461_IOBASE + 0x4000000) 24#define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000)
23#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */ 25#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
24#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */ 26#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */
25 27
26/* Standby Control Register for HD64461 */ 28/* Standby Control Register for HD64461 */
27#define HD64461_STBCR CONFIG_HD64461_IOBASE 29#define HD64461_STBCR HD64461_IO_OFFSET(0x00000000)
28#define HD64461_STBCR_CKIO_STBY 0x2000 30#define HD64461_STBCR_CKIO_STBY 0x2000
29#define HD64461_STBCR_SAFECKE_IST 0x1000 31#define HD64461_STBCR_SAFECKE_IST 0x1000
30#define HD64461_STBCR_SLCKE_IST 0x0800 32#define HD64461_STBCR_SLCKE_IST 0x0800
@@ -41,19 +43,19 @@
41#define HD64461_STBCR_SURTST 0x0001 43#define HD64461_STBCR_SURTST 0x0001
42 44
43/* System Configuration Register */ 45/* System Configuration Register */
44#define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x02) 46#define HD64461_SYSCR HD64461_IO_OFFSET(0x02)
45 47
46/* CPU Data Bus Control Register */ 48/* CPU Data Bus Control Register */
47#define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04) 49#define HD64461_SCPUCR HD64461_IO_OFFSET(0x04)
48 50
49/* Base Address Register */ 51/* Base Address Register */
50#define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000) 52#define HD64461_LCDCBAR HD64461_IO_OFFSET(0x1000)
51 53
52/* Line increment address */ 54/* Line increment address */
53#define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002) 55#define HD64461_LCDCLOR HD64461_IO_OFFSET(0x1002)
54 56
55/* Controls LCD controller */ 57/* Controls LCD controller */
56#define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x1004) 58#define HD64461_LCDCCR HD64461_IO_OFFSET(0x1004)
57 59
58/* LCCDR control bits */ 60/* LCCDR control bits */
59#define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */ 61#define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */
@@ -64,30 +66,30 @@
64#define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */ 66#define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */
65 67
66/* Controls LCD (1) */ 68/* Controls LCD (1) */
67#define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x1010) 69#define HD64461_LDR1 HD64461_IO_OFFSET(0x1010)
68#define HD64461_LDR1_DON 0x01 /* Display On */ 70#define HD64461_LDR1_DON 0x01 /* Display On */
69#define HD64461_LDR1_DINV 0x80 /* Display Invert */ 71#define HD64461_LDR1_DINV 0x80 /* Display Invert */
70 72
71/* Controls LCD (2) */ 73/* Controls LCD (2) */
72#define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x1012) 74#define HD64461_LDR2 HD64461_IO_OFFSET(0x1012)
73#define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x1014) /* Number of horizontal characters */ 75#define HD64461_LDHNCR HD64461_IO_OFFSET(0x1014) /* Number of horizontal characters */
74#define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x1016) /* Specify output start position + width of CL1 */ 76#define HD64461_LDHNSR HD64461_IO_OFFSET(0x1016) /* Specify output start position + width of CL1 */
75#define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x1018) /* Specify total vertical lines */ 77#define HD64461_LDVNTR HD64461_IO_OFFSET(0x1018) /* Specify total vertical lines */
76#define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x101a) /* specify number of display vertical lines */ 78#define HD64461_LDVNDR HD64461_IO_OFFSET(0x101a) /* specify number of display vertical lines */
77#define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x101c) /* specify vertical synchronization pos and AC nr */ 79#define HD64461_LDVSPR HD64461_IO_OFFSET(0x101c) /* specify vertical synchronization pos and AC nr */
78 80
79/* Controls LCD (3) */ 81/* Controls LCD (3) */
80#define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e) 82#define HD64461_LDR3 HD64461_IO_OFFSET(0x101e)
81 83
82/* Palette Registers */ 84/* Palette Registers */
83#define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Address Register */ 85#define HD64461_CPTWAR HD64461_IO_OFFSET(0x1030) /* Color Palette Write Address Register */
84#define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */ 86#define HD64461_CPTWDR HD64461_IO_OFFSET(0x1032) /* Color Palette Write Data Register */
85#define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Address Register */ 87#define HD64461_CPTRAR HD64461_IO_OFFSET(0x1034) /* Color Palette Read Address Register */
86#define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */ 88#define HD64461_CPTRDR HD64461_IO_OFFSET(0x1036) /* Color Palette Read Data Register */
87 89
88#define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */ 90#define HD64461_GRDOR HD64461_IO_OFFSET(0x1040) /* Display Resolution Offset Register */
89#define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x1042) /* Solid Color Register */ 91#define HD64461_GRSCR HD64461_IO_OFFSET(0x1042) /* Solid Color Register */
90#define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x1044) /* Accelerator Configuration Register */ 92#define HD64461_GRCFGR HD64461_IO_OFFSET(0x1044) /* Accelerator Configuration Register */
91 93
92#define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */ 94#define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */
93#define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */ 95#define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */
@@ -97,41 +99,41 @@
97#define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */ 99#define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */
98 100
99/* Line Drawing Registers */ 101/* Line Drawing Registers */
100#define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Address Register (H) */ 102#define HD64461_LNSARH HD64461_IO_OFFSET(0x1046) /* Line Start Address Register (H) */
101#define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Address Register (L) */ 103#define HD64461_LNSARL HD64461_IO_OFFSET(0x1048) /* Line Start Address Register (L) */
102#define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */ 104#define HD64461_LNAXLR HD64461_IO_OFFSET(0x104a) /* Axis Pixel Length Register */
103#define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */ 105#define HD64461_LNDGR HD64461_IO_OFFSET(0x104c) /* Diagonal Register */
104#define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */ 106#define HD64461_LNAXR HD64461_IO_OFFSET(0x104e) /* Axial Register */
105#define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x1050) /* Start Error Term Register */ 107#define HD64461_LNERTR HD64461_IO_OFFSET(0x1050) /* Start Error Term Register */
106#define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */ 108#define HD64461_LNMDR HD64461_IO_OFFSET(0x1052) /* Line Mode Register */
107 109
108/* BitBLT Registers */ 110/* BitBLT Registers */
109#define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Address Register (H) */ 111#define HD64461_BBTSSARH HD64461_IO_OFFSET(0x1054) /* Source Start Address Register (H) */
110#define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Address Register (L) */ 112#define HD64461_BBTSSARL HD64461_IO_OFFSET(0x1056) /* Source Start Address Register (L) */
111#define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Address Register (H) */ 113#define HD64461_BBTDSARH HD64461_IO_OFFSET(0x1058) /* Destination Start Address Register (H) */
112#define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Address Register (L) */ 114#define HD64461_BBTDSARL HD64461_IO_OFFSET(0x105a) /* Destination Start Address Register (L) */
113#define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */ 115#define HD64461_BBTDWR HD64461_IO_OFFSET(0x105c) /* Destination Block Width Register */
114#define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */ 116#define HD64461_BBTDHR HD64461_IO_OFFSET(0x105e) /* Destination Block Height Register */
115#define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Address Register (H) */ 117#define HD64461_BBTPARH HD64461_IO_OFFSET(0x1060) /* Pattern Start Address Register (H) */
116#define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Address Register (L) */ 118#define HD64461_BBTPARL HD64461_IO_OFFSET(0x1062) /* Pattern Start Address Register (L) */
117#define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Address Register (H) */ 119#define HD64461_BBTMARH HD64461_IO_OFFSET(0x1064) /* Mask Start Address Register (H) */
118#define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Address Register (L) */ 120#define HD64461_BBTMARL HD64461_IO_OFFSET(0x1066) /* Mask Start Address Register (L) */
119#define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */ 121#define HD64461_BBTROPR HD64461_IO_OFFSET(0x1068) /* ROP Register */
120#define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */ 122#define HD64461_BBTMDR HD64461_IO_OFFSET(0x106a) /* BitBLT Mode Register */
121 123
122/* PC Card Controller Registers */ 124/* PC Card Controller Registers */
123/* Maps to Physical Area 6 */ 125/* Maps to Physical Area 6 */
124#define HD64461_PCC0ISR (CONFIG_HD64461_IOBASE + 0x2000) /* socket 0 interface status */ 126#define HD64461_PCC0ISR HD64461_IO_OFFSET(0x2000) /* socket 0 interface status */
125#define HD64461_PCC0GCR (CONFIG_HD64461_IOBASE + 0x2002) /* socket 0 general control */ 127#define HD64461_PCC0GCR HD64461_IO_OFFSET(0x2002) /* socket 0 general control */
126#define HD64461_PCC0CSCR (CONFIG_HD64461_IOBASE + 0x2004) /* socket 0 card status change */ 128#define HD64461_PCC0CSCR HD64461_IO_OFFSET(0x2004) /* socket 0 card status change */
127#define HD64461_PCC0CSCIER (CONFIG_HD64461_IOBASE + 0x2006) /* socket 0 card status change interrupt enable */ 129#define HD64461_PCC0CSCIER HD64461_IO_OFFSET(0x2006) /* socket 0 card status change interrupt enable */
128#define HD64461_PCC0SCR (CONFIG_HD64461_IOBASE + 0x2008) /* socket 0 software control */ 130#define HD64461_PCC0SCR HD64461_IO_OFFSET(0x2008) /* socket 0 software control */
129/* Maps to Physical Area 5 */ 131/* Maps to Physical Area 5 */
130#define HD64461_PCC1ISR (CONFIG_HD64461_IOBASE + 0x2010) /* socket 1 interface status */ 132#define HD64461_PCC1ISR HD64461_IO_OFFSET(0x2010) /* socket 1 interface status */
131#define HD64461_PCC1GCR (CONFIG_HD64461_IOBASE + 0x2012) /* socket 1 general control */ 133#define HD64461_PCC1GCR HD64461_IO_OFFSET(0x2012) /* socket 1 general control */
132#define HD64461_PCC1CSCR (CONFIG_HD64461_IOBASE + 0x2014) /* socket 1 card status change */ 134#define HD64461_PCC1CSCR HD64461_IO_OFFSET(0x2014) /* socket 1 card status change */
133#define HD64461_PCC1CSCIER (CONFIG_HD64461_IOBASE + 0x2016) /* socket 1 card status change interrupt enable */ 135#define HD64461_PCC1CSCIER HD64461_IO_OFFSET(0x2016) /* socket 1 card status change interrupt enable */
134#define HD64461_PCC1SCR (CONFIG_HD64461_IOBASE + 0x2018) /* socket 1 software control */ 136#define HD64461_PCC1SCR HD64461_IO_OFFSET(0x2018) /* socket 1 software control */
135 137
136/* PCC Interface Status Register */ 138/* PCC Interface Status Register */
137#define HD64461_PCCISR_READY 0x80 /* card ready */ 139#define HD64461_PCCISR_READY 0x80 /* card ready */
@@ -189,41 +191,41 @@
189#define HD64461_PCCSCR_SWP 0x01 /* write protect */ 191#define HD64461_PCCSCR_SWP 0x01 /* write protect */
190 192
191/* PCC0 Output Pins Control Register */ 193/* PCC0 Output Pins Control Register */
192#define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x202a) 194#define HD64461_P0OCR HD64461_IO_OFFSET(0x202a)
193 195
194/* PCC1 Output Pins Control Register */ 196/* PCC1 Output Pins Control Register */
195#define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x202c) 197#define HD64461_P1OCR HD64461_IO_OFFSET(0x202c)
196 198
197/* PC Card General Control Register */ 199/* PC Card General Control Register */
198#define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x202e) 200#define HD64461_PGCR HD64461_IO_OFFSET(0x202e)
199 201
200/* Port Control Registers */ 202/* Port Control Registers */
201#define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x4000) /* Port A - Handles IRDA/TIMER */ 203#define HD64461_GPACR HD64461_IO_OFFSET(0x4000) /* Port A - Handles IRDA/TIMER */
202#define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x4002) /* Port B - Handles UART */ 204#define HD64461_GPBCR HD64461_IO_OFFSET(0x4002) /* Port B - Handles UART */
203#define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x4004) /* Port C - Handles PCMCIA 1 */ 205#define HD64461_GPCCR HD64461_IO_OFFSET(0x4004) /* Port C - Handles PCMCIA 1 */
204#define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x4006) /* Port D - Handles PCMCIA 1 */ 206#define HD64461_GPDCR HD64461_IO_OFFSET(0x4006) /* Port D - Handles PCMCIA 1 */
205 207
206/* Port Control Data Registers */ 208/* Port Control Data Registers */
207#define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x4010) /* A */ 209#define HD64461_GPADR HD64461_IO_OFFSET(0x4010) /* A */
208#define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x4012) /* B */ 210#define HD64461_GPBDR HD64461_IO_OFFSET(0x4012) /* B */
209#define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x4014) /* C */ 211#define HD64461_GPCDR HD64461_IO_OFFSET(0x4014) /* C */
210#define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x4016) /* D */ 212#define HD64461_GPDDR HD64461_IO_OFFSET(0x4016) /* D */
211 213
212/* Interrupt Control Registers */ 214/* Interrupt Control Registers */
213#define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x4020) /* A */ 215#define HD64461_GPAICR HD64461_IO_OFFSET(0x4020) /* A */
214#define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x4022) /* B */ 216#define HD64461_GPBICR HD64461_IO_OFFSET(0x4022) /* B */
215#define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x4024) /* C */ 217#define HD64461_GPCICR HD64461_IO_OFFSET(0x4024) /* C */
216#define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x4026) /* D */ 218#define HD64461_GPDICR HD64461_IO_OFFSET(0x4026) /* D */
217 219
218/* Interrupt Status Registers */ 220/* Interrupt Status Registers */
219#define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x4040) /* A */ 221#define HD64461_GPAISR HD64461_IO_OFFSET(0x4040) /* A */
220#define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x4042) /* B */ 222#define HD64461_GPBISR HD64461_IO_OFFSET(0x4042) /* B */
221#define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x4044) /* C */ 223#define HD64461_GPCISR HD64461_IO_OFFSET(0x4044) /* C */
222#define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x4046) /* D */ 224#define HD64461_GPDISR HD64461_IO_OFFSET(0x4046) /* D */
223 225
224/* Interrupt Request Register & Interrupt Mask Register */ 226/* Interrupt Request Register & Interrupt Mask Register */
225#define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x5000) 227#define HD64461_NIRR HD64461_IO_OFFSET(0x5000)
226#define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002) 228#define HD64461_NIMR HD64461_IO_OFFSET(0x5002)
227 229
228#define HD64461_IRQBASE OFFCHIP_IRQ_BASE 230#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
229#define OFFCHIP_IRQ_BASE 64 231#define OFFCHIP_IRQ_BASE 64
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 0454f8d68059..25348141674b 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -123,10 +123,15 @@ static inline void __raw_reads##bwlq(volatile void __iomem *mem, \
123 123
124__BUILD_MEMORY_STRING(b, u8) 124__BUILD_MEMORY_STRING(b, u8)
125__BUILD_MEMORY_STRING(w, u16) 125__BUILD_MEMORY_STRING(w, u16)
126__BUILD_MEMORY_STRING(q, u64)
127 126
127#ifdef CONFIG_SUPERH32
128void __raw_writesl(void __iomem *addr, const void *data, int longlen); 128void __raw_writesl(void __iomem *addr, const void *data, int longlen);
129void __raw_readsl(const void __iomem *addr, void *data, int longlen); 129void __raw_readsl(const void __iomem *addr, void *data, int longlen);
130#else
131__BUILD_MEMORY_STRING(l, u32)
132#endif
133
134__BUILD_MEMORY_STRING(q, u64)
130 135
131#define writesb __raw_writesb 136#define writesb __raw_writesb
132#define writesw __raw_writesw 137#define writesw __raw_writesw
@@ -224,17 +229,6 @@ void __iomem *__ioremap(unsigned long offset, unsigned long size,
224 unsigned long flags); 229 unsigned long flags);
225void __iounmap(void __iomem *addr); 230void __iounmap(void __iomem *addr);
226 231
227/* arch/sh/mm/ioremap_64.c */
228unsigned long onchip_remap(unsigned long addr, unsigned long size,
229 const char *name);
230extern void onchip_unmap(unsigned long vaddr);
231#else
232#define __ioremap(offset, size, flags) ((void __iomem *)(offset))
233#define __iounmap(addr) do { } while (0)
234#define onchip_remap(addr, size, name) (addr)
235#define onchip_unmap(addr) do { } while (0)
236#endif /* CONFIG_MMU */
237
238static inline void __iomem * 232static inline void __iomem *
239__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags) 233__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
240{ 234{
@@ -268,6 +262,10 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
268 262
269 return __ioremap(offset, size, flags); 263 return __ioremap(offset, size, flags);
270} 264}
265#else
266#define __ioremap_mode(offset, size, flags) ((void __iomem *)(offset))
267#define __iounmap(addr) do { } while (0)
268#endif /* CONFIG_MMU */
271 269
272#define ioremap(offset, size) \ 270#define ioremap(offset, size) \
273 __ioremap_mode((offset), (size), 0) 271 __ioremap_mode((offset), (size), 0)
diff --git a/arch/sh/include/asm/kprobes.h b/arch/sh/include/asm/kprobes.h
index 613644a758e8..036c3311233c 100644
--- a/arch/sh/include/asm/kprobes.h
+++ b/arch/sh/include/asm/kprobes.h
@@ -6,7 +6,7 @@
6#include <linux/types.h> 6#include <linux/types.h>
7#include <linux/ptrace.h> 7#include <linux/ptrace.h>
8 8
9typedef u16 kprobe_opcode_t; 9typedef insn_size_t kprobe_opcode_t;
10#define BREAKPOINT_INSTRUCTION 0xc33a 10#define BREAKPOINT_INSTRUCTION 0xc33a
11 11
12#define MAX_INSN_SIZE 16 12#define MAX_INSN_SIZE 16
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index df1d383e18a5..5b2e0fcdfc22 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -17,54 +17,29 @@
17 * external) PCI controllers. 17 * external) PCI controllers.
18 */ 18 */
19struct pci_channel { 19struct pci_channel {
20 struct pci_ops *pci_ops; 20 struct pci_channel *next;
21 struct resource *io_resource;
22 struct resource *mem_resource;
23 int first_devfn;
24 int last_devfn;
25};
26 21
27/* 22 struct pci_ops *pci_ops;
28 * Each board initializes this array and terminates it with a NULL entry. 23 struct resource *io_resource;
29 */ 24 struct resource *mem_resource;
30extern struct pci_channel board_pci_channels[];
31 25
32#define PCIBIOS_MIN_IO board_pci_channels->io_resource->start 26 unsigned long io_offset;
33#define PCIBIOS_MIN_MEM board_pci_channels->mem_resource->start 27 unsigned long mem_offset;
34 28
35/* 29 unsigned long reg_base;
36 * I/O routine helpers
37 */
38#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
39#define PCI_IO_AREA 0xFE400000
40#define PCI_IO_SIZE 0x00400000
41#elif defined(CONFIG_CPU_SH5)
42extern unsigned long PCI_IO_AREA;
43#define PCI_IO_SIZE 0x00010000
44#else
45#define PCI_IO_AREA 0xFE240000
46#define PCI_IO_SIZE 0x00040000
47#endif
48 30
49#define PCI_MEM_SIZE 0x01000000 31 unsigned long io_map_base;
32};
50 33
51#define SH4_PCIIOBR_MASK 0xFFFC0000 34extern void register_pci_controller(struct pci_channel *hose);
52#define pci_ioaddr(addr) (PCI_IO_AREA + (addr & ~SH4_PCIIOBR_MASK))
53 35
54#if defined(CONFIG_PCI) 36extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
55#define is_pci_ioaddr(port) \
56 (((port) >= PCIBIOS_MIN_IO) && \
57 ((port) < (PCIBIOS_MIN_IO + PCI_IO_SIZE)))
58#define is_pci_memaddr(port) \
59 (((port) >= PCIBIOS_MIN_MEM) && \
60 ((port) < (PCIBIOS_MIN_MEM + PCI_MEM_SIZE)))
61#else
62#define is_pci_ioaddr(port) (0)
63#define is_pci_memaddr(port) (0)
64#endif
65 37
66struct pci_dev; 38struct pci_dev;
67 39
40#define HAVE_PCI_MMAP
41extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
42 enum pci_mmap_state mmap_state, int write_combine);
68extern void pcibios_set_master(struct pci_dev *dev); 43extern void pcibios_set_master(struct pci_dev *dev);
69 44
70static inline void pcibios_penalize_isa_irq(int irq, int active) 45static inline void pcibios_penalize_isa_irq(int irq, int active)
@@ -123,22 +98,51 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
123} 98}
124#endif 99#endif
125 100
101#ifdef CONFIG_SUPERH32
102/*
103 * If we're on an SH7751 or SH7780 PCI controller, PCI memory is mapped
104 * at the end of the address space in a special non-translatable area.
105 */
106#define PCI_MEM_FIXED_START 0xfd000000
107#define PCI_MEM_FIXED_END (PCI_MEM_FIXED_START + 0x01000000)
108
109#define is_pci_memory_fixed_range(s, e) \
110 ((s) >= PCI_MEM_FIXED_START && (e) < PCI_MEM_FIXED_END)
111#else
112#define is_pci_memory_fixed_range(s, e) (0)
113#endif
114
126/* Board-specific fixup routines. */ 115/* Board-specific fixup routines. */
127void pcibios_fixup(void);
128int pcibios_init_platform(void);
129int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin); 116int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
130 117
131#ifdef CONFIG_PCI_AUTO 118extern void pcibios_resource_to_bus(struct pci_dev *dev,
132int pciauto_assign_resources(int busno, struct pci_channel *hose); 119 struct pci_bus_region *region, struct resource *res);
133#endif
134 120
135#endif /* __KERNEL__ */ 121extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
122 struct pci_bus_region *region);
123
124static inline struct resource *
125pcibios_select_root(struct pci_dev *pdev, struct resource *res)
126{
127 struct resource *root = NULL;
136 128
137/* generic pci stuff */ 129 if (res->flags & IORESOURCE_IO)
138#include <asm-generic/pci.h> 130 root = &ioport_resource;
131 if (res->flags & IORESOURCE_MEM)
132 root = &iomem_resource;
133
134 return root;
135}
136
137/* Chances are this interrupt is wired PC-style ... */
138static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
139{
140 return channel ? 15 : 14;
141}
139 142
140/* generic DMA-mapping stuff */ 143/* generic DMA-mapping stuff */
141#include <asm-generic/pci-dma-compat.h> 144#include <asm-generic/pci-dma-compat.h>
142 145
146#endif /* __KERNEL__ */
143#endif /* __ASM_SH_PCI_H */ 147#endif /* __ASM_SH_PCI_H */
144 148
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index b517ae08b9c0..2a011b18090b 100644
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -154,6 +154,10 @@ extern void kmap_coherent_init(void);
154#define kmap_coherent_init() do { } while (0) 154#define kmap_coherent_init() do { } while (0)
155#endif 155#endif
156 156
157/* arch/sh/mm/mmap.c */
158#define HAVE_ARCH_UNMAPPED_AREA
159#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
160
157#include <asm-generic/pgtable.h> 161#include <asm-generic/pgtable.h>
158 162
159#endif /* __ASM_SH_PGTABLE_H */ 163#endif /* __ASM_SH_PGTABLE_H */
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 1fd58b421438..005c962c8b1c 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -32,7 +32,7 @@ enum cpu_type {
32 32
33 /* SH-4A types */ 33 /* SH-4A types */
34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, 34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
35 CPU_SH7723, CPU_SHX3, 35 CPU_SH7723, CPU_SH7724, CPU_SHX3,
36 36
37 /* SH4AL-DSP types */ 37 /* SH4AL-DSP types */
38 CPU_SH7343, CPU_SH7722, CPU_SH7366, 38 CPU_SH7343, CPU_SH7722, CPU_SH7366,
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
index 68e20ff9aa9b..1dc12cb44a2d 100644
--- a/arch/sh/include/asm/ptrace.h
+++ b/arch/sh/include/asm/ptrace.h
@@ -102,6 +102,11 @@ struct pt_dspregs {
102#define PTRACE_GETDSPREGS 55 /* DSP registers */ 102#define PTRACE_GETDSPREGS 55 /* DSP registers */
103#define PTRACE_SETDSPREGS 56 103#define PTRACE_SETDSPREGS 56
104 104
105#define PT_TEXT_END_ADDR 240
106#define PT_TEXT_ADDR 244 /* &(struct user)->start_code */
107#define PT_DATA_ADDR 248 /* &(struct user)->start_data */
108#define PT_TEXT_LEN 252
109
105#ifdef __KERNEL__ 110#ifdef __KERNEL__
106#include <asm/addrspace.h> 111#include <asm/addrspace.h>
107 112
diff --git a/arch/sh/include/asm/rtc.h b/arch/sh/include/asm/rtc.h
index f7b010d48af7..52b0c2dba979 100644
--- a/arch/sh/include/asm/rtc.h
+++ b/arch/sh/include/asm/rtc.h
@@ -6,6 +6,17 @@ extern void (*board_time_init)(void);
6extern void (*rtc_sh_get_time)(struct timespec *); 6extern void (*rtc_sh_get_time)(struct timespec *);
7extern int (*rtc_sh_set_time)(const time_t); 7extern int (*rtc_sh_set_time)(const time_t);
8 8
9/* some dummy definitions */
10#define RTC_BATT_BAD 0x100 /* battery bad */
11#define RTC_SQWE 0x08 /* enable square-wave output */
12#define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
13#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
14#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
15
16struct rtc_time;
17unsigned int get_rtc_time(struct rtc_time *);
18int set_rtc_time(struct rtc_time *);
19
9#define RTC_CAP_4_DIGIT_YEAR (1 << 0) 20#define RTC_CAP_4_DIGIT_YEAR (1 << 0)
10 21
11struct sh_rtc_platform_info { 22struct sh_rtc_platform_info {
diff --git a/arch/sh/include/asm/swab.h b/arch/sh/include/asm/swab.h
index e69315935107..0e08fe54ad71 100644
--- a/arch/sh/include/asm/swab.h
+++ b/arch/sh/include/asm/swab.h
@@ -14,15 +14,15 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
14{ 14{
15 __asm__( 15 __asm__(
16#ifdef __SH5__ 16#ifdef __SH5__
17 "byterev %0, %0\n\t" 17 "byterev %1, %0\n\t"
18 "shari %0, 32, %0" 18 "shari %0, 32, %0"
19#else 19#else
20 "swap.b %0, %0\n\t" 20 "swap.b %1, %0\n\t"
21 "swap.w %0, %0\n\t" 21 "swap.w %0, %0\n\t"
22 "swap.b %0, %0" 22 "swap.b %0, %0"
23#endif 23#endif
24 : "=r" (x) 24 : "=r" (x)
25 : "0" (x)); 25 : "r" (x));
26 26
27 return x; 27 return x;
28} 28}
@@ -32,13 +32,13 @@ static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
32{ 32{
33 __asm__( 33 __asm__(
34#ifdef __SH5__ 34#ifdef __SH5__
35 "byterev %0, %0\n\t" 35 "byterev %1, %0\n\t"
36 "shari %0, 32, %0" 36 "shari %0, 32, %0"
37#else 37#else
38 "swap.b %0, %0" 38 "swap.b %1, %0"
39#endif 39#endif
40 : "=r" (x) 40 : "=r" (x)
41 : "0" (x)); 41 : "r" (x));
42 42
43 return x; 43 return x;
44} 44}
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h
index 240b31e1142c..6c68a51f1cc5 100644
--- a/arch/sh/include/asm/system_32.h
+++ b/arch/sh/include/asm/system_32.h
@@ -198,7 +198,7 @@ do { \
198}) 198})
199#endif 199#endif
200 200
201int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs, 201int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
202 struct mem_access *ma); 202 struct mem_access *ma);
203 203
204asmlinkage void do_address_error(struct pt_regs *regs, 204asmlinkage void do_address_error(struct pt_regs *regs,
diff --git a/arch/sh/include/asm/timer.h b/arch/sh/include/asm/timer.h
deleted file mode 100644
index 4c3b66e30af2..000000000000
--- a/arch/sh/include/asm/timer.h
+++ /dev/null
@@ -1,44 +0,0 @@
1#ifndef __ASM_SH_TIMER_H
2#define __ASM_SH_TIMER_H
3
4#include <linux/sysdev.h>
5#include <linux/clocksource.h>
6#include <cpu/timer.h>
7
8struct sys_timer_ops {
9 int (*init)(void);
10 int (*start)(void);
11 int (*stop)(void);
12#ifndef CONFIG_GENERIC_TIME
13 unsigned long (*get_offset)(void);
14#endif
15};
16
17struct sys_timer {
18 const char *name;
19
20 struct sys_device dev;
21 struct sys_timer_ops *ops;
22};
23
24#define TICK_SIZE (tick_nsec / 1000)
25
26extern struct sys_timer tmu_timer, cmt_timer, mtu2_timer;
27extern struct sys_timer *sys_timer;
28
29#ifndef CONFIG_GENERIC_TIME
30static inline unsigned long get_timer_offset(void)
31{
32 return sys_timer->ops->get_offset();
33}
34#endif
35
36/* arch/sh/kernel/timers/timer.c */
37struct sys_timer *get_sys_timer(void);
38
39/* arch/sh/kernel/time.c */
40void handle_timer_tick(void);
41
42extern struct clocksource clocksource_sh;
43
44#endif /* __ASM_SH_TIMER_H */
diff --git a/arch/sh/include/asm/types.h b/arch/sh/include/asm/types.h
index beea4e6f8dfd..b13caca62a76 100644
--- a/arch/sh/include/asm/types.h
+++ b/arch/sh/include/asm/types.h
@@ -23,9 +23,9 @@ typedef unsigned short umode_t;
23typedef u32 dma_addr_t; 23typedef u32 dma_addr_t;
24 24
25#ifdef CONFIG_SUPERH32 25#ifdef CONFIG_SUPERH32
26typedef u16 opcode_t; 26typedef u16 insn_size_t;
27#else 27#else
28typedef u32 opcode_t; 28typedef u32 insn_size_t;
29#endif 29#endif
30 30
31#endif /* __ASSEMBLY__ */ 31#endif /* __ASSEMBLY__ */
diff --git a/arch/sh/include/asm/ubc.h b/arch/sh/include/asm/ubc.h
index a7b9028bbfbb..4ca4b7717371 100644
--- a/arch/sh/include/asm/ubc.h
+++ b/arch/sh/include/asm/ubc.h
@@ -42,12 +42,23 @@
42 42
43#define BRCR_CMFA (1 << 15) 43#define BRCR_CMFA (1 << 15)
44#define BRCR_CMFB (1 << 14) 44#define BRCR_CMFB (1 << 14)
45
46#if defined CONFIG_CPU_SH2A
47#define BRCR_CMFCA (1 << 15)
48#define BRCR_CMFCB (1 << 14)
49#define BRCR_CMFDA (1 << 13)
50#define BRCR_CMFDB (1 << 12)
51#define BRCR_PCBB (1 << 6) /* 1: after execution */
52#define BRCR_PCBA (1 << 5) /* 1: after execution */
53#define BRCR_PCTE 0
54#else
45#define BRCR_PCTE (1 << 11) 55#define BRCR_PCTE (1 << 11)
46#define BRCR_PCBA (1 << 10) /* 1: after execution */ 56#define BRCR_PCBA (1 << 10) /* 1: after execution */
47#define BRCR_DBEB (1 << 7) 57#define BRCR_DBEB (1 << 7)
48#define BRCR_PCBB (1 << 6) 58#define BRCR_PCBB (1 << 6)
49#define BRCR_SEQ (1 << 3) 59#define BRCR_SEQ (1 << 3)
50#define BRCR_UBDE (1 << 0) 60#define BRCR_UBDE (1 << 0)
61#endif
51 62
52#ifndef __ASSEMBLY__ 63#ifndef __ASSEMBLY__
53/* arch/sh/kernel/cpu/ubc.S */ 64/* arch/sh/kernel/cpu/ubc.S */
diff --git a/arch/sh/include/cpu-sh2a/cpu/ubc.h b/arch/sh/include/cpu-sh2a/cpu/ubc.h
index 8ce2fc1cf625..1192e1c761a7 100644
--- a/arch/sh/include/cpu-sh2a/cpu/ubc.h
+++ b/arch/sh/include/cpu-sh2a/cpu/ubc.h
@@ -1 +1,28 @@
1#include <cpu-sh2/cpu/ubc.h> 1/*
2 * SH-2A UBC definitions
3 *
4 * Copyright (C) 2008 Kieran Bingham
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef __ASM_CPU_SH2A_UBC_H
12#define __ASM_CPU_SH2A_UBC_H
13
14#define UBC_BARA 0xfffc0400
15#define UBC_BAMRA 0xfffc0404
16#define UBC_BBRA 0xfffc04a0 /* 16 bit access */
17#define UBC_BDRA 0xfffc0408
18#define UBC_BDMRA 0xfffc040c
19
20#define UBC_BARB 0xfffc0410
21#define UBC_BAMRB 0xfffc0414
22#define UBC_BBRB 0xfffc04b0 /* 16 bit access */
23#define UBC_BDRB 0xfffc0418
24#define UBC_BDMRB 0xfffc041c
25
26#define UBC_BRCR 0xfffc04c0
27
28#endif /* __ASM_CPU_SH2A_UBC_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/timer.h b/arch/sh/include/cpu-sh3/cpu/timer.h
deleted file mode 100644
index 793acf12aa08..000000000000
--- a/arch/sh/include/cpu-sh3/cpu/timer.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/timer.h
3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_TIMER_H
11#define __ASM_CPU_SH3_TIMER_H
12
13/*
14 * ---------------------------------------------------------------------------
15 * TMU Common definitions for SH3 processors
16 * SH7706
17 * SH7709S
18 * SH7727
19 * SH7729R
20 * SH7710
21 * SH7720
22 * SH7710
23 * ---------------------------------------------------------------------------
24 */
25
26#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
27#define TMU_TOCR 0xfffffe90 /* Byte access */
28#endif
29
30#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7721)
33#define TMU_012_TSTR 0xa412fe92 /* Byte access */
34
35#define TMU0_TCOR 0xa412fe94 /* Long access */
36#define TMU0_TCNT 0xa412fe98 /* Long access */
37#define TMU0_TCR 0xa412fe9c /* Word access */
38
39#define TMU1_TCOR 0xa412fea0 /* Long access */
40#define TMU1_TCNT 0xa412fea4 /* Long access */
41#define TMU1_TCR 0xa412fea8 /* Word access */
42
43#define TMU2_TCOR 0xa412feac /* Long access */
44#define TMU2_TCNT 0xa412feb0 /* Long access */
45#define TMU2_TCR 0xa412feb4 /* Word access */
46
47#else
48#define TMU_012_TSTR 0xfffffe92 /* Byte access */
49
50#define TMU0_TCOR 0xfffffe94 /* Long access */
51#define TMU0_TCNT 0xfffffe98 /* Long access */
52#define TMU0_TCR 0xfffffe9c /* Word access */
53
54#define TMU1_TCOR 0xfffffea0 /* Long access */
55#define TMU1_TCNT 0xfffffea4 /* Long access */
56#define TMU1_TCR 0xfffffea8 /* Word access */
57
58#define TMU2_TCOR 0xfffffeac /* Long access */
59#define TMU2_TCNT 0xfffffeb0 /* Long access */
60#define TMU2_TCR 0xfffffeb4 /* Word access */
61#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
62#define TMU2_TCPR2 0xfffffeb8 /* Long access */
63#endif
64#endif
65
66#endif /* __ASM_CPU_SH3_TIMER_H */
67
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index 749d1c434337..ccf1d999db6d 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -25,6 +25,24 @@
25#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 25#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
26 defined(CONFIG_CPU_SUBTYPE_SH7780) 26 defined(CONFIG_CPU_SUBTYPE_SH7780)
27#define FRQCR 0xffc80000 27#define FRQCR 0xffc80000
28#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
29#define FRQCRA 0xa4150000
30#define FRQCRB 0xa4150004
31#define VCLKCR 0xa4150048
32
33#define FCLKACR 0xa4150008
34#define FCLKBCR 0xa415000c
35#define FRQCR FRQCRA
36#define SCLKACR FCLKACR
37#define SCLKBCR FCLKBCR
38#define FCLKACR 0xa4150008
39#define FCLKBCR 0xa415000c
40#define IrDACLKCR 0xa4150018
41
42#define MSTPCR0 0xa4150030
43#define MSTPCR1 0xa4150034
44#define MSTPCR2 0xa4150038
45
28#elif defined(CONFIG_CPU_SUBTYPE_SH7785) 46#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
29#define FRQCR0 0xffc80000 47#define FRQCR0 0xffc80000
30#define FRQCR1 0xffc80004 48#define FRQCR1 0xffc80004
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7724.h b/arch/sh/include/cpu-sh4/cpu/sh7724.h
new file mode 100644
index 000000000000..34605c9e354d
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7724.h
@@ -0,0 +1,255 @@
1#ifndef __ASM_SH7724_H__
2#define __ASM_SH7724_H__
3
4enum {
5 /* PTA */
6 GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
7 GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
8
9 /* PTB */
10 GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
11 GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
12
13 /* PTC */
14 GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4,
15 GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0,
16
17 /* PTD */
18 GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
19 GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
20
21 /* PTE */
22 GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4,
23 GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0,
24
25 /* PTF */
26 GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4,
27 GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0,
28
29 /* PTG */
30 GPIO_PTG5, GPIO_PTG4,
31 GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0,
32
33 /* PTH */
34 GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4,
35 GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
36
37 /* PTJ */
38 GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5,
39 GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0,
40
41 /* PTK */
42 GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4,
43 GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
44
45 /* PTL */
46 GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4,
47 GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0,
48
49 /* PTM */
50 GPIO_PTM7, GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
51 GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
52
53 /* PTN */
54 GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4,
55 GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,
56
57 /* PTQ */
58 GPIO_PTQ7, GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,
59 GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,
60
61 /* PTR */
62 GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4,
63 GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
64
65 /* PTS */
66 GPIO_PTS6, GPIO_PTS5, GPIO_PTS4,
67 GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
68
69 /* PTT */
70 GPIO_PTT7, GPIO_PTT6, GPIO_PTT5, GPIO_PTT4,
71 GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0,
72
73 /* PTU */
74 GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4,
75 GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0,
76
77 /* PTV */
78 GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4,
79 GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
80
81 /* PTW */
82 GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4,
83 GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0,
84
85 /* PTX */
86 GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4,
87 GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0,
88
89 /* PTY */
90 GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4,
91 GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0,
92
93 /* PTZ */
94 GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4,
95 GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0,
96
97 /* BSC (PTA/PTB/PTJ/PTQ/PTR/PTT) */
98 GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28,
99 GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24,
100 GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20,
101 GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16,
102 GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
103 GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
104 GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
105 GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
106 GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22,
107 GPIO_FN_CS6B_CE1B, GPIO_FN_CS6A_CE2B,
108 GPIO_FN_CS5B_CE1A, GPIO_FN_CS5A_CE2A,
109 GPIO_FN_WE3_ICIOWR, GPIO_FN_WE2_ICIORD,
110 GPIO_FN_IOIS16, GPIO_FN_WAIT,
111 GPIO_FN_BS,
112
113 /* KEYSC (PTA/PTB)*/
114 GPIO_FN_KEYOUT5_IN5, GPIO_FN_KEYOUT4_IN6, GPIO_FN_KEYIN4,
115 GPIO_FN_KEYIN3, GPIO_FN_KEYIN2, GPIO_FN_KEYIN1, GPIO_FN_KEYIN0,
116 GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT2, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT0,
117
118 /* ATAPI (PTA/PTB/PTK/PTR/PTS/PTW) */
119 GPIO_FN_IDED15, GPIO_FN_IDED14, GPIO_FN_IDED13, GPIO_FN_IDED12,
120 GPIO_FN_IDED11, GPIO_FN_IDED10, GPIO_FN_IDED9, GPIO_FN_IDED8,
121 GPIO_FN_IDED7, GPIO_FN_IDED6, GPIO_FN_IDED5, GPIO_FN_IDED4,
122 GPIO_FN_IDED3, GPIO_FN_IDED2, GPIO_FN_IDED1, GPIO_FN_IDED0,
123 GPIO_FN_IDEA2, GPIO_FN_IDEA1, GPIO_FN_IDEA0, GPIO_FN_IDEIOWR,
124 GPIO_FN_IODREQ, GPIO_FN_IDECS0, GPIO_FN_IDECS1, GPIO_FN_IDEIORD,
125 GPIO_FN_DIRECTION, GPIO_FN_EXBUF_ENB, GPIO_FN_IDERST, GPIO_FN_IODACK,
126 GPIO_FN_IDEINT, GPIO_FN_IDEIORDY,
127
128 /* TPU (PTB/PTR/PTS) */
129 GPIO_FN_TPUTO3, GPIO_FN_TPUTO2, GPIO_FN_TPUTO1, GPIO_FN_TPUTO0,
130 GPIO_FN_TPUTI3, GPIO_FN_TPUTI2,
131
132 /* LCDC (PTC/PTD/PTE/PTF/PTM/PTR) */
133 GPIO_FN_LCDD23, GPIO_FN_LCDD22, GPIO_FN_LCDD21, GPIO_FN_LCDD20,
134 GPIO_FN_LCDD19, GPIO_FN_LCDD18, GPIO_FN_LCDD17, GPIO_FN_LCDD16,
135 GPIO_FN_LCDD15, GPIO_FN_LCDD14, GPIO_FN_LCDD13, GPIO_FN_LCDD12,
136 GPIO_FN_LCDD11, GPIO_FN_LCDD10, GPIO_FN_LCDD9, GPIO_FN_LCDD8,
137 GPIO_FN_LCDD7, GPIO_FN_LCDD6, GPIO_FN_LCDD5, GPIO_FN_LCDD4,
138 GPIO_FN_LCDD3, GPIO_FN_LCDD2, GPIO_FN_LCDD1, GPIO_FN_LCDD0,
139 GPIO_FN_LCDVSYN, GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_LCDHSYN,
140 GPIO_FN_LCDCS, GPIO_FN_LCDDON, GPIO_FN_LCDDCK, GPIO_FN_LCDWR,
141 GPIO_FN_LCDVEPWC, GPIO_FN_LCDVCPWC, GPIO_FN_LCDRD, GPIO_FN_LCDLCLK,
142
143 /* SCIF0 (PTF/PTM) */
144 GPIO_FN_SCIF0_TXD, GPIO_FN_SCIF0_RXD, GPIO_FN_SCIF0_SCK,
145
146 /* SCIF1 (PTL) */
147 GPIO_FN_SCIF1_SCK, GPIO_FN_SCIF1_RXD, GPIO_FN_SCIF1_TXD,
148
149 /* SCIF2 (PTE/PTF/PTN) with LCDC, VOU */
150 GPIO_FN_SCIF2_L_TXD, GPIO_FN_SCIF2_L_SCK, GPIO_FN_SCIF2_L_RXD,
151 GPIO_FN_SCIF2_V_TXD, GPIO_FN_SCIF2_V_SCK, GPIO_FN_SCIF2_V_RXD,
152
153 /* SCIF3 (PTL/PTN/PTZ) with VOU, IRQ */
154 GPIO_FN_SCIF3_V_SCK, GPIO_FN_SCIF3_V_RXD, GPIO_FN_SCIF3_V_TXD,
155 GPIO_FN_SCIF3_V_CTS, GPIO_FN_SCIF3_V_RTS,
156 GPIO_FN_SCIF3_I_SCK, GPIO_FN_SCIF3_I_RXD, GPIO_FN_SCIF3_I_TXD,
157 GPIO_FN_SCIF3_I_CTS, GPIO_FN_SCIF3_I_RTS,
158
159 /* SCIF4 (PTE) */
160 GPIO_FN_SCIF4_SCK, GPIO_FN_SCIF4_RXD, GPIO_FN_SCIF4_TXD,
161
162 /* SCIF5 (PTS) */
163 GPIO_FN_SCIF5_SCK, GPIO_FN_SCIF5_RXD, GPIO_FN_SCIF5_TXD,
164
165 /* FSI (PTE/PTU/PTV) */
166 GPIO_FN_FSIMCKB, GPIO_FN_FSIMCKA, GPIO_FN_FSIOASD,
167 GPIO_FN_FSIIABCK, GPIO_FN_FSIIALRCK, GPIO_FN_FSIOABCK,
168 GPIO_FN_FSIOALRCK, GPIO_FN_CLKAUDIOAO, GPIO_FN_FSIIBSD,
169 GPIO_FN_FSIOBSD, GPIO_FN_FSIIBBCK, GPIO_FN_FSIIBLRCK,
170 GPIO_FN_FSIOBBCK, GPIO_FN_FSIOBLRCK, GPIO_FN_CLKAUDIOBO,
171 GPIO_FN_FSIIASD,
172
173 /* AUD (PTG) */
174 GPIO_FN_AUDCK, GPIO_FN_AUDSYNC, GPIO_FN_AUDATA3,
175 GPIO_FN_AUDATA2, GPIO_FN_AUDATA1, GPIO_FN_AUDATA0,
176
177 /* VIO (PTS) (common?) */
178 GPIO_FN_VIO_CKO,
179
180 /* VIO0 (PTH/PTK) */
181 GPIO_FN_VIO0_D15, GPIO_FN_VIO0_D14, GPIO_FN_VIO0_D13, GPIO_FN_VIO0_D12,
182 GPIO_FN_VIO0_D11, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D8,
183 GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D5, GPIO_FN_VIO0_D4,
184 GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D2, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D0,
185 GPIO_FN_VIO0_VD, GPIO_FN_VIO0_CLK,
186 GPIO_FN_VIO0_FLD, GPIO_FN_VIO0_HD,
187
188 /* VIO1 (PTK/PTS) */
189 GPIO_FN_VIO1_D7, GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D5, GPIO_FN_VIO1_D4,
190 GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D2, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D0,
191 GPIO_FN_VIO1_FLD, GPIO_FN_VIO1_HD, GPIO_FN_VIO1_VD, GPIO_FN_VIO1_CLK,
192
193 /* Eth (PTL/PTN/PTX) */
194 GPIO_FN_RMII_RXD0, GPIO_FN_RMII_RXD1,
195 GPIO_FN_RMII_TXD0, GPIO_FN_RMII_TXD1,
196 GPIO_FN_RMII_REF_CLK, GPIO_FN_RMII_TX_EN,
197 GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_CRS_DV,
198 GPIO_FN_LNKSTA, GPIO_FN_MDIO,
199 GPIO_FN_MDC,
200
201 /* System (PTJ) */
202 GPIO_FN_PDSTATUS, GPIO_FN_STATUS2, GPIO_FN_STATUS0,
203
204 /* VOU (PTL/PTM/PTN*/
205 GPIO_FN_DV_D15, GPIO_FN_DV_D14, GPIO_FN_DV_D13, GPIO_FN_DV_D12,
206 GPIO_FN_DV_D11, GPIO_FN_DV_D10, GPIO_FN_DV_D9, GPIO_FN_DV_D8,
207 GPIO_FN_DV_D7, GPIO_FN_DV_D6, GPIO_FN_DV_D5, GPIO_FN_DV_D4,
208 GPIO_FN_DV_D3, GPIO_FN_DV_D2, GPIO_FN_DV_D1, GPIO_FN_DV_D0,
209 GPIO_FN_DV_CLKI, GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC,
210
211 /* MSIOF0 (PTL/PTM) */
212 GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
213 GPIO_FN_MSIOF0_MCK, GPIO_FN_MSIOF0_TSCK,
214 GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
215 GPIO_FN_MSIOF0_TSYNC, GPIO_FN_MSIOF0_RSCK,
216 GPIO_FN_MSIOF0_RSYNC,
217
218 /* MSIOF1 (PTV) */
219 GPIO_FN_MSIOF1_RXD, GPIO_FN_MSIOF1_TXD,
220 GPIO_FN_MSIOF1_MCK, GPIO_FN_MSIOF1_TSCK,
221 GPIO_FN_MSIOF1_SS1, GPIO_FN_MSIOF1_SS2,
222 GPIO_FN_MSIOF1_TSYNC, GPIO_FN_MSIOF1_RSCK,
223 GPIO_FN_MSIOF1_RSYNC,
224
225 /* DMAC (PTU/PTX) */
226 GPIO_FN_DMAC_DACK0, GPIO_FN_DMAC_DREQ0,
227 GPIO_FN_DMAC_DACK1, GPIO_FN_DMAC_DREQ1,
228
229 /* SDHI0 (PTY) */
230 GPIO_FN_SDHI0CD, GPIO_FN_SDHI0WP, GPIO_FN_SDHI0CMD, GPIO_FN_SDHI0CLK,
231 GPIO_FN_SDHI0D3, GPIO_FN_SDHI0D2, GPIO_FN_SDHI0D1, GPIO_FN_SDHI0D0,
232
233 /* SDHI1 (PTW) */
234 GPIO_FN_SDHI1CD, GPIO_FN_SDHI1WP, GPIO_FN_SDHI1CMD, GPIO_FN_SDHI1CLK,
235 GPIO_FN_SDHI1D3, GPIO_FN_SDHI1D2, GPIO_FN_SDHI1D1, GPIO_FN_SDHI1D0,
236
237 /* MMC (PTW/PTX)*/
238 GPIO_FN_MMC_D7, GPIO_FN_MMC_D6, GPIO_FN_MMC_D5, GPIO_FN_MMC_D4,
239 GPIO_FN_MMC_D3, GPIO_FN_MMC_D2, GPIO_FN_MMC_D1, GPIO_FN_MMC_D0,
240 GPIO_FN_MMC_CLK, GPIO_FN_MMC_CMD,
241
242 /* IrDA (PTX) */
243 GPIO_FN_IRDA_OUT, GPIO_FN_IRDA_IN,
244
245 /* TSIF (PTX) */
246 GPIO_FN_TSIF_TS0_SDAT, GPIO_FN_TSIF_TS0_SCK,
247 GPIO_FN_TSIF_TS0_SDEN, GPIO_FN_TSIF_TS0_SPSYNC,
248
249 /* IRQ (PTZ) */
250 GPIO_FN_INTC_IRQ7, GPIO_FN_INTC_IRQ6, GPIO_FN_INTC_IRQ5,
251 GPIO_FN_INTC_IRQ4, GPIO_FN_INTC_IRQ3, GPIO_FN_INTC_IRQ2,
252 GPIO_FN_INTC_IRQ1, GPIO_FN_INTC_IRQ0,
253};
254
255#endif /* __ASM_SH7724_H__ */
diff --git a/arch/sh/include/cpu-sh4/cpu/timer.h b/arch/sh/include/cpu-sh4/cpu/timer.h
deleted file mode 100644
index d1e796b96888..000000000000
--- a/arch/sh/include/cpu-sh4/cpu/timer.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/timer.h
3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_TIMER_H
11#define __ASM_CPU_SH4_TIMER_H
12
13/*
14 * ---------------------------------------------------------------------------
15 * TMU Common definitions for SH4 processors
16 * SH7750S/SH7750R
17 * SH7751/SH7751R
18 * SH7760
19 * SH-X3
20 * ---------------------------------------------------------------------------
21 */
22#ifdef CONFIG_CPU_SUBTYPE_SHX3
23#define TMU_012_BASE 0xffc10000
24#define TMU_345_BASE 0xffc20000
25#else
26#define TMU_012_BASE 0xffd80000
27#define TMU_345_BASE 0xfe100000
28#endif
29
30#define TMU_TOCR TMU_012_BASE /* Not supported on all CPUs */
31
32#define TMU_012_TSTR (TMU_012_BASE + 0x04)
33#define TMU_345_TSTR (TMU_345_BASE + 0x04)
34
35#define TMU0_TCOR (TMU_012_BASE + 0x08)
36#define TMU0_TCNT (TMU_012_BASE + 0x0c)
37#define TMU0_TCR (TMU_012_BASE + 0x10)
38
39#define TMU1_TCOR (TMU_012_BASE + 0x14)
40#define TMU1_TCNT (TMU_012_BASE + 0x18)
41#define TMU1_TCR (TMU_012_BASE + 0x1c)
42
43#define TMU2_TCOR (TMU_012_BASE + 0x20)
44#define TMU2_TCNT (TMU_012_BASE + 0x24)
45#define TMU2_TCR (TMU_012_BASE + 0x28)
46#define TMU2_TCPR (TMU_012_BASE + 0x2c)
47
48#define TMU3_TCOR (TMU_345_BASE + 0x08)
49#define TMU3_TCNT (TMU_345_BASE + 0x0c)
50#define TMU3_TCR (TMU_345_BASE + 0x10)
51
52#define TMU4_TCOR (TMU_345_BASE + 0x14)
53#define TMU4_TCNT (TMU_345_BASE + 0x18)
54#define TMU4_TCR (TMU_345_BASE + 0x1c)
55
56#define TMU5_TCOR (TMU_345_BASE + 0x20)
57#define TMU5_TCNT (TMU_345_BASE + 0x24)
58#define TMU5_TCR (TMU_345_BASE + 0x28)
59
60#endif /* __ASM_CPU_SH4_TIMER_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/irq.h b/arch/sh/include/cpu-sh5/cpu/irq.h
index f0f0756e6e84..0ccf257a72d1 100644
--- a/arch/sh/include/cpu-sh5/cpu/irq.h
+++ b/arch/sh/include/cpu-sh5/cpu/irq.h
@@ -111,7 +111,6 @@
111#define TOP_PRIORITY 15 111#define TOP_PRIORITY 15
112 112
113extern int intc_evt_to_irq[(0xE20/0x20)+1]; 113extern int intc_evt_to_irq[(0xE20/0x20)+1];
114int intc_irq_describe(char* p, int irq);
115extern int platform_int_priority[NR_INTC_IRQS]; 114extern int platform_int_priority[NR_INTC_IRQS];
116 115
117#endif /* __ASM_SH_CPU_SH5_IRQ_H */ 116#endif /* __ASM_SH_CPU_SH5_IRQ_H */
diff --git a/arch/sh/include/mach-common/mach/sh7785lcr.h b/arch/sh/include/mach-common/mach/sh7785lcr.h
index 1ce27d5c7491..90011d435f30 100644
--- a/arch/sh/include/mach-common/mach/sh7785lcr.h
+++ b/arch/sh/include/mach-common/mach/sh7785lcr.h
@@ -9,11 +9,11 @@
9 * -----------------------------+---------------+--------------- 9 * -----------------------------+---------------+---------------
10 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash 10 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
11 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD 11 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
12 * 0x06000000 - 0x07ffffff(CS1) | reserved | I2C 12 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
13 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM 13 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
14 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM 14 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
15 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107 15 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
16 * 0x14000000 - 0x17ffffff(CS5) | I2C | USB 16 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB
17 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD 17 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
18 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use) 18 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
19 * 19 *
@@ -32,6 +32,9 @@
32#define PLD_VERSR (PLD_BASE_ADDR + 0x0c) 32#define PLD_VERSR (PLD_BASE_ADDR + 0x0c)
33#define PLD_MMSR (PLD_BASE_ADDR + 0x0e) 33#define PLD_MMSR (PLD_BASE_ADDR + 0x0e)
34 34
35#define PCA9564_ADDR 0x06000000 /* I2C */
36#define PCA9564_SIZE 0x00000100
37
35#define SM107_MEM_ADDR 0x10000000 38#define SM107_MEM_ADDR 0x10000000
36#define SM107_MEM_SIZE 0x00e00000 39#define SM107_MEM_SIZE 0x00e00000
37#define SM107_REG_ADDR 0x13e00000 40#define SM107_REG_ADDR 0x13e00000
@@ -40,16 +43,13 @@
40#if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS) 43#if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS)
41#define R8A66597_ADDR 0x14000000 /* USB */ 44#define R8A66597_ADDR 0x14000000 /* USB */
42#define CG200_ADDR 0x18000000 /* SD */ 45#define CG200_ADDR 0x18000000 /* SD */
43#define PCA9564_ADDR 0x06000000 /* I2C */
44#else 46#else
45#define R8A66597_ADDR 0x08000000 47#define R8A66597_ADDR 0x08000000
46#define CG200_ADDR 0x0c000000 48#define CG200_ADDR 0x0c000000
47#define PCA9564_ADDR 0x14000000
48#endif 49#endif
49 50
50#define R8A66597_SIZE 0x00000100 51#define R8A66597_SIZE 0x00000100
51#define CG200_SIZE 0x00010000 52#define CG200_SIZE 0x00010000
52#define PCA9564_SIZE 0x00000100
53 53
54#endif /* __ASM_SH_RENESAS_SH7785LCR_H */ 54#endif /* __ASM_SH_RENESAS_SH7785LCR_H */
55 55
diff --git a/arch/sh/include/mach-dreamcast/mach/pci.h b/arch/sh/include/mach-dreamcast/mach/pci.h
index 75fc9009e092..0314d975e626 100644
--- a/arch/sh/include/mach-dreamcast/mach/pci.h
+++ b/arch/sh/include/mach-dreamcast/mach/pci.h
@@ -21,5 +21,7 @@
21 21
22#define GAPSPCI_IRQ HW_EVENT_EXTERNAL 22#define GAPSPCI_IRQ HW_EVENT_EXTERNAL
23 23
24extern struct pci_ops gapspci_pci_ops;
25
24#endif /* __ASM_SH_DREAMCAST_PCI_H */ 26#endif /* __ASM_SH_DREAMCAST_PCI_H */
25 27
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-20 09:37:55 -0400