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authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-23 12:00:40 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-23 12:00:40 -0400
commit1d767cae4dbd4116fc3b2cc3251a20760f98339f (patch)
tree79a1a48a67a9b4296ce062d61ee863fe7a46c77f /arch/sh/include
parent6101167727932a929e37fb8a6eeb68bdbf54d58e (diff)
parent5f19f14fed7786652b9617c633db101d26a42251 (diff)
Merge tag 'sh-for-linus' of git://github.com/pmundt/linux-sh
Pull SuperH updates from Paul Mundt: - New CPUs: SH7734 (SH-4A), SH7264 and SH7269 (SH-2A) - New boards: RSK2+SH7264, RSK2+SH7269 - Unbreaking kgdb for SMP - Consolidation of _32/_64 page fault handling. - watchdog and legacy DMA chainsawing, part 1 - Conversion to evt2irq() hwirq lookup, to support relocation of vectored IRQs for irqdomains. * tag 'sh-for-linus' of git://github.com/pmundt/linux-sh: (98 commits) sh: intc: Kill off special reservation interface. sh: Enable PIO API for hp6xx and se770x. sh: Kill off machvec IRQ hinting. sh: dma: More legacy cpu dma chainsawing. sh: Kill off MAX_DMA_ADDRESS leftovers. sh: Tidy up some of the cpu legacy dma header mess. sh: Move sh4a dma header from cpu-sh4 to cpu-sh4a. sh64: Fix up vmalloc fault range check. Revert "sh: Ensure fixmap and store queue space can co-exist." serial: sh-sci: Fix for port types without BRI interrupts. sh: legacy PCI evt2irq migration. sh: cpu dma evt2irq migration. sh: sh7763rdp evt2irq migration. sh: sdk7780 evt2irq migration. sh: migor evt2irq migration. sh: landisk evt2irq migration. sh: kfr2r09 evt2irq migration. sh: ecovec24 evt2irq migration. sh: ap325rxa evt2irq migration. sh: urquell evt2irq migration. ...
Diffstat (limited to 'arch/sh/include')
-rw-r--r--arch/sh/include/asm/dma-sh.h87
-rw-r--r--arch/sh/include/asm/dma.h9
-rw-r--r--arch/sh/include/asm/fixmap.h2
-rw-r--r--arch/sh/include/asm/i2c-sh7760.h2
-rw-r--r--arch/sh/include/asm/io.h5
-rw-r--r--arch/sh/include/asm/io_noioport.h41
-rw-r--r--arch/sh/include/asm/irq.h13
-rw-r--r--arch/sh/include/asm/kdebug.h2
-rw-r--r--arch/sh/include/asm/kgdb.h30
-rw-r--r--arch/sh/include/asm/machvec.h1
-rw-r--r--arch/sh/include/asm/pgtable_64.h3
-rw-r--r--arch/sh/include/asm/processor.h5
-rw-r--r--arch/sh/include/asm/processor_64.h3
-rw-r--r--arch/sh/include/asm/stackprotector.h27
-rw-r--r--arch/sh/include/asm/thread_info.h46
-rw-r--r--arch/sh/include/asm/traps_64.h14
-rw-r--r--arch/sh/include/cpu-sh2/cpu/dma.h23
-rw-r--r--arch/sh/include/cpu-sh2a/cpu/dma.h1
-rw-r--r--arch/sh/include/cpu-sh2a/cpu/sh7264.h176
-rw-r--r--arch/sh/include/cpu-sh2a/cpu/sh7269.h201
-rw-r--r--arch/sh/include/cpu-sh3/cpu/dma.h13
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-sh4a.h83
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma.h25
-rw-r--r--arch/sh/include/cpu-sh4/cpu/freq.h5
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7734.h306
-rw-r--r--arch/sh/include/cpu-sh4a/cpu/dma.h72
-rw-r--r--arch/sh/include/cpu-sh5/cpu/dma.h6
-rw-r--r--arch/sh/include/mach-common/mach/hp6xx.h7
-rw-r--r--arch/sh/include/mach-common/mach/lboxre2.h13
-rw-r--r--arch/sh/include/mach-common/mach/sdk7780.h5
-rw-r--r--arch/sh/include/mach-common/mach/titan.h12
-rw-r--r--arch/sh/include/mach-dreamcast/mach/dma.h2
-rw-r--r--arch/sh/include/mach-landisk/mach/iodata_landisk.h19
-rw-r--r--arch/sh/include/mach-se/mach/se.h19
-rw-r--r--arch/sh/include/mach-se/mach/se7343.h9
-rw-r--r--arch/sh/include/mach-se/mach/se7721.h6
-rw-r--r--arch/sh/include/mach-se/mach/se7722.h9
-rw-r--r--arch/sh/include/mach-se/mach/se7724.h7
-rw-r--r--arch/sh/include/mach-se/mach/se7751.h3
-rw-r--r--arch/sh/include/mach-se/mach/se7780.h7
40 files changed, 985 insertions, 334 deletions
diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h
deleted file mode 100644
index f3acb8e34c6b..000000000000
--- a/arch/sh/include/asm/dma-sh.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * arch/sh/include/asm/dma-sh.h
3 *
4 * Copyright (C) 2000 Takashi YOSHII
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __DMA_SH_H
12#define __DMA_SH_H
13
14#include <asm/dma-register.h>
15#include <cpu/dma-register.h>
16#include <cpu/dma.h>
17
18/* DMAOR contorl: The DMAOR access size is different by CPU.*/
19#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
20 defined(CONFIG_CPU_SUBTYPE_SH7724) || \
21 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
22 defined(CONFIG_CPU_SUBTYPE_SH7785)
23#define dmaor_read_reg(n) \
24 (n ? __raw_readw(SH_DMAC_BASE1 + DMAOR) \
25 : __raw_readw(SH_DMAC_BASE0 + DMAOR))
26#define dmaor_write_reg(n, data) \
27 (n ? __raw_writew(data, SH_DMAC_BASE1 + DMAOR) \
28 : __raw_writew(data, SH_DMAC_BASE0 + DMAOR))
29#else /* Other CPU */
30#define dmaor_read_reg(n) __raw_readw(SH_DMAC_BASE0 + DMAOR)
31#define dmaor_write_reg(n, data) __raw_writew(data, SH_DMAC_BASE0 + DMAOR)
32#endif
33
34static int dmte_irq_map[] __maybe_unused = {
35#if (MAX_DMA_CHANNELS >= 4)
36 DMTE0_IRQ,
37 DMTE0_IRQ + 1,
38 DMTE0_IRQ + 2,
39 DMTE0_IRQ + 3,
40#endif
41#if (MAX_DMA_CHANNELS >= 6)
42 DMTE4_IRQ,
43 DMTE4_IRQ + 1,
44#endif
45#if (MAX_DMA_CHANNELS >= 8)
46 DMTE6_IRQ,
47 DMTE6_IRQ + 1,
48#endif
49#if (MAX_DMA_CHANNELS >= 12)
50 DMTE8_IRQ,
51 DMTE9_IRQ,
52 DMTE10_IRQ,
53 DMTE11_IRQ,
54#endif
55};
56
57/*
58 * Define the default configuration for dual address memory-memory transfer.
59 * The 0x400 value represents auto-request, external->external.
60 */
61#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT))
62
63/* DMA base address */
64static u32 dma_base_addr[] __maybe_unused = {
65#if (MAX_DMA_CHANNELS >= 4)
66 SH_DMAC_BASE0 + 0x00, /* channel 0 */
67 SH_DMAC_BASE0 + 0x10,
68 SH_DMAC_BASE0 + 0x20,
69 SH_DMAC_BASE0 + 0x30,
70#endif
71#if (MAX_DMA_CHANNELS >= 6)
72 SH_DMAC_BASE0 + 0x50,
73 SH_DMAC_BASE0 + 0x60,
74#endif
75#if (MAX_DMA_CHANNELS >= 8)
76 SH_DMAC_BASE1 + 0x00,
77 SH_DMAC_BASE1 + 0x10,
78#endif
79#if (MAX_DMA_CHANNELS >= 12)
80 SH_DMAC_BASE1 + 0x20,
81 SH_DMAC_BASE1 + 0x30,
82 SH_DMAC_BASE1 + 0x50,
83 SH_DMAC_BASE1 + 0x60, /* channel 11 */
84#endif
85};
86
87#endif /* __DMA_SH_H */
diff --git a/arch/sh/include/asm/dma.h b/arch/sh/include/asm/dma.h
index 6aa2080c0065..fb6e4f7b00a2 100644
--- a/arch/sh/include/asm/dma.h
+++ b/arch/sh/include/asm/dma.h
@@ -15,17 +15,8 @@
15#include <linux/wait.h> 15#include <linux/wait.h>
16#include <linux/sched.h> 16#include <linux/sched.h>
17#include <linux/device.h> 17#include <linux/device.h>
18#include <cpu/dma.h>
19#include <asm-generic/dma.h> 18#include <asm-generic/dma.h>
20 19
21#ifdef CONFIG_NR_DMA_CHANNELS
22# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
23#elif defined(CONFIG_NR_ONCHIP_DMA_CHANNELS)
24# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
25#else
26# define MAX_DMA_CHANNELS 0
27#endif
28
29/* 20/*
30 * Read and write modes can mean drastically different things depending on the 21 * Read and write modes can mean drastically different things depending on the
31 * channel configuration. Consult your DMAC documentation and module 22 * channel configuration. Consult your DMAC documentation and module
diff --git a/arch/sh/include/asm/fixmap.h b/arch/sh/include/asm/fixmap.h
index bd7e79a12653..cbe0186b6794 100644
--- a/arch/sh/include/asm/fixmap.h
+++ b/arch/sh/include/asm/fixmap.h
@@ -96,7 +96,7 @@ extern void __clear_fixmap(enum fixed_addresses idx, pgprot_t flags);
96#ifdef CONFIG_SUPERH32 96#ifdef CONFIG_SUPERH32
97#define FIXADDR_TOP (P4SEG - PAGE_SIZE) 97#define FIXADDR_TOP (P4SEG - PAGE_SIZE)
98#else 98#else
99#define FIXADDR_TOP (0xff000000 - PAGE_SIZE) 99#define FIXADDR_TOP ((unsigned long)(-PAGE_SIZE))
100#endif 100#endif
101#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) 101#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
102#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 102#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
diff --git a/arch/sh/include/asm/i2c-sh7760.h b/arch/sh/include/asm/i2c-sh7760.h
index 24182116711f..69fee1239b03 100644
--- a/arch/sh/include/asm/i2c-sh7760.h
+++ b/arch/sh/include/asm/i2c-sh7760.h
@@ -9,11 +9,9 @@
9 9
10#define SH7760_I2C0_MMIO 0xFE140000 10#define SH7760_I2C0_MMIO 0xFE140000
11#define SH7760_I2C0_MMIOEND 0xFE14003B 11#define SH7760_I2C0_MMIOEND 0xFE14003B
12#define SH7760_I2C0_IRQ 62
13 12
14#define SH7760_I2C1_MMIO 0xFE150000 13#define SH7760_I2C1_MMIO 0xFE150000
15#define SH7760_I2C1_MMIOEND 0xFE15003B 14#define SH7760_I2C1_MMIOEND 0xFE15003B
16#define SH7760_I2C1_IRQ 63
17 15
18struct sh7760_i2c_platdata { 16struct sh7760_i2c_platdata {
19 unsigned int speed_khz; 17 unsigned int speed_khz;
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index ec464a6b95fe..0cf60a628814 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -218,8 +218,13 @@ __BUILD_IOPORT_STRING(w, u16)
218__BUILD_IOPORT_STRING(l, u32) 218__BUILD_IOPORT_STRING(l, u32)
219__BUILD_IOPORT_STRING(q, u64) 219__BUILD_IOPORT_STRING(q, u64)
220 220
221#else /* !CONFIG_HAS_IOPORT */
222
223#include <asm/io_noioport.h>
224
221#endif 225#endif
222 226
227
223#define IO_SPACE_LIMIT 0xffffffff 228#define IO_SPACE_LIMIT 0xffffffff
224 229
225/* synco on SH-4A, otherwise a nop */ 230/* synco on SH-4A, otherwise a nop */
diff --git a/arch/sh/include/asm/io_noioport.h b/arch/sh/include/asm/io_noioport.h
new file mode 100644
index 000000000000..e136d28d1d2e
--- /dev/null
+++ b/arch/sh/include/asm/io_noioport.h
@@ -0,0 +1,41 @@
1#ifndef __ASM_SH_IO_NOIOPORT_H
2#define __ASM_SH_IO_NOIOPORT_H
3
4static inline u8 inb(unsigned long addr)
5{
6 BUG();
7 return -1;
8}
9
10static inline u16 inw(unsigned long addr)
11{
12 BUG();
13 return -1;
14}
15
16static inline u32 inl(unsigned long addr)
17{
18 BUG();
19 return -1;
20}
21
22#define outb(x, y) BUG()
23#define outw(x, y) BUG()
24#define outl(x, y) BUG()
25
26#define inb_p(addr) inb(addr)
27#define inw_p(addr) inw(addr)
28#define inl_p(addr) inl(addr)
29#define outb_p(x, addr) outb((x), (addr))
30#define outw_p(x, addr) outw((x), (addr))
31#define outl_p(x, addr) outl((x), (addr))
32
33#define insb(a, b, c) BUG()
34#define insw(a, b, c) BUG()
35#define insl(a, b, c) BUG()
36
37#define outsb(a, b, c) BUG()
38#define outsw(a, b, c) BUG()
39#define outsl(a, b, c) BUG()
40
41#endif /* __ASM_SH_IO_NOIOPORT_H */
diff --git a/arch/sh/include/asm/irq.h b/arch/sh/include/asm/irq.h
index 2a62017eb275..0e4f532e4737 100644
--- a/arch/sh/include/asm/irq.h
+++ b/arch/sh/include/asm/irq.h
@@ -5,12 +5,15 @@
5#include <asm/machvec.h> 5#include <asm/machvec.h>
6 6
7/* 7/*
8 * A sane default based on a reasonable vector table size, platforms are 8 * Only legacy non-sparseirq platforms have to set a reasonably sane
9 * advised to cap this at the hard limit that they're interested in 9 * value here. sparseirq platforms allocate their irq_descs on the fly,
10 * through the machvec. 10 * so will expand automatically based on the number of registered IRQs.
11 */ 11 */
12#define NR_IRQS 512 12#ifdef CONFIG_SPARSE_IRQ
13#define NR_IRQS_LEGACY 8 /* Legacy external IRQ0-7 */ 13# define NR_IRQS 8
14#else
15# define NR_IRQS 512
16#endif
14 17
15/* 18/*
16 * This is a special IRQ number for indicating that no IRQ has been 19 * This is a special IRQ number for indicating that no IRQ has been
diff --git a/arch/sh/include/asm/kdebug.h b/arch/sh/include/asm/kdebug.h
index 5f6d2e9ccb7c..a6201f10c273 100644
--- a/arch/sh/include/asm/kdebug.h
+++ b/arch/sh/include/asm/kdebug.h
@@ -10,4 +10,6 @@ enum die_val {
10 DIE_SSTEP, 10 DIE_SSTEP,
11}; 11};
12 12
13extern void printk_address(unsigned long address, int reliable);
14
13#endif /* __ASM_SH_KDEBUG_H */ 15#endif /* __ASM_SH_KDEBUG_H */
diff --git a/arch/sh/include/asm/kgdb.h b/arch/sh/include/asm/kgdb.h
index f3613952d1ae..9e7d2d1b03e0 100644
--- a/arch/sh/include/asm/kgdb.h
+++ b/arch/sh/include/asm/kgdb.h
@@ -4,18 +4,6 @@
4#include <asm/cacheflush.h> 4#include <asm/cacheflush.h>
5#include <asm/ptrace.h> 5#include <asm/ptrace.h>
6 6
7/* Same as pt_regs but has vbr in place of syscall_nr */
8struct kgdb_regs {
9 unsigned long regs[16];
10 unsigned long pc;
11 unsigned long pr;
12 unsigned long sr;
13 unsigned long gbr;
14 unsigned long mach;
15 unsigned long macl;
16 unsigned long vbr;
17};
18
19enum regnames { 7enum regnames {
20 GDB_R0, GDB_R1, GDB_R2, GDB_R3, GDB_R4, GDB_R5, GDB_R6, GDB_R7, 8 GDB_R0, GDB_R1, GDB_R2, GDB_R3, GDB_R4, GDB_R5, GDB_R6, GDB_R7,
21 GDB_R8, GDB_R9, GDB_R10, GDB_R11, GDB_R12, GDB_R13, GDB_R14, GDB_R15, 9 GDB_R8, GDB_R9, GDB_R10, GDB_R11, GDB_R12, GDB_R13, GDB_R14, GDB_R15,
@@ -23,17 +11,27 @@ enum regnames {
23 GDB_PC, GDB_PR, GDB_SR, GDB_GBR, GDB_MACH, GDB_MACL, GDB_VBR, 11 GDB_PC, GDB_PR, GDB_SR, GDB_GBR, GDB_MACH, GDB_MACL, GDB_VBR,
24}; 12};
25 13
26#define NUMREGBYTES ((GDB_VBR + 1) * 4) 14#define _GP_REGS 16
15#define _EXTRA_REGS 7
16#define GDB_SIZEOF_REG sizeof(u32)
17
18#define DBG_MAX_REG_NUM (_GP_REGS + _EXTRA_REGS)
19#define NUMREGBYTES (DBG_MAX_REG_NUM * sizeof(GDB_SIZEOF_REG))
27 20
28static inline void arch_kgdb_breakpoint(void) 21static inline void arch_kgdb_breakpoint(void)
29{ 22{
30 __asm__ __volatile__ ("trapa #0x3c\n"); 23 __asm__ __volatile__ ("trapa #0x3c\n");
31} 24}
32 25
33#define BUFMAX 2048
34
35#define CACHE_FLUSH_IS_SAFE 1
36#define BREAK_INSTR_SIZE 2 26#define BREAK_INSTR_SIZE 2
27#define BUFMAX 2048
28
29#ifdef CONFIG_SMP
30# define CACHE_FLUSH_IS_SAFE 0
31#else
32# define CACHE_FLUSH_IS_SAFE 1
33#endif
34
37#define GDB_ADJUSTS_BREAK_OFFSET 35#define GDB_ADJUSTS_BREAK_OFFSET
38 36
39#endif /* __ASM_SH_KGDB_H */ 37#endif /* __ASM_SH_KGDB_H */
diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h
index 57c5c3d0f39f..eb9c20d971dd 100644
--- a/arch/sh/include/asm/machvec.h
+++ b/arch/sh/include/asm/machvec.h
@@ -17,7 +17,6 @@
17struct sh_machine_vector { 17struct sh_machine_vector {
18 void (*mv_setup)(char **cmdline_p); 18 void (*mv_setup)(char **cmdline_p);
19 const char *mv_name; 19 const char *mv_name;
20 int mv_nr_irqs;
21 20
22 int (*mv_irq_demux)(int irq); 21 int (*mv_irq_demux)(int irq);
23 void (*mv_init_irq)(void); 22 void (*mv_init_irq)(void);
diff --git a/arch/sh/include/asm/pgtable_64.h b/arch/sh/include/asm/pgtable_64.h
index 42cb9dd52161..dda8c82601b9 100644
--- a/arch/sh/include/asm/pgtable_64.h
+++ b/arch/sh/include/asm/pgtable_64.h
@@ -87,9 +87,6 @@ static __inline__ void set_pte(pte_t *pteptr, pte_t pteval)
87#define pte_unmap(pte) do { } while (0) 87#define pte_unmap(pte) do { } while (0)
88 88
89#ifndef __ASSEMBLY__ 89#ifndef __ASSEMBLY__
90#define IOBASE_VADDR 0xff000000
91#define IOBASE_END 0xffffffff
92
93/* 90/*
94 * PTEL coherent flags. 91 * PTEL coherent flags.
95 * See Chapter 17 ST50 CPU Core Volume 1, Architecture. 92 * See Chapter 17 ST50 CPU Core Volume 1, Architecture.
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 6dbc1be28a0f..3d14aeaef57c 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -18,7 +18,8 @@ enum cpu_type {
18 CPU_SH7619, 18 CPU_SH7619,
19 19
20 /* SH-2A types */ 20 /* SH-2A types */
21 CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG, 21 CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_SH7269,
22 CPU_MXG,
22 23
23 /* SH-3 types */ 24 /* SH-3 types */
24 CPU_SH7705, CPU_SH7706, CPU_SH7707, 25 CPU_SH7705, CPU_SH7706, CPU_SH7707,
@@ -32,7 +33,7 @@ enum cpu_type {
32 33
33 /* SH-4A types */ 34 /* SH-4A types */
34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, 35 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
35 CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3, 36 CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SH7734, CPU_SHX3,
36 37
37 /* SH4AL-DSP types */ 38 /* SH4AL-DSP types */
38 CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372, 39 CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372,
diff --git a/arch/sh/include/asm/processor_64.h b/arch/sh/include/asm/processor_64.h
index e25c4c7d6b63..740e26876596 100644
--- a/arch/sh/include/asm/processor_64.h
+++ b/arch/sh/include/asm/processor_64.h
@@ -121,7 +121,6 @@ struct thread_struct {
121 NULL for a kernel thread. */ 121 NULL for a kernel thread. */
122 struct pt_regs *uregs; 122 struct pt_regs *uregs;
123 123
124 unsigned long trap_no, error_code;
125 unsigned long address; 124 unsigned long address;
126 /* Hardware debugging registers may come here */ 125 /* Hardware debugging registers may come here */
127 126
@@ -138,8 +137,6 @@ struct thread_struct {
138 .pc = 0, \ 137 .pc = 0, \
139 .kregs = &fake_swapper_regs, \ 138 .kregs = &fake_swapper_regs, \
140 .uregs = NULL, \ 139 .uregs = NULL, \
141 .trap_no = 0, \
142 .error_code = 0, \
143 .address = 0, \ 140 .address = 0, \
144 .flags = 0, \ 141 .flags = 0, \
145} 142}
diff --git a/arch/sh/include/asm/stackprotector.h b/arch/sh/include/asm/stackprotector.h
new file mode 100644
index 000000000000..d9df3a76847c
--- /dev/null
+++ b/arch/sh/include/asm/stackprotector.h
@@ -0,0 +1,27 @@
1#ifndef __ASM_SH_STACKPROTECTOR_H
2#define __ASM_SH_STACKPROTECTOR_H
3
4#include <linux/random.h>
5#include <linux/version.h>
6
7extern unsigned long __stack_chk_guard;
8
9/*
10 * Initialize the stackprotector canary value.
11 *
12 * NOTE: this must only be called from functions that never return,
13 * and it must always be inlined.
14 */
15static __always_inline void boot_init_stack_canary(void)
16{
17 unsigned long canary;
18
19 /* Try to get a semi random initial value. */
20 get_random_bytes(&canary, sizeof(canary));
21 canary ^= LINUX_VERSION_CODE;
22
23 current->stack_canary = canary;
24 __stack_chk_guard = current->stack_canary;
25}
26
27#endif /* __ASM_SH_STACKPROTECTOR_H */
diff --git a/arch/sh/include/asm/thread_info.h b/arch/sh/include/asm/thread_info.h
index b6902061d4dc..0c04ffc4f12c 100644
--- a/arch/sh/include/asm/thread_info.h
+++ b/arch/sh/include/asm/thread_info.h
@@ -10,8 +10,18 @@
10 * - Incorporating suggestions made by Linus Torvalds and Dave Miller 10 * - Incorporating suggestions made by Linus Torvalds and Dave Miller
11 */ 11 */
12#ifdef __KERNEL__ 12#ifdef __KERNEL__
13
13#include <asm/page.h> 14#include <asm/page.h>
14 15
16/*
17 * Page fault error code bits
18 */
19#define FAULT_CODE_WRITE (1 << 0) /* write access */
20#define FAULT_CODE_INITIAL (1 << 1) /* initial page write */
21#define FAULT_CODE_ITLB (1 << 2) /* ITLB miss */
22#define FAULT_CODE_PROT (1 << 3) /* protection fault */
23#define FAULT_CODE_USER (1 << 4) /* user-mode access */
24
15#ifndef __ASSEMBLY__ 25#ifndef __ASSEMBLY__
16#include <asm/processor.h> 26#include <asm/processor.h>
17 27
@@ -98,10 +108,13 @@ extern void init_thread_xstate(void);
98#endif /* __ASSEMBLY__ */ 108#endif /* __ASSEMBLY__ */
99 109
100/* 110/*
101 * thread information flags 111 * Thread information flags
102 * - these are process state flags that various assembly files may need to access 112 *
103 * - pending work-to-be-done flags are in LSW 113 * - Limited to 24 bits, upper byte used for fault code encoding.
104 * - other flags in MSW 114 *
115 * - _TIF_ALLWORK_MASK and _TIF_WORK_MASK need to fit within 2 bytes, or
116 * we blow the tst immediate size constraints and need to fix up
117 * arch/sh/kernel/entry-common.S.
105 */ 118 */
106#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ 119#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
107#define TIF_SIGPENDING 1 /* signal pending */ 120#define TIF_SIGPENDING 1 /* signal pending */
@@ -124,12 +137,6 @@ extern void init_thread_xstate(void);
124#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT) 137#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT)
125#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) 138#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG)
126 139
127/*
128 * _TIF_ALLWORK_MASK and _TIF_WORK_MASK need to fit within 2 bytes, or we
129 * blow the tst immediate size constraints and need to fix up
130 * arch/sh/kernel/entry-common.S.
131 */
132
133/* work to do in syscall trace */ 140/* work to do in syscall trace */
134#define _TIF_WORK_SYSCALL_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \ 141#define _TIF_WORK_SYSCALL_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \
135 _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \ 142 _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
@@ -156,6 +163,7 @@ extern void init_thread_xstate(void);
156#define TS_USEDFPU 0x0002 /* FPU used by this task this quantum */ 163#define TS_USEDFPU 0x0002 /* FPU used by this task this quantum */
157 164
158#ifndef __ASSEMBLY__ 165#ifndef __ASSEMBLY__
166
159#define HAVE_SET_RESTORE_SIGMASK 1 167#define HAVE_SET_RESTORE_SIGMASK 1
160static inline void set_restore_sigmask(void) 168static inline void set_restore_sigmask(void)
161{ 169{
@@ -163,6 +171,24 @@ static inline void set_restore_sigmask(void)
163 ti->status |= TS_RESTORE_SIGMASK; 171 ti->status |= TS_RESTORE_SIGMASK;
164 set_bit(TIF_SIGPENDING, (unsigned long *)&ti->flags); 172 set_bit(TIF_SIGPENDING, (unsigned long *)&ti->flags);
165} 173}
174
175#define TI_FLAG_FAULT_CODE_SHIFT 24
176
177/*
178 * Additional thread flag encoding
179 */
180static inline void set_thread_fault_code(unsigned int val)
181{
182 struct thread_info *ti = current_thread_info();
183 ti->flags = (ti->flags & (~0 >> (32 - TI_FLAG_FAULT_CODE_SHIFT)))
184 | (val << TI_FLAG_FAULT_CODE_SHIFT);
185}
186
187static inline unsigned int get_thread_fault_code(void)
188{
189 struct thread_info *ti = current_thread_info();
190 return ti->flags >> TI_FLAG_FAULT_CODE_SHIFT;
191}
166#endif /* !__ASSEMBLY__ */ 192#endif /* !__ASSEMBLY__ */
167 193
168#endif /* __KERNEL__ */ 194#endif /* __KERNEL__ */
diff --git a/arch/sh/include/asm/traps_64.h b/arch/sh/include/asm/traps_64.h
index c52d7f9a06c1..ef5eff919449 100644
--- a/arch/sh/include/asm/traps_64.h
+++ b/arch/sh/include/asm/traps_64.h
@@ -10,8 +10,22 @@
10#ifndef __ASM_SH_TRAPS_64_H 10#ifndef __ASM_SH_TRAPS_64_H
11#define __ASM_SH_TRAPS_64_H 11#define __ASM_SH_TRAPS_64_H
12 12
13#include <cpu/registers.h>
14
13extern void phys_stext(void); 15extern void phys_stext(void);
14 16
17#define lookup_exception_vector() \
18({ \
19 unsigned long _vec; \
20 \
21 __asm__ __volatile__ ( \
22 "getcon " __EXPEVT ", %0\n\t" \
23 : "=r" (_vec) \
24 ); \
25 \
26 _vec; \
27})
28
15static inline void trigger_address_error(void) 29static inline void trigger_address_error(void)
16{ 30{
17 phys_stext(); 31 phys_stext();
diff --git a/arch/sh/include/cpu-sh2/cpu/dma.h b/arch/sh/include/cpu-sh2/cpu/dma.h
deleted file mode 100644
index d66b43cdc637..000000000000
--- a/arch/sh/include/cpu-sh2/cpu/dma.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * Definitions for the SH-2 DMAC.
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_DMA_H
11#define __ASM_CPU_SH2_DMA_H
12
13#define SH_MAX_DMA_CHANNELS 2
14
15#define SAR ((unsigned long[]){ 0xffffff80, 0xffffff90 })
16#define DAR ((unsigned long[]){ 0xffffff84, 0xffffff94 })
17#define DMATCR ((unsigned long[]){ 0xffffff88, 0xffffff98 })
18#define CHCR ((unsigned long[]){ 0xfffffffc, 0xffffff9c })
19
20#define DMAOR 0xffffffb0
21
22#endif /* __ASM_CPU_SH2_DMA_H */
23
diff --git a/arch/sh/include/cpu-sh2a/cpu/dma.h b/arch/sh/include/cpu-sh2a/cpu/dma.h
deleted file mode 100644
index 27a13ef4fdfc..000000000000
--- a/arch/sh/include/cpu-sh2a/cpu/dma.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <cpu-sh2/cpu/dma.h>
diff --git a/arch/sh/include/cpu-sh2a/cpu/sh7264.h b/arch/sh/include/cpu-sh2a/cpu/sh7264.h
new file mode 100644
index 000000000000..4d1ef6d74bd6
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/sh7264.h
@@ -0,0 +1,176 @@
1#ifndef __ASM_SH7264_H__
2#define __ASM_SH7264_H__
3
4enum {
5 /* Port A */
6 GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
7
8 /* Port B */
9 GPIO_PB22, GPIO_PB21, GPIO_PB20,
10 GPIO_PB19, GPIO_PB18, GPIO_PB17, GPIO_PB16,
11 GPIO_PB15, GPIO_PB14, GPIO_PB13, GPIO_PB12,
12 GPIO_PB11, GPIO_PB10, GPIO_PB9, GPIO_PB8,
13 GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
14 GPIO_PB3, GPIO_PB2, GPIO_PB1,
15
16 /* Port C */
17 GPIO_PC10, GPIO_PC9, GPIO_PC8,
18 GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
19 GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
20
21 /* Port D */
22 GPIO_PD15, GPIO_PD14, GPIO_PD13, GPIO_PD12,
23 GPIO_PD11, GPIO_PD10, GPIO_PD9, GPIO_PD8,
24 GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
25 GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
26
27 /* Port E */
28 GPIO_PE5, GPIO_PE4,
29 GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0,
30
31 /* Port F */
32 GPIO_PF12,
33 GPIO_PF11, GPIO_PF10, GPIO_PF9, GPIO_PF8,
34 GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
35 GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
36
37 /* Port G */
38 GPIO_PG24,
39 GPIO_PG23, GPIO_PG22, GPIO_PG21, GPIO_PG20,
40 GPIO_PG19, GPIO_PG18, GPIO_PG17, GPIO_PG16,
41 GPIO_PG15, GPIO_PG14, GPIO_PG13, GPIO_PG12,
42 GPIO_PG11, GPIO_PG10, GPIO_PG9, GPIO_PG8,
43 GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
44 GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
45
46 /* Port H */
47 GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
48 GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
49
50 /* Port I - not on device */
51
52 /* Port J */
53 GPIO_PJ11, GPIO_PJ10, GPIO_PJ9, GPIO_PJ8,
54 GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
55 GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
56
57 /* Port K */
58 GPIO_PK11, GPIO_PK10, GPIO_PK9, GPIO_PK8,
59 GPIO_PK7, GPIO_PK6, GPIO_PK5, GPIO_PK4,
60 GPIO_PK3, GPIO_PK2, GPIO_PK1, GPIO_PK0,
61
62 /* INTC: IRQ and PINT on PB/PD/PE */
63 GPIO_FN_PINT7_PG, GPIO_FN_PINT6_PG, GPIO_FN_PINT5_PG, GPIO_FN_PINT4_PG,
64 GPIO_FN_PINT3_PG, GPIO_FN_PINT2_PG, GPIO_FN_PINT1_PG,
65
66 GPIO_FN_IRQ7_PC, GPIO_FN_IRQ6_PC, GPIO_FN_IRQ5_PC, GPIO_FN_IRQ4_PC,
67 GPIO_FN_IRQ3_PG, GPIO_FN_IRQ2_PG, GPIO_FN_IRQ1_PJ, GPIO_FN_IRQ0_PJ,
68 GPIO_FN_IRQ3_PE, GPIO_FN_IRQ2_PE, GPIO_FN_IRQ1_PE, GPIO_FN_IRQ0_PE,
69
70 /* WDT */
71 GPIO_FN_WDTOVF,
72
73 /* CAN */
74 GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1,
75 GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1,
76
77 /* DMAC */
78 GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0,
79 GPIO_FN_TEND1, GPIO_FN_DACK1, GPIO_FN_DREQ1,
80
81 /* ADC */
82 GPIO_FN_ADTRG,
83
84 /* BSC */
85
86 GPIO_FN_A25, GPIO_FN_A24,
87 GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20,
88 GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16,
89 GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12,
90 GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8,
91 GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4,
92 GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0,
93 GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
94 GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
95 GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
96 GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
97
98 GPIO_FN_BS,
99 GPIO_FN_CS4, GPIO_FN_CS3, GPIO_FN_CS2, GPIO_FN_CS1, GPIO_FN_CS0,
100 GPIO_FN_CS6CE1B, GPIO_FN_CS5CE1A,
101 GPIO_FN_CE2A, GPIO_FN_CE2B,
102 GPIO_FN_RD, GPIO_FN_RDWR,
103 GPIO_FN_ICIOWRAH, GPIO_FN_ICIORD,
104 GPIO_FN_WE1DQMUWE, GPIO_FN_WE0DQML,
105 GPIO_FN_RAS, GPIO_FN_CAS, GPIO_FN_CKE,
106 GPIO_FN_WAIT, GPIO_FN_BREQ, GPIO_FN_BACK,
107 GPIO_FN_IOIS16,
108
109 /* TMU */
110 GPIO_FN_TIOC4D, GPIO_FN_TIOC4C, GPIO_FN_TIOC4B, GPIO_FN_TIOC4A,
111 GPIO_FN_TIOC3D, GPIO_FN_TIOC3C, GPIO_FN_TIOC3B, GPIO_FN_TIOC3A,
112 GPIO_FN_TIOC2B, GPIO_FN_TIOC1B, GPIO_FN_TIOC2A, GPIO_FN_TIOC1A,
113 GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
114 GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,
115
116 /* SSU */
117 GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
118 GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
119 GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
120 GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
121
122 /* SCIF */
123 GPIO_FN_SCK0, GPIO_FN_SCK1, GPIO_FN_SCK2, GPIO_FN_SCK3,
124 GPIO_FN_RXD0, GPIO_FN_RXD1, GPIO_FN_RXD2, GPIO_FN_RXD3,
125 GPIO_FN_TXD0, GPIO_FN_TXD1, GPIO_FN_TXD2, GPIO_FN_TXD3,
126 GPIO_FN_RXD4, GPIO_FN_RXD5, GPIO_FN_RXD6, GPIO_FN_RXD7,
127 GPIO_FN_TXD4, GPIO_FN_TXD5, GPIO_FN_TXD6, GPIO_FN_TXD7,
128 GPIO_FN_RTS1, GPIO_FN_RTS3, GPIO_FN_CTS1, GPIO_FN_CTS3,
129
130 /* RSPI */
131 GPIO_FN_RSPCK0, GPIO_FN_MOSI0,
132 GPIO_FN_MISO0_PF12, GPIO_FN_MISO1,
133 GPIO_FN_SSL00,
134 GPIO_FN_RSPCK1, GPIO_FN_MOSI1,
135 GPIO_FN_MISO1_PG19, GPIO_FN_SSL10,
136
137 /* IIC3 */
138 GPIO_FN_SCL0, GPIO_FN_SCL1, GPIO_FN_SCL2,
139 GPIO_FN_SDA2, GPIO_FN_SDA1, GPIO_FN_SDA0,
140
141 /* SSI */
142 GPIO_FN_SSISCK0, GPIO_FN_SSIWS0, GPIO_FN_SSITXD0, GPIO_FN_SSIRXD0,
143 GPIO_FN_SSIWS1, GPIO_FN_SSIWS2, GPIO_FN_SSIWS3,
144 GPIO_FN_SSISCK1, GPIO_FN_SSISCK2, GPIO_FN_SSISCK3,
145 GPIO_FN_SSIDATA1, GPIO_FN_SSIDATA2, GPIO_FN_SSIDATA3,
146 GPIO_FN_AUDIO_CLK,
147
148 /* SIOF */
149 GPIO_FN_SIOFTXD, GPIO_FN_SIOFRXD, GPIO_FN_SIOFSYNC, GPIO_FN_SIOFSCK,
150
151 /* SPDIF */
152 GPIO_FN_SPDIF_IN,
153 GPIO_FN_SPDIF_OUT,
154
155 /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
156 GPIO_FN_FCE,
157 GPIO_FN_FRB,
158
159 /* VDC3 */
160 GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC,
161 GPIO_FN_DV_DATA7, GPIO_FN_DV_DATA6, GPIO_FN_DV_DATA5, GPIO_FN_DV_DATA4,
162 GPIO_FN_DV_DATA3, GPIO_FN_DV_DATA2, GPIO_FN_DV_DATA1, GPIO_FN_DV_DATA0,
163 GPIO_FN_LCD_CLK, GPIO_FN_LCD_EXTCLK,
164 GPIO_FN_LCD_VSYNC, GPIO_FN_LCD_HSYNC, GPIO_FN_LCD_DE,
165 GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14,
166 GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12,
167 GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10,
168 GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8,
169 GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6,
170 GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4,
171 GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2,
172 GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0,
173 GPIO_FN_LCD_M_DISP,
174};
175
176#endif /* __ASM_SH7264_H__ */
diff --git a/arch/sh/include/cpu-sh2a/cpu/sh7269.h b/arch/sh/include/cpu-sh2a/cpu/sh7269.h
new file mode 100644
index 000000000000..48d14498e774
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/sh7269.h
@@ -0,0 +1,201 @@
1#ifndef __ASM_SH7269_H__
2#define __ASM_SH7269_H__
3
4enum {
5 /* Port A */
6 GPIO_PA1, GPIO_PA0,
7
8 /* Port B */
9 GPIO_PB22, GPIO_PB21, GPIO_PB20,
10 GPIO_PB19, GPIO_PB18, GPIO_PB17, GPIO_PB16,
11 GPIO_PB15, GPIO_PB14, GPIO_PB13, GPIO_PB12,
12 GPIO_PB11, GPIO_PB10, GPIO_PB9, GPIO_PB8,
13 GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
14 GPIO_PB3, GPIO_PB2, GPIO_PB1,
15
16 /* Port C */
17 GPIO_PC8,
18 GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
19 GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
20
21 /* Port D */
22 GPIO_PD15, GPIO_PD14, GPIO_PD13, GPIO_PD12,
23 GPIO_PD11, GPIO_PD10, GPIO_PD9, GPIO_PD8,
24 GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
25 GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
26
27 /* Port E */
28 GPIO_PE7, GPIO_PE6, GPIO_PE5, GPIO_PE4,
29 GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0,
30
31 /* Port F */
32 GPIO_PF23, GPIO_PF22, GPIO_PF21, GPIO_PF20,
33 GPIO_PF19, GPIO_PF18, GPIO_PF17, GPIO_PF16,
34 GPIO_PF15, GPIO_PF14, GPIO_PF13, GPIO_PF12,
35 GPIO_PF11, GPIO_PF10, GPIO_PF9, GPIO_PF8,
36 GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
37 GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
38
39 /* Port G */
40 GPIO_PG27, GPIO_PG26, GPIO_PG25, GPIO_PG24,
41 GPIO_PG23, GPIO_PG22, GPIO_PG21, GPIO_PG20,
42 GPIO_PG19, GPIO_PG18, GPIO_PG17, GPIO_PG16,
43 GPIO_PG15, GPIO_PG14, GPIO_PG13, GPIO_PG12,
44 GPIO_PG11, GPIO_PG10, GPIO_PG9, GPIO_PG8,
45 GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
46 GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
47
48 /* Port H */
49 GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
50 GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
51
52 /* Port I - not on device */
53
54 /* Port J */
55 GPIO_PJ31, GPIO_PJ30, GPIO_PJ29, GPIO_PJ28,
56 GPIO_PJ27, GPIO_PJ26, GPIO_PJ25, GPIO_PJ24,
57 GPIO_PJ23, GPIO_PJ22, GPIO_PJ21, GPIO_PJ20,
58 GPIO_PJ19, GPIO_PJ18, GPIO_PJ17, GPIO_PJ16,
59 GPIO_PJ15, GPIO_PJ14, GPIO_PJ13, GPIO_PJ12,
60 GPIO_PJ11, GPIO_PJ10, GPIO_PJ9, GPIO_PJ8,
61 GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
62 GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
63
64 /* INTC: IRQ and PINT */
65 GPIO_FN_IRQ7_PG, GPIO_FN_IRQ6_PG, GPIO_FN_IRQ5_PG, GPIO_FN_IRQ4_PG,
66 GPIO_FN_IRQ3_PG, GPIO_FN_IRQ2_PG, GPIO_FN_IRQ1_PG, GPIO_FN_IRQ0_PG,
67 GPIO_FN_IRQ7_PF, GPIO_FN_IRQ6_PF, GPIO_FN_IRQ5_PF, GPIO_FN_IRQ4_PF,
68 GPIO_FN_IRQ3_PJ, GPIO_FN_IRQ2_PJ, GPIO_FN_IRQ1_PJ, GPIO_FN_IRQ0_PJ,
69 GPIO_FN_IRQ1_PC, GPIO_FN_IRQ0_PC,
70
71 GPIO_FN_PINT7_PG, GPIO_FN_PINT6_PG, GPIO_FN_PINT5_PG, GPIO_FN_PINT4_PG,
72 GPIO_FN_PINT3_PG, GPIO_FN_PINT2_PG, GPIO_FN_PINT1_PG, GPIO_FN_PINT0_PG,
73 GPIO_FN_PINT7_PH, GPIO_FN_PINT6_PH, GPIO_FN_PINT5_PH, GPIO_FN_PINT4_PH,
74 GPIO_FN_PINT3_PH, GPIO_FN_PINT2_PH, GPIO_FN_PINT1_PH, GPIO_FN_PINT0_PH,
75 GPIO_FN_PINT7_PJ, GPIO_FN_PINT6_PJ, GPIO_FN_PINT5_PJ, GPIO_FN_PINT4_PJ,
76 GPIO_FN_PINT3_PJ, GPIO_FN_PINT2_PJ, GPIO_FN_PINT1_PJ, GPIO_FN_PINT0_PJ,
77
78 /* WDT */
79 GPIO_FN_WDTOVF,
80
81 /* CAN */
82 GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1,
83 GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, GPIO_FN_CRX0_CRX1_CRX2,
84
85 /* DMAC */
86 GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0,
87 GPIO_FN_TEND1, GPIO_FN_DACK1, GPIO_FN_DREQ1,
88
89 /* ADC */
90 GPIO_FN_ADTRG,
91
92 /* BSC */
93 GPIO_FN_A25, GPIO_FN_A24,
94 GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20,
95 GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16,
96 GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12,
97 GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8,
98 GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4,
99 GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0,
100 GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
101 GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
102 GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
103 GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
104
105 GPIO_FN_BS,
106 GPIO_FN_CS4, GPIO_FN_CS3, GPIO_FN_CS2, GPIO_FN_CS1, GPIO_FN_CS0,
107 GPIO_FN_CS5CE1A,
108 GPIO_FN_CE2A, GPIO_FN_CE2B,
109 GPIO_FN_RD, GPIO_FN_RDWR,
110 GPIO_FN_WE3ICIOWRAHDQMUU, GPIO_FN_WE2ICIORDDQMUL,
111 GPIO_FN_WE1DQMUWE, GPIO_FN_WE0DQML,
112 GPIO_FN_RAS, GPIO_FN_CAS, GPIO_FN_CKE,
113 GPIO_FN_WAIT, GPIO_FN_BREQ, GPIO_FN_BACK,
114 GPIO_FN_IOIS16,
115
116 /* TMU */
117 GPIO_FN_TIOC4D, GPIO_FN_TIOC4C, GPIO_FN_TIOC4B, GPIO_FN_TIOC4A,
118 GPIO_FN_TIOC3D, GPIO_FN_TIOC3C, GPIO_FN_TIOC3B, GPIO_FN_TIOC3A,
119 GPIO_FN_TIOC2B, GPIO_FN_TIOC1B, GPIO_FN_TIOC2A, GPIO_FN_TIOC1A,
120 GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
121 GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,
122
123 /* SSU */
124 GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
125 GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
126 GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
127 GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
128
129 /* SCIF */
130 GPIO_FN_SCK0, GPIO_FN_RXD0, GPIO_FN_TXD0,
131 GPIO_FN_SCK1, GPIO_FN_RXD1, GPIO_FN_TXD1, GPIO_FN_RTS1, GPIO_FN_CTS1,
132 GPIO_FN_SCK2, GPIO_FN_RXD2, GPIO_FN_TXD2,
133 GPIO_FN_SCK3, GPIO_FN_RXD3, GPIO_FN_TXD3,
134 GPIO_FN_SCK4, GPIO_FN_RXD4, GPIO_FN_TXD4,
135 GPIO_FN_SCK5, GPIO_FN_RXD5, GPIO_FN_TXD5, GPIO_FN_RTS5, GPIO_FN_CTS5,
136 GPIO_FN_SCK6, GPIO_FN_RXD6, GPIO_FN_TXD6,
137 GPIO_FN_SCK7, GPIO_FN_RXD7, GPIO_FN_TXD7, GPIO_FN_RTS7, GPIO_FN_CTS7,
138
139 /* RSPI */
140 GPIO_FN_MISO0_PJ19, GPIO_FN_MISO0_PB20,
141 GPIO_FN_MOSI0_PJ18, GPIO_FN_MOSI0_PB19,
142 GPIO_FN_SSL00_PJ17, GPIO_FN_SSL00_PB18,
143 GPIO_FN_RSPCK0_PJ16, GPIO_FN_RSPCK0_PB17,
144 GPIO_FN_RSPCK1, GPIO_FN_MOSI1,
145 GPIO_FN_MISO1, GPIO_FN_SSL10,
146
147 /* IIC3 */
148 GPIO_FN_SCL0, GPIO_FN_SCL1, GPIO_FN_SCL2,
149 GPIO_FN_SDA2, GPIO_FN_SDA1, GPIO_FN_SDA0,
150
151 /* SSI */
152 GPIO_FN_SSISCK0, GPIO_FN_SSIWS0, GPIO_FN_SSITXD0, GPIO_FN_SSIRXD0,
153 GPIO_FN_SSIWS1, GPIO_FN_SSIWS2, GPIO_FN_SSIWS3,
154 GPIO_FN_SSISCK1, GPIO_FN_SSISCK2, GPIO_FN_SSISCK3,
155 GPIO_FN_SSIDATA1, GPIO_FN_SSIDATA2, GPIO_FN_SSIDATA3,
156 GPIO_FN_AUDIO_CLK,
157 GPIO_FN_AUDIO_XOUT,
158
159 /* SIOF */
160 GPIO_FN_SIOFTXD, GPIO_FN_SIOFRXD, GPIO_FN_SIOFSYNC, GPIO_FN_SIOFSCK,
161
162 /* SPDIF */
163 GPIO_FN_SPDIF_IN,
164 GPIO_FN_SPDIF_OUT,
165
166 /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
167 GPIO_FN_FCE,
168 GPIO_FN_FRB,
169
170 /* VDC */
171 GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC,
172 GPIO_FN_DV_DATA23, GPIO_FN_DV_DATA22,
173 GPIO_FN_DV_DATA21, GPIO_FN_DV_DATA20,
174 GPIO_FN_DV_DATA19, GPIO_FN_DV_DATA18,
175 GPIO_FN_DV_DATA17, GPIO_FN_DV_DATA16,
176 GPIO_FN_DV_DATA15, GPIO_FN_DV_DATA14,
177 GPIO_FN_DV_DATA13, GPIO_FN_DV_DATA12,
178 GPIO_FN_DV_DATA11, GPIO_FN_DV_DATA10,
179 GPIO_FN_DV_DATA9, GPIO_FN_DV_DATA8,
180 GPIO_FN_DV_DATA7, GPIO_FN_DV_DATA6,
181 GPIO_FN_DV_DATA5, GPIO_FN_DV_DATA4,
182 GPIO_FN_DV_DATA3, GPIO_FN_DV_DATA2,
183 GPIO_FN_DV_DATA1, GPIO_FN_DV_DATA0,
184 GPIO_FN_LCD_CLK, GPIO_FN_LCD_EXTCLK,
185 GPIO_FN_LCD_VSYNC, GPIO_FN_LCD_HSYNC, GPIO_FN_LCD_DE,
186 GPIO_FN_LCD_DATA23, GPIO_FN_LCD_DATA22,
187 GPIO_FN_LCD_DATA21, GPIO_FN_LCD_DATA20,
188 GPIO_FN_LCD_DATA19, GPIO_FN_LCD_DATA18,
189 GPIO_FN_LCD_DATA17, GPIO_FN_LCD_DATA16,
190 GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14,
191 GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12,
192 GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10,
193 GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8,
194 GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6,
195 GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4,
196 GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2,
197 GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0,
198 GPIO_FN_LCD_M_DISP,
199};
200
201#endif /* __ASM_SH7269_H__ */
diff --git a/arch/sh/include/cpu-sh3/cpu/dma.h b/arch/sh/include/cpu-sh3/cpu/dma.h
index 24e28b91c9d5..bccb4144a5e3 100644
--- a/arch/sh/include/cpu-sh3/cpu/dma.h
+++ b/arch/sh/include/cpu-sh3/cpu/dma.h
@@ -1,6 +1,8 @@
1#ifndef __ASM_CPU_SH3_DMA_H 1#ifndef __ASM_CPU_SH3_DMA_H
2#define __ASM_CPU_SH3_DMA_H 2#define __ASM_CPU_SH3_DMA_H
3 3
4#include <linux/sh_intc.h>
5
4#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 6#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
5 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 7 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7710) || \ 8 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
@@ -10,14 +12,7 @@
10#define SH_DMAC_BASE0 0xa4000020 12#define SH_DMAC_BASE0 0xa4000020
11#endif 13#endif
12 14
13#define DMTE0_IRQ 48 15#define DMTE0_IRQ evt2irq(0x800)
14#define DMTE4_IRQ 76 16#define DMTE4_IRQ evt2irq(0xb80)
15
16/* Definitions for the SuperH DMAC */
17#define TM_BURST 0x00000020
18#define TS_8 0x00000000
19#define TS_16 0x00000008
20#define TS_32 0x00000010
21#define TS_128 0x00000018
22 17
23#endif /* __ASM_CPU_SH3_DMA_H */ 18#endif /* __ASM_CPU_SH3_DMA_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
deleted file mode 100644
index 9647e681fd27..000000000000
--- a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
+++ /dev/null
@@ -1,83 +0,0 @@
1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
2#define __ASM_SH_CPU_SH4_DMA_SH7780_H
3
4#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
5 defined(CONFIG_CPU_SUBTYPE_SH7730)
6#define DMTE0_IRQ 48
7#define DMTE4_IRQ 76
8#define DMAE0_IRQ 78 /* DMA Error IRQ*/
9#define SH_DMAC_BASE0 0xFE008020
10#define SH_DMARS_BASE0 0xFE009000
11#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
12#define DMTE0_IRQ 48
13#define DMTE4_IRQ 76
14#define DMAE0_IRQ 78 /* DMA Error IRQ*/
15#define SH_DMAC_BASE0 0xFE008020
16#define SH_DMARS_BASE0 0xFE009000
17#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
18 defined(CONFIG_CPU_SUBTYPE_SH7764)
19#define DMTE0_IRQ 34
20#define DMTE4_IRQ 44
21#define DMAE0_IRQ 38
22#define SH_DMAC_BASE0 0xFF608020
23#define SH_DMARS_BASE0 0xFF609000
24#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
25#define DMTE0_IRQ 48 /* DMAC0A*/
26#define DMTE4_IRQ 76 /* DMAC0B */
27#define DMTE6_IRQ 40
28#define DMTE8_IRQ 42 /* DMAC1A */
29#define DMTE9_IRQ 43
30#define DMTE10_IRQ 72 /* DMAC1B */
31#define DMTE11_IRQ 73
32#define DMAE0_IRQ 78 /* DMA Error IRQ*/
33#define DMAE1_IRQ 74 /* DMA Error IRQ*/
34#define SH_DMAC_BASE0 0xFE008020
35#define SH_DMAC_BASE1 0xFDC08020
36#define SH_DMARS_BASE0 0xFDC09000
37#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
38#define DMTE0_IRQ 48 /* DMAC0A*/
39#define DMTE4_IRQ 76 /* DMAC0B */
40#define DMTE6_IRQ 40
41#define DMTE8_IRQ 42 /* DMAC1A */
42#define DMTE9_IRQ 43
43#define DMTE10_IRQ 72 /* DMAC1B */
44#define DMTE11_IRQ 73
45#define DMAE0_IRQ 78 /* DMA Error IRQ*/
46#define DMAE1_IRQ 74 /* DMA Error IRQ*/
47#define SH_DMAC_BASE0 0xFE008020
48#define SH_DMAC_BASE1 0xFDC08020
49#define SH_DMARS_BASE0 0xFE009000
50#define SH_DMARS_BASE1 0xFDC09000
51#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
52#define DMTE0_IRQ 34
53#define DMTE4_IRQ 44
54#define DMTE6_IRQ 46
55#define DMTE8_IRQ 92
56#define DMTE9_IRQ 93
57#define DMTE10_IRQ 94
58#define DMTE11_IRQ 95
59#define DMAE0_IRQ 38 /* DMA Error IRQ */
60#define SH_DMAC_BASE0 0xFC808020
61#define SH_DMAC_BASE1 0xFC818020
62#define SH_DMARS_BASE0 0xFC809000
63#else /* SH7785 */
64#define DMTE0_IRQ 33
65#define DMTE4_IRQ 37
66#define DMTE6_IRQ 52
67#define DMTE8_IRQ 54
68#define DMTE9_IRQ 55
69#define DMTE10_IRQ 56
70#define DMTE11_IRQ 57
71#define DMAE0_IRQ 39 /* DMA Error IRQ0 */
72#define DMAE1_IRQ 58 /* DMA Error IRQ1 */
73#define SH_DMAC_BASE0 0xFC808020
74#define SH_DMAC_BASE1 0xFCC08020
75#define SH_DMARS_BASE0 0xFC809000
76#endif
77
78#define REQ_HE 0x000000C0
79#define REQ_H 0x00000080
80#define REQ_LE 0x00000040
81#define TM_BURST 0x00000020
82
83#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma.h b/arch/sh/include/cpu-sh4/cpu/dma.h
index ca747e93c2ed..a520eb219621 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma.h
@@ -1,32 +1,17 @@
1#ifndef __ASM_CPU_SH4_DMA_H 1#ifndef __ASM_CPU_SH4_DMA_H
2#define __ASM_CPU_SH4_DMA_H 2#define __ASM_CPU_SH4_DMA_H
3 3
4/* SH7751/7760/7780 DMA IRQ sources */ 4#include <linux/sh_intc.h>
5 5
6#ifdef CONFIG_CPU_SH4A
7
8#include <cpu/dma-sh4a.h>
9
10#else /* CONFIG_CPU_SH4A */
11/* 6/*
12 * SH7750/SH7751/SH7760 7 * SH7750/SH7751/SH7760
13 */ 8 */
14#define DMTE0_IRQ 34 9#define DMTE0_IRQ evt2irq(0x640)
15#define DMTE4_IRQ 44 10#define DMTE4_IRQ evt2irq(0x780)
16#define DMTE6_IRQ 46 11#define DMTE6_IRQ evt2irq(0x7c0)
17#define DMAE0_IRQ 38 12#define DMAE0_IRQ evt2irq(0x6c0)
18 13
19#define SH_DMAC_BASE0 0xffa00000 14#define SH_DMAC_BASE0 0xffa00000
20#define SH_DMAC_BASE1 0xffa00070 15#define SH_DMAC_BASE1 0xffa00070
21/* Definitions for the SuperH DMAC */
22#define TM_BURST 0x00000080
23#define TS_8 0x00000010
24#define TS_16 0x00000020
25#define TS_32 0x00000030
26#define TS_64 0x00000000
27
28#define DMAOR_COD 0x00000008
29
30#endif
31 16
32#endif /* __ASM_CPU_SH4_DMA_H */ 17#endif /* __ASM_CPU_SH4_DMA_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index cffd25ed0240..1631fc238e6f 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -47,6 +47,11 @@
47#define MSTPCR1 0xa4150034 47#define MSTPCR1 0xa4150034
48#define MSTPCR2 0xa4150038 48#define MSTPCR2 0xa4150038
49 49
50#elif defined(CONFIG_CPU_SUBTYPE_SH7734)
51#define FRQCR0 0xffc80000
52#define FRQCR2 0xffc80008
53#define FRQMR1 0xffc80014
54#define FRQMR2 0xffc80018
50#elif defined(CONFIG_CPU_SUBTYPE_SH7785) 55#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
51#define FRQCR0 0xffc80000 56#define FRQCR0 0xffc80000
52#define FRQCR1 0xffc80004 57#define FRQCR1 0xffc80004
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7734.h b/arch/sh/include/cpu-sh4/cpu/sh7734.h
new file mode 100644
index 000000000000..2fb9a7b71b41
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7734.h
@@ -0,0 +1,306 @@
1#ifndef __ASM_SH7734_H__
2#define __ASM_SH7734_H__
3
4/* Pin Function Controller:
5 * GPIO_FN_xx - GPIO used to select pin function
6 * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
7 */
8enum {
9 GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
10 GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
11 GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
12 GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
13 GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
14 GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
15 GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
16 GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
17
18 GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
19 GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
20 GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
21 GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
22 GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
23 GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
24 GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
25 GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
26
27 GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
28 GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
29 GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
30 GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
31 GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
32 GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
33 GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
34 GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
35
36 GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
37 GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
38 GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
39 GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
40 GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
41 GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
42 GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
43 GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
44
45 GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
46 GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
47 GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
48 GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
49 GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
50 GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
51 GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
52 GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
53
54 GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
55 GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
56 GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
57
58 GPIO_FN_CLKOUT, GPIO_FN_BS, GPIO_FN_CS0, GPIO_FN_EX_CS0, GPIO_FN_RD,
59 GPIO_FN_WE0, GPIO_FN_WE1,
60
61 GPIO_FN_SCL0, GPIO_FN_PENC0, GPIO_FN_USB_OVC0,
62
63 GPIO_FN_IRQ2_B, GPIO_FN_IRQ3_B,
64
65 /* IPSR0 */
66 GPIO_FN_A15, GPIO_FN_ST0_VCO_CLKIN, GPIO_FN_LCD_DATA15_A,
67 GPIO_FN_TIOC3D_C,
68 GPIO_FN_A14, GPIO_FN_LCD_DATA14_A, GPIO_FN_TIOC3C_C,
69 GPIO_FN_A13, GPIO_FN_LCD_DATA13_A, GPIO_FN_TIOC3B_C,
70 GPIO_FN_A12, GPIO_FN_LCD_DATA12_A, GPIO_FN_TIOC3A_C,
71 GPIO_FN_A11, GPIO_FN_ST0_D7, GPIO_FN_LCD_DATA11_A,
72 GPIO_FN_TIOC2B_C,
73 GPIO_FN_A10, GPIO_FN_ST0_D6, GPIO_FN_LCD_DATA10_A,
74 GPIO_FN_TIOC2A_C,
75 GPIO_FN_A9, GPIO_FN_ST0_D5, GPIO_FN_LCD_DATA9_A,
76 GPIO_FN_TIOC1B_C,
77 GPIO_FN_A8, GPIO_FN_ST0_D4, GPIO_FN_LCD_DATA8_A,
78 GPIO_FN_TIOC1A_C,
79 GPIO_FN_A7, GPIO_FN_ST0_D3, GPIO_FN_LCD_DATA7_A, GPIO_FN_TIOC0D_C,
80 GPIO_FN_A6, GPIO_FN_ST0_D2, GPIO_FN_LCD_DATA6_A, GPIO_FN_TIOC0C_C,
81 GPIO_FN_A5, GPIO_FN_ST0_D1, GPIO_FN_LCD_DATA5_A, GPIO_FN_TIOC0B_C,
82 GPIO_FN_A4, GPIO_FN_ST0_D0, GPIO_FN_LCD_DATA4_A, GPIO_FN_TIOC0A_C,
83 GPIO_FN_A3, GPIO_FN_ST0_VLD, GPIO_FN_LCD_DATA3_A, GPIO_FN_TCLKD_C,
84 GPIO_FN_A2, GPIO_FN_ST0_SYC, GPIO_FN_LCD_DATA2_A, GPIO_FN_TCLKC_C,
85 GPIO_FN_A1, GPIO_FN_ST0_REQ, GPIO_FN_LCD_DATA1_A, GPIO_FN_TCLKB_C,
86 GPIO_FN_A0, GPIO_FN_ST0_CLKIN, GPIO_FN_LCD_DATA0_A, GPIO_FN_TCLKA_C,
87
88 /* IPSR1 */
89 GPIO_FN_D3, GPIO_FN_SD0_DAT3_A, GPIO_FN_MMC_D3_A, GPIO_FN_ST1_D6,
90 GPIO_FN_FD3_A,
91 GPIO_FN_D2, GPIO_FN_SD0_DAT2_A, GPIO_FN_MMC_D2_A, GPIO_FN_ST1_D5,
92 GPIO_FN_FD2_A,
93 GPIO_FN_D1, GPIO_FN_SD0_DAT1_A, GPIO_FN_MMC_D1_A, GPIO_FN_ST1_D4,
94 GPIO_FN_FD1_A,
95 GPIO_FN_D0, GPIO_FN_SD0_DAT0_A, GPIO_FN_MMC_D0_A, GPIO_FN_ST1_D3,
96 GPIO_FN_FD0_A,
97 GPIO_FN_A25, GPIO_FN_TX2_D, GPIO_FN_ST1_D2,
98 GPIO_FN_A24, GPIO_FN_RX2_D, GPIO_FN_ST1_D1,
99 GPIO_FN_A23, GPIO_FN_ST1_D0, GPIO_FN_LCD_M_DISP_A,
100 GPIO_FN_A22, GPIO_FN_ST1_VLD, GPIO_FN_LCD_VEPWC_A,
101 GPIO_FN_A21, GPIO_FN_ST1_SYC, GPIO_FN_LCD_VCPWC_A,
102 GPIO_FN_A20, GPIO_FN_ST1_REQ, GPIO_FN_LCD_FLM_A,
103 GPIO_FN_A19, GPIO_FN_ST1_CLKIN, GPIO_FN_LCD_CLK_A, GPIO_FN_TIOC4D_C,
104 GPIO_FN_A18, GPIO_FN_ST1_PWM, GPIO_FN_LCD_CL2_A, GPIO_FN_TIOC4C_C,
105 GPIO_FN_A17, GPIO_FN_ST1_VCO_CLKIN, GPIO_FN_LCD_CL1_A, GPIO_FN_TIOC4B_C,
106 GPIO_FN_A16, GPIO_FN_ST0_PWM, GPIO_FN_LCD_DON_A, GPIO_FN_TIOC4A_C,
107
108 /* IPSR2 */
109 GPIO_FN_D14, GPIO_FN_TX2_B, GPIO_FN_FSE_A, GPIO_FN_ET0_TX_CLK_B,
110 GPIO_FN_D13, GPIO_FN_RX2_B, GPIO_FN_FRB_A, GPIO_FN_ET0_ETXD6_B,
111 GPIO_FN_D12, GPIO_FN_FWE_A, GPIO_FN_ET0_ETXD5_B,
112 GPIO_FN_D11, GPIO_FN_RSPI_MISO_A, GPIO_FN_QMI_QIO1_A,
113 GPIO_FN_FRE_A, GPIO_FN_ET0_ETXD3_B,
114 GPIO_FN_D10, GPIO_FN_RSPI_MOSI_A, GPIO_FN_QMO_QIO0_A,
115 GPIO_FN_FALE_A, GPIO_FN_ET0_ETXD2_B,
116 GPIO_FN_D9, GPIO_FN_SD0_CMD_A, GPIO_FN_MMC_CMD_A, GPIO_FN_QIO3_A,
117 GPIO_FN_FCLE_A, GPIO_FN_ET0_ETXD1_B,
118 GPIO_FN_D8, GPIO_FN_SD0_CLK_A, GPIO_FN_MMC_CLK_A, GPIO_FN_QIO2_A,
119 GPIO_FN_FCE_A, GPIO_FN_ET0_GTX_CLK_B,
120 GPIO_FN_D7, GPIO_FN_RSPI_SSL_A, GPIO_FN_MMC_D7_A, GPIO_FN_QSSL_A,
121 GPIO_FN_FD7_A,
122 GPIO_FN_D6, GPIO_FN_RSPI_RSPCK_A, GPIO_FN_MMC_D6_A, GPIO_FN_QSPCLK_A,
123 GPIO_FN_FD6_A,
124 GPIO_FN_D5, GPIO_FN_SD0_WP_A, GPIO_FN_MMC_D5_A, GPIO_FN_FD5_A,
125 GPIO_FN_D4, GPIO_FN_SD0_CD_A, GPIO_FN_MMC_D4_A, GPIO_FN_ST1_D7,
126 GPIO_FN_FD4_A,
127
128 /* IPSR3 */
129 GPIO_FN_DRACK0, GPIO_FN_SD1_DAT2_A, GPIO_FN_ATAG, GPIO_FN_TCLK1_A,
130 GPIO_FN_ET0_ETXD7,
131 GPIO_FN_EX_WAIT2, GPIO_FN_SD1_DAT1_A, GPIO_FN_DACK2, GPIO_FN_CAN1_RX_C,
132 GPIO_FN_ET0_MAGIC_C, GPIO_FN_ET0_ETXD6_A,
133 GPIO_FN_EX_WAIT1, GPIO_FN_SD1_DAT0_A, GPIO_FN_DREQ2, GPIO_FN_CAN1_TX_C,
134 GPIO_FN_ET0_LINK_C, GPIO_FN_ET0_ETXD5_A,
135 GPIO_FN_EX_WAIT0, GPIO_FN_TCLK1_B,
136 GPIO_FN_RD_WR, GPIO_FN_TCLK0,
137 GPIO_FN_EX_CS5, GPIO_FN_SD1_CMD_A, GPIO_FN_ATADIR, GPIO_FN_QSSL_B,
138 GPIO_FN_ET0_ETXD3_A,
139 GPIO_FN_EX_CS4, GPIO_FN_SD1_WP_A, GPIO_FN_ATAWR, GPIO_FN_QMI_QIO1_B,
140 GPIO_FN_ET0_ETXD2_A,
141 GPIO_FN_EX_CS3, GPIO_FN_SD1_CD_A, GPIO_FN_ATARD, GPIO_FN_QMO_QIO0_B,
142 GPIO_FN_ET0_ETXD1_A,
143 GPIO_FN_EX_CS2, GPIO_FN_TX3_B, GPIO_FN_ATACS1, GPIO_FN_QSPCLK_B,
144 GPIO_FN_ET0_GTX_CLK_A,
145 GPIO_FN_EX_CS1, GPIO_FN_RX3_B, GPIO_FN_ATACS0, GPIO_FN_QIO2_B,
146 GPIO_FN_ET0_ETXD0,
147 GPIO_FN_CS1_A26, GPIO_FN_QIO3_B,
148 GPIO_FN_D15, GPIO_FN_SCK2_B,
149
150 /* IPSR4 */
151 GPIO_FN_SCK2_A, GPIO_FN_VI0_G3,
152 GPIO_FN_RTS1_B, GPIO_FN_VI0_G2,
153 GPIO_FN_CTS1_B, GPIO_FN_VI0_DATA7_VI0_G1,
154 GPIO_FN_TX1_B, GPIO_FN_VI0_DATA6_VI0_G0, GPIO_FN_ET0_PHY_INT_A,
155 GPIO_FN_RX1_B, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_ET0_MAGIC_A,
156 GPIO_FN_SCK1_B, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ET0_LINK_A,
157 GPIO_FN_RTS0_B, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ET0_MDIO_A,
158 GPIO_FN_CTS0_B, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_RMII0_MDIO_A,
159 GPIO_FN_ET0_MDC,
160 GPIO_FN_HTX0_A, GPIO_FN_TX1_A, GPIO_FN_VI0_DATA1_VI0_B1,
161 GPIO_FN_RMII0_MDC_A, GPIO_FN_ET0_COL,
162 GPIO_FN_HRX0_A, GPIO_FN_RX1_A, GPIO_FN_VI0_DATA0_VI0_B0,
163 GPIO_FN_RMII0_CRS_DV_A, GPIO_FN_ET0_CRS,
164 GPIO_FN_HSCK0_A, GPIO_FN_SCK1_A, GPIO_FN_VI0_VSYNC,
165 GPIO_FN_RMII0_RX_ER_A, GPIO_FN_ET0_RX_ER,
166 GPIO_FN_HRTS0_A, GPIO_FN_RTS1_A, GPIO_FN_VI0_HSYNC,
167 GPIO_FN_RMII0_TXD_EN_A, GPIO_FN_ET0_RX_DV,
168 GPIO_FN_HCTS0_A, GPIO_FN_CTS1_A, GPIO_FN_VI0_FIELD,
169 GPIO_FN_RMII0_RXD1_A, GPIO_FN_ET0_ERXD7,
170
171 /* IPSR5 */
172 GPIO_FN_SD2_CLK_A, GPIO_FN_RX2_A, GPIO_FN_VI0_G4, GPIO_FN_ET0_RX_CLK_B,
173 GPIO_FN_SD2_CMD_A, GPIO_FN_TX2_A, GPIO_FN_VI0_G5, GPIO_FN_ET0_ERXD2_B,
174 GPIO_FN_SD2_DAT0_A, GPIO_FN_RX3_A, GPIO_FN_VI0_R0, GPIO_FN_ET0_ERXD3_B,
175 GPIO_FN_SD2_DAT1_A, GPIO_FN_TX3_A, GPIO_FN_VI0_R1, GPIO_FN_ET0_MDIO_B,
176 GPIO_FN_SD2_DAT2_A, GPIO_FN_RX4_A, GPIO_FN_VI0_R2, GPIO_FN_ET0_LINK_B,
177 GPIO_FN_SD2_DAT3_A, GPIO_FN_TX4_A, GPIO_FN_VI0_R3, GPIO_FN_ET0_MAGIC_B,
178 GPIO_FN_SD2_CD_A, GPIO_FN_RX5_A, GPIO_FN_VI0_R4, GPIO_FN_ET0_PHY_INT_B,
179 GPIO_FN_SD2_WP_A, GPIO_FN_TX5_A, GPIO_FN_VI0_R5,
180 GPIO_FN_REF125CK, GPIO_FN_ADTRG, GPIO_FN_RX5_C,
181 GPIO_FN_REF50CK, GPIO_FN_CTS1_E, GPIO_FN_HCTS0_D,
182
183 /* IPSR6 */
184 GPIO_FN_DU0_DR0, GPIO_FN_SCIF_CLK_B, GPIO_FN_HRX0_D, GPIO_FN_IETX_A,
185 GPIO_FN_TCLKA_A, GPIO_FN_HIFD00,
186 GPIO_FN_DU0_DR1, GPIO_FN_SCK0_B, GPIO_FN_HTX0_D, GPIO_FN_IERX_A,
187 GPIO_FN_TCLKB_A, GPIO_FN_HIFD01,
188 GPIO_FN_DU0_DR2, GPIO_FN_RX0_B, GPIO_FN_TCLKC_A, GPIO_FN_HIFD02,
189 GPIO_FN_DU0_DR3, GPIO_FN_TX0_B, GPIO_FN_TCLKD_A, GPIO_FN_HIFD03,
190 GPIO_FN_DU0_DR4, GPIO_FN_CTS0_C, GPIO_FN_TIOC0A_A, GPIO_FN_HIFD04,
191 GPIO_FN_DU0_DR5, GPIO_FN_RTS0_C, GPIO_FN_TIOC0B_A, GPIO_FN_HIFD05,
192 GPIO_FN_DU0_DR6, GPIO_FN_SCK1_C, GPIO_FN_TIOC0C_A, GPIO_FN_HIFD06,
193 GPIO_FN_DU0_DR7, GPIO_FN_RX1_C, GPIO_FN_TIOC0D_A, GPIO_FN_HIFD07,
194 GPIO_FN_DU0_DG0, GPIO_FN_TX1_C, GPIO_FN_HSCK0_D, GPIO_FN_IECLK_A,
195 GPIO_FN_TIOC1A_A, GPIO_FN_HIFD08,
196 GPIO_FN_DU0_DG1, GPIO_FN_CTS1_C, GPIO_FN_HRTS0_D, GPIO_FN_TIOC1B_A,
197 GPIO_FN_HIFD09,
198
199 /* IPSR7 */
200 GPIO_FN_DU0_DG2, GPIO_FN_RTS1_C, GPIO_FN_RMII0_MDC_B, GPIO_FN_TIOC2A_A,
201 GPIO_FN_HIFD10,
202 GPIO_FN_DU0_DG3, GPIO_FN_SCK2_C, GPIO_FN_RMII0_MDIO_B, GPIO_FN_TIOC2B_A,
203 GPIO_FN_HIFD11,
204 GPIO_FN_DU0_DG4, GPIO_FN_RX2_C, GPIO_FN_RMII0_CRS_DV_B,
205 GPIO_FN_TIOC3A_A, GPIO_FN_HIFD12,
206 GPIO_FN_DU0_DG5, GPIO_FN_TX2_C, GPIO_FN_RMII0_RX_ER_B,
207 GPIO_FN_TIOC3B_A, GPIO_FN_HIFD13,
208 GPIO_FN_DU0_DG6, GPIO_FN_RX3_C, GPIO_FN_RMII0_RXD0_B,
209 GPIO_FN_TIOC3C_A, GPIO_FN_HIFD14,
210 GPIO_FN_DU0_DG7, GPIO_FN_TX3_C, GPIO_FN_RMII0_RXD1_B,
211 GPIO_FN_TIOC3D_A, GPIO_FN_HIFD15,
212 GPIO_FN_DU0_DB0, GPIO_FN_RX4_C, GPIO_FN_RMII0_TXD_EN_B,
213 GPIO_FN_TIOC4A_A, GPIO_FN_HIFCS,
214 GPIO_FN_DU0_DB1, GPIO_FN_TX4_C, GPIO_FN_RMII0_TXD0_B,
215 GPIO_FN_TIOC4B_A, GPIO_FN_HIFRS,
216 GPIO_FN_DU0_DB2, GPIO_FN_RX5_B, GPIO_FN_RMII0_TXD1_B,
217 GPIO_FN_TIOC4C_A, GPIO_FN_HIFWR,
218 GPIO_FN_DU0_DB3, GPIO_FN_TX5_B, GPIO_FN_TIOC4D_A, GPIO_FN_HIFRD,
219 GPIO_FN_DU0_DB4, GPIO_FN_HIFINT,
220
221 /* IPSR8 */
222 GPIO_FN_DU0_DB5, GPIO_FN_HIFDREQ,
223 GPIO_FN_DU0_DB6, GPIO_FN_HIFRDY,
224 GPIO_FN_DU0_DB7, GPIO_FN_SSI_SCK0_B, GPIO_FN_HIFEBL_B,
225 GPIO_FN_DU0_DOTCLKIN, GPIO_FN_HSPI_CS0_C, GPIO_FN_SSI_WS0_B,
226 GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_HSPI_CLK0_C, GPIO_FN_SSI_SDATA0_B,
227 GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_HSPI_TX0_C, GPIO_FN_SSI_SCK1_B,
228 GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_HSPI_RX0_C, GPIO_FN_SSI_WS1_B,
229 GPIO_FN_DU0_EXODDF_DU0_ODDF, GPIO_FN_CAN0_RX_B, GPIO_FN_HSCK0_B,
230 GPIO_FN_SSI_SDATA1_B,
231 GPIO_FN_DU0_DISP, GPIO_FN_CAN0_TX_B, GPIO_FN_HRX0_B,
232 GPIO_FN_AUDIO_CLKA_B,
233 GPIO_FN_DU0_CDE, GPIO_FN_HTX0_B, GPIO_FN_AUDIO_CLKB_B,
234 GPIO_FN_LCD_VCPWC_B,
235 GPIO_FN_IRQ0_A, GPIO_FN_HSPI_TX_B, GPIO_FN_RX3_E, GPIO_FN_ET0_ERXD0,
236 GPIO_FN_IRQ1_A, GPIO_FN_HSPI_RX_B, GPIO_FN_TX3_E, GPIO_FN_ET0_ERXD1,
237 GPIO_FN_IRQ2_A, GPIO_FN_CTS0_A, GPIO_FN_HCTS0_B, GPIO_FN_ET0_ERXD2_A,
238 GPIO_FN_IRQ3_A, GPIO_FN_RTS0_A, GPIO_FN_HRTS0_B, GPIO_FN_ET0_ERXD3_A,
239
240 /* IPSR9 */
241 GPIO_FN_VI1_CLK_A, GPIO_FN_FD0_B, GPIO_FN_LCD_DATA0_B,
242 GPIO_FN_VI1_0_A, GPIO_FN_FD1_B, GPIO_FN_LCD_DATA1_B,
243 GPIO_FN_VI1_1_A, GPIO_FN_FD2_B, GPIO_FN_LCD_DATA2_B,
244 GPIO_FN_VI1_2_A, GPIO_FN_FD3_B, GPIO_FN_LCD_DATA3_B,
245 GPIO_FN_VI1_3_A, GPIO_FN_FD4_B, GPIO_FN_LCD_DATA4_B,
246 GPIO_FN_VI1_4_A, GPIO_FN_FD5_B, GPIO_FN_LCD_DATA5_B,
247 GPIO_FN_VI1_5_A, GPIO_FN_FD6_B, GPIO_FN_LCD_DATA6_B,
248 GPIO_FN_VI1_6_A, GPIO_FN_FD7_B, GPIO_FN_LCD_DATA7_B,
249 GPIO_FN_VI1_7_A, GPIO_FN_FCE_B, GPIO_FN_LCD_DATA8_B,
250 GPIO_FN_SSI_SCK0_A, GPIO_FN_TIOC1A_B, GPIO_FN_LCD_DATA9_B,
251 GPIO_FN_SSI_WS0_A, GPIO_FN_TIOC1B_B, GPIO_FN_LCD_DATA10_B,
252 GPIO_FN_SSI_SDATA0_A, GPIO_FN_VI1_0_B, GPIO_FN_TIOC2A_B,
253 GPIO_FN_LCD_DATA11_B,
254 GPIO_FN_SSI_SCK1_A, GPIO_FN_VI1_1_B, GPIO_FN_TIOC2B_B,
255 GPIO_FN_LCD_DATA12_B,
256 GPIO_FN_SSI_WS1_A, GPIO_FN_VI1_2_B, GPIO_FN_LCD_DATA13_B,
257 GPIO_FN_SSI_SDATA1_A, GPIO_FN_VI1_3_B, GPIO_FN_LCD_DATA14_B,
258
259 /* IPSR10 */
260 GPIO_FN_SSI_SCK23, GPIO_FN_VI1_4_B, GPIO_FN_RX1_D, GPIO_FN_FCLE_B,
261 GPIO_FN_LCD_DATA15_B,
262 GPIO_FN_SSI_WS23, GPIO_FN_VI1_5_B, GPIO_FN_TX1_D, GPIO_FN_HSCK0_C,
263 GPIO_FN_FALE_B, GPIO_FN_LCD_DON_B,
264 GPIO_FN_SSI_SDATA2, GPIO_FN_VI1_6_B, GPIO_FN_HRX0_C, GPIO_FN_FRE_B,
265 GPIO_FN_LCD_CL1_B,
266 GPIO_FN_SSI_SDATA3, GPIO_FN_VI1_7_B, GPIO_FN_HTX0_C, GPIO_FN_FWE_B,
267 GPIO_FN_LCD_CL2_B,
268 GPIO_FN_AUDIO_CLKA_A, GPIO_FN_VI1_CLK_B, GPIO_FN_SCK1_D,
269 GPIO_FN_IECLK_B, GPIO_FN_LCD_FLM_B,
270 GPIO_FN_AUDIO_CLKB_A, GPIO_FN_LCD_CLK_B,
271 GPIO_FN_AUDIO_CLKC, GPIO_FN_SCK1_E, GPIO_FN_HCTS0_C, GPIO_FN_FRB_B,
272 GPIO_FN_LCD_VEPWC_B,
273 GPIO_FN_AUDIO_CLKOUT, GPIO_FN_TX1_E, GPIO_FN_HRTS0_C, GPIO_FN_FSE_B,
274 GPIO_FN_LCD_M_DISP_B,
275 GPIO_FN_CAN_CLK_A, GPIO_FN_RX4_D,
276 GPIO_FN_CAN0_TX_A, GPIO_FN_TX4_D, GPIO_FN_MLB_CLK,
277 GPIO_FN_CAN1_RX_A, GPIO_FN_IRQ1_B,
278 GPIO_FN_CAN0_RX_A, GPIO_FN_IRQ0_B, GPIO_FN_MLB_SIG,
279 GPIO_FN_CAN1_TX_A, GPIO_FN_TX5_C, GPIO_FN_MLB_DAT,
280
281 /* IPSR11 */
282 GPIO_FN_SCL1, GPIO_FN_SCIF_CLK_C,
283 GPIO_FN_SDA1, GPIO_FN_RX1_E,
284 GPIO_FN_SDA0, GPIO_FN_HIFEBL_A,
285 GPIO_FN_SDSELF, GPIO_FN_RTS1_E,
286 GPIO_FN_SCIF_CLK_A, GPIO_FN_HSPI_CLK_A, GPIO_FN_VI0_CLK,
287 GPIO_FN_RMII0_TXD0_A, GPIO_FN_ET0_ERXD4,
288 GPIO_FN_SCK0_A, GPIO_FN_HSPI_CS_A, GPIO_FN_VI0_CLKENB,
289 GPIO_FN_RMII0_TXD1_A, GPIO_FN_ET0_ERXD5,
290 GPIO_FN_RX0_A, GPIO_FN_HSPI_RX_A, GPIO_FN_RMII0_RXD0_A,
291 GPIO_FN_ET0_ERXD6,
292 GPIO_FN_TX0_A, GPIO_FN_HSPI_TX_A,
293 GPIO_FN_PENC1, GPIO_FN_TX3_D, GPIO_FN_CAN1_TX_B, GPIO_FN_TX5_D,
294 GPIO_FN_IETX_B,
295 GPIO_FN_USB_OVC1, GPIO_FN_RX3_D, GPIO_FN_CAN1_RX_B, GPIO_FN_RX5_D,
296 GPIO_FN_IERX_B,
297 GPIO_FN_DREQ0, GPIO_FN_SD1_CLK_A, GPIO_FN_ET0_TX_EN,
298 GPIO_FN_DACK0, GPIO_FN_SD1_DAT3_A, GPIO_FN_ET0_TX_ER,
299 GPIO_FN_DREQ1, GPIO_FN_HSPI_CLK_B, GPIO_FN_RX4_B, GPIO_FN_ET0_PHY_INT_C,
300 GPIO_FN_ET0_TX_CLK_A,
301 GPIO_FN_DACK1, GPIO_FN_HSPI_CS_B, GPIO_FN_TX4_B, GPIO_FN_ET0_RX_CLK_A,
302 GPIO_FN_PRESETOUT, GPIO_FN_ST_CLKOUT,
303
304};
305
306#endif /* __ASM_SH7734_H__ */
diff --git a/arch/sh/include/cpu-sh4a/cpu/dma.h b/arch/sh/include/cpu-sh4a/cpu/dma.h
new file mode 100644
index 000000000000..89afb650ce25
--- /dev/null
+++ b/arch/sh/include/cpu-sh4a/cpu/dma.h
@@ -0,0 +1,72 @@
1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
2#define __ASM_SH_CPU_SH4_DMA_SH7780_H
3
4#include <linux/sh_intc.h>
5
6#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
7 defined(CONFIG_CPU_SUBTYPE_SH7730)
8#define DMTE0_IRQ evt2irq(0x800)
9#define DMTE4_IRQ evt2irq(0xb80)
10#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
11#define SH_DMAC_BASE0 0xFE008020
12#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
13#define DMTE0_IRQ evt2irq(0x800)
14#define DMTE4_IRQ evt2irq(0xb80)
15#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
16#define SH_DMAC_BASE0 0xFE008020
17#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
18 defined(CONFIG_CPU_SUBTYPE_SH7764)
19#define DMTE0_IRQ evt2irq(0x640)
20#define DMTE4_IRQ evt2irq(0x780)
21#define DMAE0_IRQ evt2irq(0x6c0)
22#define SH_DMAC_BASE0 0xFF608020
23#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
24#define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/
25#define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */
26#define DMTE6_IRQ evt2irq(0x700)
27#define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */
28#define DMTE9_IRQ evt2irq(0x760)
29#define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */
30#define DMTE11_IRQ evt2irq(0xb20)
31#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
32#define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/
33#define SH_DMAC_BASE0 0xFE008020
34#define SH_DMAC_BASE1 0xFDC08020
35#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
36#define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/
37#define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */
38#define DMTE6_IRQ evt2irq(0x700)
39#define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */
40#define DMTE9_IRQ evt2irq(0x760)
41#define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */
42#define DMTE11_IRQ evt2irq(0xb20)
43#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
44#define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/
45#define SH_DMAC_BASE0 0xFE008020
46#define SH_DMAC_BASE1 0xFDC08020
47#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
48#define DMTE0_IRQ evt2irq(0x640)
49#define DMTE4_IRQ evt2irq(0x780)
50#define DMTE6_IRQ evt2irq(0x7c0)
51#define DMTE8_IRQ evt2irq(0xd80)
52#define DMTE9_IRQ evt2irq(0xda0)
53#define DMTE10_IRQ evt2irq(0xdc0)
54#define DMTE11_IRQ evt2irq(0xde0)
55#define DMAE0_IRQ evt2irq(0x6c0) /* DMA Error IRQ */
56#define SH_DMAC_BASE0 0xFC808020
57#define SH_DMAC_BASE1 0xFC818020
58#else /* SH7785 */
59#define DMTE0_IRQ evt2irq(0x620)
60#define DMTE4_IRQ evt2irq(0x6a0)
61#define DMTE6_IRQ evt2irq(0x880)
62#define DMTE8_IRQ evt2irq(0x8c0)
63#define DMTE9_IRQ evt2irq(0x8e0)
64#define DMTE10_IRQ evt2irq(0x900)
65#define DMTE11_IRQ evt2irq(0x920)
66#define DMAE0_IRQ evt2irq(0x6e0) /* DMA Error IRQ0 */
67#define DMAE1_IRQ evt2irq(0x940) /* DMA Error IRQ1 */
68#define SH_DMAC_BASE0 0xFC808020
69#define SH_DMAC_BASE1 0xFCC08020
70#endif
71
72#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/dma.h b/arch/sh/include/cpu-sh5/cpu/dma.h
deleted file mode 100644
index 7bf6bb3d35ed..000000000000
--- a/arch/sh/include/cpu-sh5/cpu/dma.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_SH_CPU_SH5_DMA_H
2#define __ASM_SH_CPU_SH5_DMA_H
3
4/* Nothing yet */
5
6#endif /* __ASM_SH_CPU_SH5_DMA_H */
diff --git a/arch/sh/include/mach-common/mach/hp6xx.h b/arch/sh/include/mach-common/mach/hp6xx.h
index bcc301ac12f4..6aaaf8596e6a 100644
--- a/arch/sh/include/mach-common/mach/hp6xx.h
+++ b/arch/sh/include/mach-common/mach/hp6xx.h
@@ -9,10 +9,11 @@
9 * for more details. 9 * for more details.
10 * 10 *
11 */ 11 */
12#include <linux/sh_intc.h>
12 13
13#define HP680_BTN_IRQ 32 /* IRQ0_IRQ */ 14#define HP680_BTN_IRQ evt2irq(0x600) /* IRQ0_IRQ */
14#define HP680_TS_IRQ 35 /* IRQ3_IRQ */ 15#define HP680_TS_IRQ evt2irq(0x660) /* IRQ3_IRQ */
15#define HP680_HD64461_IRQ 36 /* IRQ4_IRQ */ 16#define HP680_HD64461_IRQ evt2irq(0x680) /* IRQ4_IRQ */
16 17
17#define DAC_LCD_BRIGHTNESS 0 18#define DAC_LCD_BRIGHTNESS 0
18#define DAC_SPEAKER_VOLUME 1 19#define DAC_SPEAKER_VOLUME 1
diff --git a/arch/sh/include/mach-common/mach/lboxre2.h b/arch/sh/include/mach-common/mach/lboxre2.h
index e6d160504923..3a4dcc5c74ee 100644
--- a/arch/sh/include/mach-common/mach/lboxre2.h
+++ b/arch/sh/include/mach-common/mach/lboxre2.h
@@ -11,13 +11,14 @@
11 * for more details. 11 * for more details.
12 * 12 *
13 */ 13 */
14#include <linux/sh_intc.h>
14 15
15#define IRQ_CF1 9 /* CF1 */ 16#define IRQ_CF1 evt2irq(0x320) /* CF1 */
16#define IRQ_CF0 10 /* CF0 */ 17#define IRQ_CF0 evt2irq(0x340) /* CF0 */
17#define IRQ_INTD 11 /* INTD */ 18#define IRQ_INTD evt2irq(0x360) /* INTD */
18#define IRQ_ETH1 12 /* Ether1 */ 19#define IRQ_ETH1 evt2irq(0x380) /* Ether1 */
19#define IRQ_ETH0 13 /* Ether0 */ 20#define IRQ_ETH0 evt2irq(0x3a0) /* Ether0 */
20#define IRQ_INTA 14 /* INTA */ 21#define IRQ_INTA evt2irq(0x3c0) /* INTA */
21 22
22void init_lboxre2_IRQ(void); 23void init_lboxre2_IRQ(void);
23 24
diff --git a/arch/sh/include/mach-common/mach/sdk7780.h b/arch/sh/include/mach-common/mach/sdk7780.h
index 697dc865f21b..ce64e02e9b50 100644
--- a/arch/sh/include/mach-common/mach/sdk7780.h
+++ b/arch/sh/include/mach-common/mach/sdk7780.h
@@ -11,6 +11,7 @@
11 * License. See the file "COPYING" in the main directory of this archive 11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details. 12 * for more details.
13 */ 13 */
14#include <linux/sh_intc.h>
14#include <asm/addrspace.h> 15#include <asm/addrspace.h>
15 16
16/* Box specific addresses. */ 17/* Box specific addresses. */
@@ -67,9 +68,9 @@
67 68
68#define SDK7780_NR_IRL 15 69#define SDK7780_NR_IRL 15
69/* IDE/ATA interrupt */ 70/* IDE/ATA interrupt */
70#define IRQ_CFCARD 14 71#define IRQ_CFCARD evt2irq(0x3c0)
71/* SMC interrupt */ 72/* SMC interrupt */
72#define IRQ_ETHERNET 6 73#define IRQ_ETHERNET evt2irq(0x2c0)
73 74
74 75
75/* arch/sh/boards/renesas/sdk7780/irq.c */ 76/* arch/sh/boards/renesas/sdk7780/irq.c */
diff --git a/arch/sh/include/mach-common/mach/titan.h b/arch/sh/include/mach-common/mach/titan.h
index 4a674d27cbb8..fa3cd801cf2e 100644
--- a/arch/sh/include/mach-common/mach/titan.h
+++ b/arch/sh/include/mach-common/mach/titan.h
@@ -4,14 +4,16 @@
4#ifndef _ASM_SH_TITAN_H 4#ifndef _ASM_SH_TITAN_H
5#define _ASM_SH_TITAN_H 5#define _ASM_SH_TITAN_H
6 6
7#include <linux/sh_intc.h>
8
7#define __IO_PREFIX titan 9#define __IO_PREFIX titan
8#include <asm/io_generic.h> 10#include <asm/io_generic.h>
9 11
10/* IRQ assignments */ 12/* IRQ assignments */
11#define TITAN_IRQ_WAN 2 /* eth0 (WAN) */ 13#define TITAN_IRQ_WAN evt2irq(0x240) /* eth0 (WAN) */
12#define TITAN_IRQ_LAN 5 /* eth1 (LAN) */ 14#define TITAN_IRQ_LAN evt2irq(0x2a0) /* eth1 (LAN) */
13#define TITAN_IRQ_MPCIA 8 /* mPCI A */ 15#define TITAN_IRQ_MPCIA evt2irq(0x300) /* mPCI A */
14#define TITAN_IRQ_MPCIB 11 /* mPCI B */ 16#define TITAN_IRQ_MPCIB evt2irq(0x360) /* mPCI B */
15#define TITAN_IRQ_USB 11 /* USB */ 17#define TITAN_IRQ_USB evt2irq(0x360) /* USB */
16 18
17#endif /* __ASM_SH_TITAN_H */ 19#endif /* __ASM_SH_TITAN_H */
diff --git a/arch/sh/include/mach-dreamcast/mach/dma.h b/arch/sh/include/mach-dreamcast/mach/dma.h
index ddd68e788705..1dbfdf701c9d 100644
--- a/arch/sh/include/mach-dreamcast/mach/dma.h
+++ b/arch/sh/include/mach-dreamcast/mach/dma.h
@@ -11,9 +11,7 @@
11#define __ASM_SH_DREAMCAST_DMA_H 11#define __ASM_SH_DREAMCAST_DMA_H
12 12
13/* Number of DMA channels */ 13/* Number of DMA channels */
14#define ONCHIP_NR_DMA_CHANNELS 4
15#define G2_NR_DMA_CHANNELS 4 14#define G2_NR_DMA_CHANNELS 4
16#define PVR2_NR_DMA_CHANNELS 1
17 15
18/* Channels for cascading */ 16/* Channels for cascading */
19#define PVR2_CASCADE_CHAN 2 17#define PVR2_CASCADE_CHAN 2
diff --git a/arch/sh/include/mach-landisk/mach/iodata_landisk.h b/arch/sh/include/mach-landisk/mach/iodata_landisk.h
index f432773a9571..ceeea48cc7af 100644
--- a/arch/sh/include/mach-landisk/mach/iodata_landisk.h
+++ b/arch/sh/include/mach-landisk/mach/iodata_landisk.h
@@ -8,6 +8,7 @@
8 * 8 *
9 * IO-DATA LANDISK support 9 * IO-DATA LANDISK support
10 */ 10 */
11#include <linux/sh_intc.h>
11 12
12/* Box specific addresses. */ 13/* Box specific addresses. */
13 14
@@ -25,15 +26,15 @@
25#define PA_PIDE_OFFSET 0x40 /* CF IDE Offset */ 26#define PA_PIDE_OFFSET 0x40 /* CF IDE Offset */
26#define PA_SIDE_OFFSET 0x40 /* HDD IDE Offset */ 27#define PA_SIDE_OFFSET 0x40 /* HDD IDE Offset */
27 28
28#define IRQ_PCIINTA 5 /* PCI INTA IRQ */ 29#define IRQ_PCIINTA evt2irq(0x2a0) /* PCI INTA IRQ */
29#define IRQ_PCIINTB 6 /* PCI INTB IRQ */ 30#define IRQ_PCIINTB evt2irq(0x2c0) /* PCI INTB IRQ */
30#define IRQ_PCIINTC 7 /* PCI INTC IRQ */ 31#define IRQ_PCIINTC evt2irq(0x2e0) /* PCI INTC IRQ */
31#define IRQ_PCIINTD 8 /* PCI INTD IRQ */ 32#define IRQ_PCIINTD evt2irq(0x300) /* PCI INTD IRQ */
32#define IRQ_ATA 9 /* ATA IRQ */ 33#define IRQ_ATA evt2irq(0x320) /* ATA IRQ */
33#define IRQ_FATA 10 /* FATA IRQ */ 34#define IRQ_FATA evt2irq(0x340) /* FATA IRQ */
34#define IRQ_POWER 11 /* Power Switch IRQ */ 35#define IRQ_POWER evt2irq(0x360) /* Power Switch IRQ */
35#define IRQ_BUTTON 12 /* USL-5P Button IRQ */ 36#define IRQ_BUTTON evt2irq(0x380) /* USL-5P Button IRQ */
36#define IRQ_FAULT 13 /* USL-5P Fault IRQ */ 37#define IRQ_FAULT evt2irq(0x3a0) /* USL-5P Fault IRQ */
37 38
38void init_landisk_IRQ(void); 39void init_landisk_IRQ(void);
39 40
diff --git a/arch/sh/include/mach-se/mach/se.h b/arch/sh/include/mach-se/mach/se.h
index 14be91c5a2f0..8a6d44b4987b 100644
--- a/arch/sh/include/mach-se/mach/se.h
+++ b/arch/sh/include/mach-se/mach/se.h
@@ -8,6 +8,7 @@
8 * 8 *
9 * Hitachi SolutionEngine support 9 * Hitachi SolutionEngine support
10 */ 10 */
11#include <linux/sh_intc.h>
11 12
12/* Box specific addresses. */ 13/* Box specific addresses. */
13 14
@@ -82,16 +83,16 @@
82#define INTC_IPRD 0xa4000018UL 83#define INTC_IPRD 0xa4000018UL
83#define INTC_IPRE 0xa400001aUL 84#define INTC_IPRE 0xa400001aUL
84 85
85#define IRQ0_IRQ 32 86#define IRQ0_IRQ evt2irq(0x600)
86#define IRQ1_IRQ 33 87#define IRQ1_IRQ evt2irq(0x620)
87#endif 88#endif
88 89
89#if defined(CONFIG_CPU_SUBTYPE_SH7705) 90#if defined(CONFIG_CPU_SUBTYPE_SH7705)
90#define IRQ_STNIC 12 91#define IRQ_STNIC evt2irq(0x380)
91#define IRQ_CFCARD 14 92#define IRQ_CFCARD evt2irq(0x3c0)
92#else 93#else
93#define IRQ_STNIC 10 94#define IRQ_STNIC evt2irq(0x340)
94#define IRQ_CFCARD 7 95#define IRQ_CFCARD evt2irq(0x2e0)
95#endif 96#endif
96 97
97/* SH Ether support (SH7710/SH7712) */ 98/* SH Ether support (SH7710/SH7712) */
@@ -105,9 +106,9 @@
105# define PHY_ID 0x01 106# define PHY_ID 0x01
106#endif 107#endif
107/* Ether IRQ */ 108/* Ether IRQ */
108#define SH_ETH0_IRQ 80 109#define SH_ETH0_IRQ evt2irq(0xc00)
109#define SH_ETH1_IRQ 81 110#define SH_ETH1_IRQ evt2irq(0xc20)
110#define SH_TSU_IRQ 82 111#define SH_TSU_IRQ evt2irq(0xc40)
111 112
112void init_se_IRQ(void); 113void init_se_IRQ(void);
113 114
diff --git a/arch/sh/include/mach-se/mach/se7343.h b/arch/sh/include/mach-se/mach/se7343.h
index 8d8170d6cc43..50b5d575dff0 100644
--- a/arch/sh/include/mach-se/mach/se7343.h
+++ b/arch/sh/include/mach-se/mach/se7343.h
@@ -8,6 +8,7 @@
8 * 8 *
9 * SH-Mobile SolutionEngine 7343 support 9 * SH-Mobile SolutionEngine 7343 support
10 */ 10 */
11#include <linux/sh_intc.h>
11 12
12/* Box specific addresses. */ 13/* Box specific addresses. */
13 14
@@ -118,10 +119,10 @@
118#define FPGA_IN 0xb1400000 119#define FPGA_IN 0xb1400000
119#define FPGA_OUT 0xb1400002 120#define FPGA_OUT 0xb1400002
120 121
121#define IRQ0_IRQ 32 122#define IRQ0_IRQ evt2irq(0x600)
122#define IRQ1_IRQ 33 123#define IRQ1_IRQ evt2irq(0x620)
123#define IRQ4_IRQ 36 124#define IRQ4_IRQ evt2irq(0x680)
124#define IRQ5_IRQ 37 125#define IRQ5_IRQ evt2irq(0x6a0)
125 126
126#define SE7343_FPGA_IRQ_MRSHPC0 0 127#define SE7343_FPGA_IRQ_MRSHPC0 0
127#define SE7343_FPGA_IRQ_MRSHPC1 1 128#define SE7343_FPGA_IRQ_MRSHPC1 1
diff --git a/arch/sh/include/mach-se/mach/se7721.h b/arch/sh/include/mach-se/mach/se7721.h
index b957f6041193..eabd0538de44 100644
--- a/arch/sh/include/mach-se/mach/se7721.h
+++ b/arch/sh/include/mach-se/mach/se7721.h
@@ -11,6 +11,8 @@
11 11
12#ifndef __ASM_SH_SE7721_H 12#ifndef __ASM_SH_SE7721_H
13#define __ASM_SH_SE7721_H 13#define __ASM_SH_SE7721_H
14
15#include <linux/sh_intc.h>
14#include <asm/addrspace.h> 16#include <asm/addrspace.h>
15 17
16/* Box specific addresses. */ 18/* Box specific addresses. */
@@ -49,9 +51,9 @@
49#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) 51#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
50 52
51#define PA_LED 0xB6800000 /* 8bit LED */ 53#define PA_LED 0xB6800000 /* 8bit LED */
52#define PA_FPGA 0xB7000000 /* FPGA base address */ 54#define PA_FPGA 0xB7000000 /* FPGA base address */
53 55
54#define MRSHPC_IRQ0 10 56#define MRSHPC_IRQ0 evt2irq(0x340)
55 57
56#define FPGA_ILSR1 (PA_FPGA + 0x02) 58#define FPGA_ILSR1 (PA_FPGA + 0x02)
57#define FPGA_ILSR2 (PA_FPGA + 0x03) 59#define FPGA_ILSR2 (PA_FPGA + 0x03)
diff --git a/arch/sh/include/mach-se/mach/se7722.h b/arch/sh/include/mach-se/mach/se7722.h
index 16505bfb8a9e..201081ebdbce 100644
--- a/arch/sh/include/mach-se/mach/se7722.h
+++ b/arch/sh/include/mach-se/mach/se7722.h
@@ -13,6 +13,7 @@
13 * for more details. 13 * for more details.
14 * 14 *
15 */ 15 */
16#include <linux/sh_intc.h>
16#include <asm/addrspace.h> 17#include <asm/addrspace.h>
17 18
18/* Box specific addresses. */ 19/* Box specific addresses. */
@@ -31,7 +32,7 @@
31 32
32#define PA_PERIPHERAL 0xB0000000 33#define PA_PERIPHERAL 0xB0000000
33 34
34#define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */ 35#define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */
35#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */ 36#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */
36#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */ 37#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */
37#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */ 38#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */
@@ -51,7 +52,7 @@
51#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) 52#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
52 53
53#define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */ 54#define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */
54#define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */ 55#define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */
55 56
56#define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */ 57#define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */
57/* GPIO */ 58/* GPIO */
@@ -77,8 +78,8 @@
77#define PORT_HIZCRC 0xA405015CUL 78#define PORT_HIZCRC 0xA405015CUL
78 79
79/* IRQ */ 80/* IRQ */
80#define IRQ0_IRQ 32 81#define IRQ0_IRQ evt2irq(0x600)
81#define IRQ1_IRQ 33 82#define IRQ1_IRQ evt2irq(0x620)
82 83
83#define IRQ01_MODE 0xb1800000 84#define IRQ01_MODE 0xb1800000
84#define IRQ01_STS 0xb1800004 85#define IRQ01_STS 0xb1800004
diff --git a/arch/sh/include/mach-se/mach/se7724.h b/arch/sh/include/mach-se/mach/se7724.h
index 29514a39d0f5..be842dd1ca02 100644
--- a/arch/sh/include/mach-se/mach/se7724.h
+++ b/arch/sh/include/mach-se/mach/se7724.h
@@ -18,6 +18,7 @@
18 * for more details. 18 * for more details.
19 * 19 *
20 */ 20 */
21#include <linux/sh_intc.h>
21#include <asm/addrspace.h> 22#include <asm/addrspace.h>
22 23
23/* SH Eth */ 24/* SH Eth */
@@ -35,9 +36,9 @@
35#define IRQ2_MR (0xba200028) 36#define IRQ2_MR (0xba200028)
36 37
37/* IRQ */ 38/* IRQ */
38#define IRQ0_IRQ 32 39#define IRQ0_IRQ evt2irq(0x600)
39#define IRQ1_IRQ 33 40#define IRQ1_IRQ evt2irq(0x620)
40#define IRQ2_IRQ 34 41#define IRQ2_IRQ evt2irq(0x640)
41 42
42/* Bits in IRQ012 registers */ 43/* Bits in IRQ012 registers */
43#define SE7724_FPGA_IRQ_BASE 220 44#define SE7724_FPGA_IRQ_BASE 220
diff --git a/arch/sh/include/mach-se/mach/se7751.h b/arch/sh/include/mach-se/mach/se7751.h
index b36792ac5d66..271871793d59 100644
--- a/arch/sh/include/mach-se/mach/se7751.h
+++ b/arch/sh/include/mach-se/mach/se7751.h
@@ -11,6 +11,7 @@
11 * Modified for 7751 Solution Engine by 11 * Modified for 7751 Solution Engine by
12 * Ian da Silva and Jeremy Siegel, 2001. 12 * Ian da Silva and Jeremy Siegel, 2001.
13 */ 13 */
14#include <linux/sh_intc.h>
14 15
15/* Box specific addresses. */ 16/* Box specific addresses. */
16 17
@@ -63,7 +64,7 @@
63#define BCR_ILCRF (PA_BCR + 10) 64#define BCR_ILCRF (PA_BCR + 10)
64#define BCR_ILCRG (PA_BCR + 12) 65#define BCR_ILCRG (PA_BCR + 12)
65 66
66#define IRQ_79C973 13 67#define IRQ_79C973 evt2irq(0x3a0)
67 68
68void init_7751se_IRQ(void); 69void init_7751se_IRQ(void);
69 70
diff --git a/arch/sh/include/mach-se/mach/se7780.h b/arch/sh/include/mach-se/mach/se7780.h
index 40e9b41458cd..bde357cf81bd 100644
--- a/arch/sh/include/mach-se/mach/se7780.h
+++ b/arch/sh/include/mach-se/mach/se7780.h
@@ -12,6 +12,7 @@
12 * License. See the file "COPYING" in the main directory of this archive 12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details. 13 * for more details.
14 */ 14 */
15#include <linux/sh_intc.h>
15#include <asm/addrspace.h> 16#include <asm/addrspace.h>
16 17
17/* Box specific addresses. */ 18/* Box specific addresses. */
@@ -80,13 +81,13 @@
80#define IRQPOS_PCCPW (0 * 4) 81#define IRQPOS_PCCPW (0 * 4)
81 82
82/* IDE interrupt */ 83/* IDE interrupt */
83#define IRQ_IDE0 67 /* iVDR */ 84#define IRQ_IDE0 evt2irq(0xa60) /* iVDR */
84 85
85/* SMC interrupt */ 86/* SMC interrupt */
86#define SMC_IRQ 8 87#define SMC_IRQ evt2irq(0x300)
87 88
88/* SM501 interrupt */ 89/* SM501 interrupt */
89#define SM501_IRQ 0 90#define SM501_IRQ evt2irq(0x200)
90 91
91/* interrupt pin */ 92/* interrupt pin */
92#define IRQPIN_EXTINT1 0 /* IRQ0 pin */ 93#define IRQPIN_EXTINT1 0 /* IRQ0 pin */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-02 00:26:45 -0400