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authorPaul Mundt <lethal@linux-sh.org>2008-07-29 08:41:37 -0400
committerPaul Mundt <lethal@linux-sh.org>2008-07-29 08:41:37 -0400
commit939a24a6df24649cea9fd0ff54fe71ee0dc1d61e (patch)
tree75c71fec79583491ed0ae1038f906ce90d11192c /arch/sh/include/mach-se
parente565b518ec3a62aebf54da31c65bb6036bb5a276 (diff)
sh: Move out the solution engine headers to arch/sh/include/mach-se/
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/mach-se')
-rw-r--r--arch/sh/include/mach-se/mach/se.h99
-rw-r--r--arch/sh/include/mach-se/mach/se7206.h13
-rw-r--r--arch/sh/include/mach-se/mach/se7343.h149
-rw-r--r--arch/sh/include/mach-se/mach/se7721.h70
-rw-r--r--arch/sh/include/mach-se/mach/se7722.h112
-rw-r--r--arch/sh/include/mach-se/mach/se7751.h73
-rw-r--r--arch/sh/include/mach-se/mach/se7780.h108
7 files changed, 624 insertions, 0 deletions
diff --git a/arch/sh/include/mach-se/mach/se.h b/arch/sh/include/mach-se/mach/se.h
new file mode 100644
index 000000000000..eb23000e1bbe
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se.h
@@ -0,0 +1,99 @@
1#ifndef __ASM_SH_HITACHI_SE_H
2#define __ASM_SH_HITACHI_SE_H
3
4/*
5 * linux/include/asm-sh/hitachi_se.h
6 *
7 * Copyright (C) 2000 Kazumoto Kojima
8 *
9 * Hitachi SolutionEngine support
10 */
11
12/* Box specific addresses. */
13
14#define PA_ROM 0x00000000 /* EPROM */
15#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
16#define PA_FROM 0x01000000 /* EPROM */
17#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
18#define PA_EXT1 0x04000000
19#define PA_EXT1_SIZE 0x04000000
20#define PA_EXT2 0x08000000
21#define PA_EXT2_SIZE 0x04000000
22#define PA_SDRAM 0x0c000000
23#define PA_SDRAM_SIZE 0x04000000
24
25#define PA_EXT4 0x12000000
26#define PA_EXT4_SIZE 0x02000000
27#define PA_EXT5 0x14000000
28#define PA_EXT5_SIZE 0x04000000
29#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
30
31#define PA_83902 0xb0000000 /* DP83902A */
32#define PA_83902_IF 0xb0040000 /* DP83902A remote io port */
33#define PA_83902_RST 0xb0080000 /* DP83902A reset port */
34
35#define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */
36#define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */
37#define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */
38#define PA_LED 0xb0c00000 /* LED */
39#if defined(CONFIG_CPU_SUBTYPE_SH7705)
40#define PA_BCR 0xb0e00000
41#else
42#define PA_BCR 0xb1400000 /* FPGA */
43#endif
44
45#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
46#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
47#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
48#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
49#define MRSHPC_OPTION (PA_MRSHPC + 6)
50#define MRSHPC_CSR (PA_MRSHPC + 8)
51#define MRSHPC_ISR (PA_MRSHPC + 10)
52#define MRSHPC_ICR (PA_MRSHPC + 12)
53#define MRSHPC_CPWCR (PA_MRSHPC + 14)
54#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
55#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
56#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
57#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
58#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
59#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
60#define MRSHPC_CDCR (PA_MRSHPC + 28)
61#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
62
63#define BCR_ILCRA (PA_BCR + 0)
64#define BCR_ILCRB (PA_BCR + 2)
65#define BCR_ILCRC (PA_BCR + 4)
66#define BCR_ILCRD (PA_BCR + 6)
67#define BCR_ILCRE (PA_BCR + 8)
68#define BCR_ILCRF (PA_BCR + 10)
69#define BCR_ILCRG (PA_BCR + 12)
70
71#if defined(CONFIG_CPU_SUBTYPE_SH7705)
72#define IRQ_STNIC 12
73#define IRQ_CFCARD 14
74#else
75#define IRQ_STNIC 10
76#define IRQ_CFCARD 7
77#endif
78
79/* SH Ether support (SH7710/SH7712) */
80/* Base address */
81#define SH_ETH0_BASE 0xA7000000
82#define SH_ETH1_BASE 0xA7000400
83/* PHY ID */
84#if defined(CONFIG_CPU_SUBTYPE_SH7710)
85# define PHY_ID 0x00
86#elif defined(CONFIG_CPU_SUBTYPE_SH7712)
87# define PHY_ID 0x01
88#endif
89/* Ether IRQ */
90#define SH_ETH0_IRQ 80
91#define SH_ETH1_IRQ 81
92#define SH_TSU_IRQ 82
93
94void init_se_IRQ(void);
95
96#define __IO_PREFIX se
97#include <asm/io_generic.h>
98
99#endif /* __ASM_SH_HITACHI_SE_H */
diff --git a/arch/sh/include/mach-se/mach/se7206.h b/arch/sh/include/mach-se/mach/se7206.h
new file mode 100644
index 000000000000..698eb80389ab
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7206.h
@@ -0,0 +1,13 @@
1#ifndef __ASM_SH_SE7206_H
2#define __ASM_SH_SE7206_H
3
4#define PA_SMSC 0x30000000
5#define PA_MRSHPC 0x34000000
6#define PA_LED 0x31400000
7
8void init_se7206_IRQ(void);
9
10#define __IO_PREFIX se7206
11#include <asm/io_generic.h>
12
13#endif /* __ASM_SH_SE7206_H */
diff --git a/arch/sh/include/mach-se/mach/se7343.h b/arch/sh/include/mach-se/mach/se7343.h
new file mode 100644
index 000000000000..98458460e632
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7343.h
@@ -0,0 +1,149 @@
1#ifndef __ASM_SH_HITACHI_SE7343_H
2#define __ASM_SH_HITACHI_SE7343_H
3
4/*
5 * include/asm-sh/se/se7343.h
6 *
7 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
8 *
9 * SH-Mobile SolutionEngine 7343 support
10 */
11
12/* Box specific addresses. */
13
14/* Area 0 */
15#define PA_ROM 0x00000000 /* EPROM */
16#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
17#define PA_FROM 0x00400000 /* Flash ROM */
18#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
19#define PA_SRAM 0x00800000 /* SRAM */
20#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
21/* Area 1 */
22#define PA_EXT1 0x04000000
23#define PA_EXT1_SIZE 0x04000000
24/* Area 2 */
25#define PA_EXT2 0x08000000
26#define PA_EXT2_SIZE 0x04000000
27/* Area 3 */
28#define PA_SDRAM 0x0c000000
29#define PA_SDRAM_SIZE 0x04000000
30/* Area 4 */
31#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */
32#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */
33#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */
34#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */
35#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */
36#define MRSHPC_OPTION (PA_MRSHPC + 6)
37#define MRSHPC_CSR (PA_MRSHPC + 8)
38#define MRSHPC_ISR (PA_MRSHPC + 10)
39#define MRSHPC_ICR (PA_MRSHPC + 12)
40#define MRSHPC_CPWCR (PA_MRSHPC + 14)
41#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
42#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
43#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
44#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
45#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
46#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
47#define MRSHPC_CDCR (PA_MRSHPC + 28)
48#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
49#define PA_LED 0xb0C00000 /* LED */
50#define LED_SHIFT 0
51#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
52#define PA_CPLD_MODESET 0xb1400004 /* CPLD Mode set register */
53#define PA_CPLD_ST 0xb1400008 /* CPLD Interrupt status register */
54#define PA_CPLD_IMSK 0xb140000a /* CPLD Interrupt mask register */
55/* Area 5 */
56#define PA_EXT5 0x14000000
57#define PA_EXT5_SIZE 0x04000000
58/* Area 6 */
59#define PA_LCD1 0xb8000000
60#define PA_LCD2 0xb8800000
61
62#define PORT_PACR 0xA4050100
63#define PORT_PBCR 0xA4050102
64#define PORT_PCCR 0xA4050104
65#define PORT_PDCR 0xA4050106
66#define PORT_PECR 0xA4050108
67#define PORT_PFCR 0xA405010A
68#define PORT_PGCR 0xA405010C
69#define PORT_PHCR 0xA405010E
70#define PORT_PJCR 0xA4050110
71#define PORT_PKCR 0xA4050112
72#define PORT_PLCR 0xA4050114
73#define PORT_PMCR 0xA4050116
74#define PORT_PNCR 0xA4050118
75#define PORT_PQCR 0xA405011A
76#define PORT_PRCR 0xA405011C
77#define PORT_PSCR 0xA405011E
78#define PORT_PTCR 0xA4050140
79#define PORT_PUCR 0xA4050142
80#define PORT_PVCR 0xA4050144
81#define PORT_PWCR 0xA4050146
82#define PORT_PYCR 0xA4050148
83#define PORT_PZCR 0xA405014A
84
85#define PORT_PSELA 0xA405014C
86#define PORT_PSELB 0xA405014E
87#define PORT_PSELC 0xA4050150
88#define PORT_PSELD 0xA4050152
89#define PORT_PSELE 0xA4050154
90
91#define PORT_HIZCRA 0xA4050156
92#define PORT_HIZCRB 0xA4050158
93#define PORT_HIZCRC 0xA405015C
94
95#define PORT_DRVCR 0xA4050180
96
97#define PORT_PADR 0xA4050120
98#define PORT_PBDR 0xA4050122
99#define PORT_PCDR 0xA4050124
100#define PORT_PDDR 0xA4050126
101#define PORT_PEDR 0xA4050128
102#define PORT_PFDR 0xA405012A
103#define PORT_PGDR 0xA405012C
104#define PORT_PHDR 0xA405012E
105#define PORT_PJDR 0xA4050130
106#define PORT_PKDR 0xA4050132
107#define PORT_PLDR 0xA4050134
108#define PORT_PMDR 0xA4050136
109#define PORT_PNDR 0xA4050138
110#define PORT_PQDR 0xA405013A
111#define PORT_PRDR 0xA405013C
112#define PORT_PTDR 0xA4050160
113#define PORT_PUDR 0xA4050162
114#define PORT_PVDR 0xA4050164
115#define PORT_PWDR 0xA4050166
116#define PORT_PYDR 0xA4050168
117
118#define FPGA_IN 0xb1400000
119#define FPGA_OUT 0xb1400002
120
121#define __IO_PREFIX sh7343se
122#include <asm/io_generic.h>
123
124#define IRQ0_IRQ 32
125#define IRQ1_IRQ 33
126#define IRQ4_IRQ 36
127#define IRQ5_IRQ 37
128
129#define SE7343_FPGA_IRQ_MRSHPC0 0
130#define SE7343_FPGA_IRQ_MRSHPC1 1
131#define SE7343_FPGA_IRQ_MRSHPC2 2
132#define SE7343_FPGA_IRQ_MRSHPC3 3
133#define SE7343_FPGA_IRQ_SMC 6 /* EXT_IRQ2 */
134#define SE7343_FPGA_IRQ_USB 8
135
136#define SE7343_FPGA_IRQ_NR 11
137#define SE7343_FPGA_IRQ_BASE 120
138
139#define MRSHPC_IRQ3 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC3)
140#define MRSHPC_IRQ2 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC2)
141#define MRSHPC_IRQ1 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC1)
142#define MRSHPC_IRQ0 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC0)
143#define SMC_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_SMC)
144#define USB_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_USB)
145
146/* arch/sh/boards/se/7343/irq.c */
147void init_7343se_IRQ(void);
148
149#endif /* __ASM_SH_HITACHI_SE7343_H */
diff --git a/arch/sh/include/mach-se/mach/se7721.h b/arch/sh/include/mach-se/mach/se7721.h
new file mode 100644
index 000000000000..b957f6041193
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7721.h
@@ -0,0 +1,70 @@
1/*
2 * Copyright (C) 2008 Renesas Solutions Corp.
3 *
4 * Hitachi UL SolutionEngine 7721 Support.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 */
11
12#ifndef __ASM_SH_SE7721_H
13#define __ASM_SH_SE7721_H
14#include <asm/addrspace.h>
15
16/* Box specific addresses. */
17#define SE_AREA0_WIDTH 2 /* Area0: 32bit */
18#define PA_ROM 0xa0000000 /* EPROM */
19#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
20#define PA_FROM 0xa1000000 /* Flash-ROM */
21#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
22#define PA_EXT1 0xa4000000
23#define PA_EXT1_SIZE 0x04000000
24#define PA_SDRAM 0xaC000000 /* SDRAM(Area3) 64MB */
25#define PA_SDRAM_SIZE 0x04000000
26
27#define PA_EXT4 0xb0000000
28#define PA_EXT4_SIZE 0x04000000
29
30#define PA_PERIPHERAL 0xB8000000
31
32#define PA_PCIC PA_PERIPHERAL
33#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0)
34#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000)
35#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000)
36#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000)
37#define MRSHPC_OPTION (PA_MRSHPC + 6)
38#define MRSHPC_CSR (PA_MRSHPC + 8)
39#define MRSHPC_ISR (PA_MRSHPC + 10)
40#define MRSHPC_ICR (PA_MRSHPC + 12)
41#define MRSHPC_CPWCR (PA_MRSHPC + 14)
42#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
43#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
44#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
45#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
46#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
47#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
48#define MRSHPC_CDCR (PA_MRSHPC + 28)
49#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
50
51#define PA_LED 0xB6800000 /* 8bit LED */
52#define PA_FPGA 0xB7000000 /* FPGA base address */
53
54#define MRSHPC_IRQ0 10
55
56#define FPGA_ILSR1 (PA_FPGA + 0x02)
57#define FPGA_ILSR2 (PA_FPGA + 0x03)
58#define FPGA_ILSR3 (PA_FPGA + 0x04)
59#define FPGA_ILSR4 (PA_FPGA + 0x05)
60#define FPGA_ILSR5 (PA_FPGA + 0x06)
61#define FPGA_ILSR6 (PA_FPGA + 0x07)
62#define FPGA_ILSR7 (PA_FPGA + 0x08)
63#define FPGA_ILSR8 (PA_FPGA + 0x09)
64
65void init_se7721_IRQ(void);
66
67#define __IO_PREFIX se7721
68#include <asm/io_generic.h>
69
70#endif /* __ASM_SH_SE7721_H */
diff --git a/arch/sh/include/mach-se/mach/se7722.h b/arch/sh/include/mach-se/mach/se7722.h
new file mode 100644
index 000000000000..e971d9a82f4a
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7722.h
@@ -0,0 +1,112 @@
1#ifndef __ASM_SH_SE7722_H
2#define __ASM_SH_SE7722_H
3
4/*
5 * linux/include/asm-sh/se7722.h
6 *
7 * Copyright (C) 2007 Nobuhiro Iwamatsu
8 *
9 * Hitachi UL SolutionEngine 7722 Support.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 *
15 */
16#include <asm/addrspace.h>
17
18/* Box specific addresses. */
19#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
20#define PA_ROM 0xa0000000 /* EPROM */
21#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
22#define PA_FROM 0xa1000000 /* Flash-ROM */
23#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
24#define PA_EXT1 0xa4000000
25#define PA_EXT1_SIZE 0x04000000
26#define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */
27#define PA_SDRAM_SIZE 0x04000000
28
29#define PA_EXT4 0xb0000000
30#define PA_EXT4_SIZE 0x04000000
31
32#define PA_PERIPHERAL 0xB0000000
33
34#define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */
35#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */
36#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */
37#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */
38#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) /* MR-SHPC-01 I/O window base */
39#define MRSHPC_OPTION (PA_MRSHPC + 6)
40#define MRSHPC_CSR (PA_MRSHPC + 8)
41#define MRSHPC_ISR (PA_MRSHPC + 10)
42#define MRSHPC_ICR (PA_MRSHPC + 12)
43#define MRSHPC_CPWCR (PA_MRSHPC + 14)
44#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
45#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
46#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
47#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
48#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
49#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
50#define MRSHPC_CDCR (PA_MRSHPC + 28)
51#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
52
53#define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */
54#define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */
55
56#define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */
57/* GPIO */
58#define FPGA_IN 0xb1840000UL
59#define FPGA_OUT 0xb1840004UL
60
61#define PORT_PECR 0xA4050108UL
62#define PORT_PJCR 0xA4050110UL
63#define PORT_PSELD 0xA4050154UL
64#define PORT_PSELB 0xA4050150UL
65
66#define PORT_PSELC 0xA4050152UL
67#define PORT_PKCR 0xA4050112UL
68#define PORT_PHCR 0xA405010EUL
69#define PORT_PLCR 0xA4050114UL
70#define PORT_PMCR 0xA4050116UL
71#define PORT_PRCR 0xA405011CUL
72#define PORT_PXCR 0xA4050148UL
73#define PORT_PSELA 0xA405014EUL
74#define PORT_PYCR 0xA405014AUL
75#define PORT_PZCR 0xA405014CUL
76#define PORT_HIZCRA 0xA4050158UL
77#define PORT_HIZCRC 0xA405015CUL
78
79/* IRQ */
80#define IRQ0_IRQ 32
81#define IRQ1_IRQ 33
82
83#define IRQ01_MODE 0xb1800000
84#define IRQ01_STS 0xb1800004
85#define IRQ01_MASK 0xb1800008
86
87/* Bits in IRQ01_* registers */
88
89#define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */
90#define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */
91#define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */
92#define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */
93#define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */
94#define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */
95
96#define SE7722_FPGA_IRQ_NR 6
97#define SE7722_FPGA_IRQ_BASE 110
98
99#define MRSHPC_IRQ3 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC3)
100#define MRSHPC_IRQ2 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC2)
101#define MRSHPC_IRQ1 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC1)
102#define MRSHPC_IRQ0 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC0)
103#define SMC_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_SMC)
104#define USB_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_USB)
105
106/* arch/sh/boards/se/7722/irq.c */
107void init_se7722_IRQ(void);
108
109#define __IO_PREFIX se7722
110#include <asm/io_generic.h>
111
112#endif /* __ASM_SH_SE7722_H */
diff --git a/arch/sh/include/mach-se/mach/se7751.h b/arch/sh/include/mach-se/mach/se7751.h
new file mode 100644
index 000000000000..b36792ac5d66
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7751.h
@@ -0,0 +1,73 @@
1#ifndef __ASM_SH_HITACHI_7751SE_H
2#define __ASM_SH_HITACHI_7751SE_H
3
4/*
5 * linux/include/asm-sh/hitachi_7751se.h
6 *
7 * Copyright (C) 2000 Kazumoto Kojima
8 *
9 * Hitachi SolutionEngine support
10
11 * Modified for 7751 Solution Engine by
12 * Ian da Silva and Jeremy Siegel, 2001.
13 */
14
15/* Box specific addresses. */
16
17#define PA_ROM 0x00000000 /* EPROM */
18#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
19#define PA_FROM 0x01000000 /* EPROM */
20#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
21#define PA_EXT1 0x04000000
22#define PA_EXT1_SIZE 0x04000000
23#define PA_EXT2 0x08000000
24#define PA_EXT2_SIZE 0x04000000
25#define PA_SDRAM 0x0c000000
26#define PA_SDRAM_SIZE 0x04000000
27
28#define PA_EXT4 0x12000000
29#define PA_EXT4_SIZE 0x02000000
30#define PA_EXT5 0x14000000
31#define PA_EXT5_SIZE 0x04000000
32#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
33
34#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */
35#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */
36#define PA_LED 0xba000000 /* LED */
37#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */
38
39#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
40#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
41#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
42#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
43#define MRSHPC_MODE (PA_MRSHPC + 4)
44#define MRSHPC_OPTION (PA_MRSHPC + 6)
45#define MRSHPC_CSR (PA_MRSHPC + 8)
46#define MRSHPC_ISR (PA_MRSHPC + 10)
47#define MRSHPC_ICR (PA_MRSHPC + 12)
48#define MRSHPC_CPWCR (PA_MRSHPC + 14)
49#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
50#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
51#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
52#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
53#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
54#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
55#define MRSHPC_CDCR (PA_MRSHPC + 28)
56#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
57
58#define BCR_ILCRA (PA_BCR + 0)
59#define BCR_ILCRB (PA_BCR + 2)
60#define BCR_ILCRC (PA_BCR + 4)
61#define BCR_ILCRD (PA_BCR + 6)
62#define BCR_ILCRE (PA_BCR + 8)
63#define BCR_ILCRF (PA_BCR + 10)
64#define BCR_ILCRG (PA_BCR + 12)
65
66#define IRQ_79C973 13
67
68void init_7751se_IRQ(void);
69
70#define __IO_PREFIX sh7751se
71#include <asm/io_generic.h>
72
73#endif /* __ASM_SH_HITACHI_7751SE_H */
diff --git a/arch/sh/include/mach-se/mach/se7780.h b/arch/sh/include/mach-se/mach/se7780.h
new file mode 100644
index 000000000000..40e9b41458cd
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7780.h
@@ -0,0 +1,108 @@
1#ifndef __ASM_SH_SE7780_H
2#define __ASM_SH_SE7780_H
3
4/*
5 * linux/include/asm-sh/se7780.h
6 *
7 * Copyright (C) 2006,2007 Nobuhiro Iwamatsu
8 *
9 * Hitachi UL SolutionEngine 7780 Support.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <asm/addrspace.h>
16
17/* Box specific addresses. */
18#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
19#define PA_ROM 0xa0000000 /* EPROM */
20#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
21#define PA_FROM 0xa1000000 /* Flash-ROM */
22#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
23#define PA_EXT1 0xa4000000
24#define PA_EXT1_SIZE 0x04000000
25#define PA_SM501 PA_EXT1 /* Graphic IC (SM501) */
26#define PA_SM501_SIZE PA_EXT1_SIZE /* Graphic IC (SM501) */
27#define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */
28#define PA_SDRAM_SIZE 0x08000000
29
30#define PA_EXT4 0xb0000000
31#define PA_EXT4_SIZE 0x04000000
32#define PA_EXT_FLASH PA_EXT4 /* Expansion Flash-ROM */
33
34#define PA_PERIPHERAL PA_AREA6_IO /* SW6-6=ON */
35
36#define PA_LAN (PA_PERIPHERAL + 0) /* SMC LAN91C111 */
37#define PA_LED_DISP (PA_PERIPHERAL + 0x02000000) /* 8words LED Display */
38#define DISP_CHAR_RAM (7 << 3)
39#define DISP_SEL0_ADDR (DISP_CHAR_RAM + 0)
40#define DISP_SEL1_ADDR (DISP_CHAR_RAM + 1)
41#define DISP_SEL2_ADDR (DISP_CHAR_RAM + 2)
42#define DISP_SEL3_ADDR (DISP_CHAR_RAM + 3)
43#define DISP_SEL4_ADDR (DISP_CHAR_RAM + 4)
44#define DISP_SEL5_ADDR (DISP_CHAR_RAM + 5)
45#define DISP_SEL6_ADDR (DISP_CHAR_RAM + 6)
46#define DISP_SEL7_ADDR (DISP_CHAR_RAM + 7)
47
48#define DISP_UDC_RAM (5 << 3)
49#define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */
50
51/* FPGA register address and bit */
52#define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */
53#define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */
54#define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */
55#define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */
56#define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */
57#define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */
58#define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */
59#define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */
60#define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */
61#define FPGA_INTSTS1 (PA_FPGA + 18) /* Interrupt status register 1 */
62#define FPGA_INTSTS2 (PA_FPGA + 20) /* Interrupt status register 2 */
63#define FPGA_REQSEL (PA_FPGA + 22) /* REQ/GNT select register */
64#define FPGA_DBG_LED (PA_FPGA + 32) /* Debug LED(D-LED[8:1] */
65#define PA_LED FPGA_DBG_LED
66#define FPGA_IVDRID (PA_FPGA + 36) /* iVDR ID Register */
67#define FPGA_IVDRPW (PA_FPGA + 38) /* iVDR Power ON Register */
68#define FPGA_MMCID (PA_FPGA + 40) /* MMC ID Register */
69
70/* FPGA INTSEL position */
71/* INTSEL1 */
72#define IRQPOS_SMC91CX (0 * 4)
73#define IRQPOS_SM501 (1 * 4)
74/* INTSEL2 */
75#define IRQPOS_EXTINT1 (0 * 4)
76#define IRQPOS_EXTINT2 (1 * 4)
77#define IRQPOS_EXTINT3 (2 * 4)
78#define IRQPOS_EXTINT4 (3 * 4)
79/* INTSEL3 */
80#define IRQPOS_PCCPW (0 * 4)
81
82/* IDE interrupt */
83#define IRQ_IDE0 67 /* iVDR */
84
85/* SMC interrupt */
86#define SMC_IRQ 8
87
88/* SM501 interrupt */
89#define SM501_IRQ 0
90
91/* interrupt pin */
92#define IRQPIN_EXTINT1 0 /* IRQ0 pin */
93#define IRQPIN_EXTINT2 1 /* IRQ1 pin */
94#define IRQPIN_EXTINT3 2 /* IRQ2 pin */
95#define IRQPIN_SMC91CX 3 /* IRQ3 pin */
96#define IRQPIN_EXTINT4 4 /* IRQ4 pin */
97#define IRQPIN_PCC0 5 /* IRQ5 pin */
98#define IRQPIN_PCC2 6 /* IRQ6 pin */
99#define IRQPIN_SM501 7 /* IRQ7 pin */
100#define IRQPIN_PCCPW 7 /* IRQ7 pin */
101
102/* arch/sh/boards/se/7780/irq.c */
103void init_se7780_IRQ(void);
104
105#define __IO_PREFIX se7780
106#include <asm/io_generic.h>
107
108#endif /* __ASM_SH_SE7780_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 17:16:47 -0500