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authorPaul Mundt <lethal@linux-sh.org>2010-01-20 01:08:36 -0500
committerPaul Mundt <lethal@linux-sh.org>2010-01-20 01:08:36 -0500
commitefd590d57a5edddabaaf4cfaf532c0f674193b81 (patch)
tree62832f461bcadfe662eb6cf6bb1e74fad90adca6 /arch/sh/include/mach-sdk7786
parentbdc27300f5718626a3817e6478e339f6cca6b994 (diff)
sh: mach-sdk7786: FPGA updates.
This does a bit of refactoring of the FPGA management code. The primary FPGA initialization is moved out to its own file in preparation for implementing some of the more complex capabilities, a complete set of register definitions is provided, and all of the existing users in the board code are moved over to use the new interface instead of setting up overlapping mappings. This also corrects the FPGA size, which previously was chomped off at the SDIF control register. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/mach-sdk7786')
-rw-r--r--arch/sh/include/mach-sdk7786/mach/fpga.h112
1 files changed, 112 insertions, 0 deletions
diff --git a/arch/sh/include/mach-sdk7786/mach/fpga.h b/arch/sh/include/mach-sdk7786/mach/fpga.h
new file mode 100644
index 000000000000..a85d9853d34f
--- /dev/null
+++ b/arch/sh/include/mach-sdk7786/mach/fpga.h
@@ -0,0 +1,112 @@
1#ifndef __MACH_SDK7786_FPGA_H
2#define __MACH_SDK7786_FPGA_H
3
4#include <linux/io.h>
5#include <linux/types.h>
6#include <linux/bitops.h>
7
8#define SRSTR 0x000
9#define INTASR 0x010
10#define INTAMR 0x020
11#define MODSWR 0x030
12#define INTTESTR 0x040
13#define SYSSR 0x050
14#define NRGPR 0x060
15#define NMISR 0x070
16
17#define NMIMR 0x080
18#define NMIMR_MAN_NMIM BIT(0) /* Manual NMI mask */
19#define NMIMR_AUX_NMIM BIT(1) /* Auxiliary NMI mask */
20
21#define INTBSR 0x090
22#define INTBMR 0x0a0
23#define USRLEDR 0x0b0
24#define MAPSWR 0x0c0
25#define FPGAVR 0x0d0
26#define FPGADR 0x0e0
27#define PCBRR 0x0f0
28#define RSR 0x100
29#define EXTASR 0x110
30#define SPCAR 0x120
31#define INTMSR 0x130
32#define PCIECR 0x140
33#define FAER 0x150
34#define USRGPIR 0x160
35/* 0x170 reserved */
36#define LCLASR 0x180
37
38#define SBCR 0x190
39#define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */
40#define SCBR_I2CCEN BIT(1) /* CPU I2C master enable */
41
42#define PWRCR 0x1a0
43#define SPCBR 0x1b0
44#define SPICR 0x1c0
45#define SPIDR 0x1d0
46#define I2CCR 0x1e0
47#define I2CDR 0x1f0
48#define FPGACR 0x200
49#define IASELR1 0x210
50#define IASELR2 0x220
51#define IASELR3 0x230
52#define IASELR4 0x240
53#define IASELR5 0x250
54#define IASELR6 0x260
55#define IASELR7 0x270
56#define IASELR8 0x280
57#define IASELR9 0x290
58#define IASELR10 0x2a0
59#define IASELR11 0x2b0
60#define IASELR12 0x2c0
61#define IASELR13 0x2d0
62#define IASELR14 0x2e0
63#define IASELR15 0x2f0
64/* 0x300 reserved */
65#define IBSELR1 0x310
66#define IBSELR2 0x320
67#define IBSELR3 0x330
68#define IBSELR4 0x340
69#define IBSELR5 0x350
70#define IBSELR6 0x360
71#define IBSELR7 0x370
72#define IBSELR8 0x380
73#define IBSELR9 0x390
74#define IBSELR10 0x3a0
75#define IBSELR11 0x3b0
76#define IBSELR12 0x3c0
77#define IBSELR13 0x3d0
78#define IBSELR14 0x3e0
79#define IBSELR15 0x3f0
80#define USRACR 0x400
81#define BEEPR 0x410
82#define USRLCDR 0x420
83#define SMBCR 0x430
84#define SMBDR 0x440
85#define USBCR 0x450
86#define AMSR 0x460
87#define ACCR 0x470
88#define SDIFCR 0x480
89
90/* arch/sh/boards/mach-sdk7786/fpga.c */
91extern void __iomem *sdk7786_fpga_base;
92extern void sdk7786_fpga_init(void);
93
94#define SDK7786_FPGA_REGADDR(reg) (sdk7786_fpga_base + (reg))
95
96/*
97 * A convenience wrapper from register offset to internal I2C address,
98 * when the FPGA is in I2C slave mode.
99 */
100#define SDK7786_FPGA_I2CADDR(reg) ((reg) >> 3)
101
102static inline u16 fpga_read_reg(unsigned int reg)
103{
104 return ioread16(sdk7786_fpga_base + reg);
105}
106
107static inline void fpga_write_reg(u16 val, unsigned int reg)
108{
109 iowrite16(val, sdk7786_fpga_base + reg);
110}
111
112#endif /* __MACH_SDK7786_FPGA_H */