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authorPaul Mundt <lethal@linux-sh.org>2008-07-28 19:09:44 -0400
committerPaul Mundt <lethal@linux-sh.org>2008-07-28 19:09:44 -0400
commitf15cbe6f1a4b4d9df59142fc8e4abb973302cf44 (patch)
tree774d7b11abaaf33561ab8268bf51ddd9ceb79025 /arch/sh/include/mach-dreamcast
parent25326277d8d1393d1c66240e6255aca780f9e3eb (diff)
sh: migrate to arch/sh/include/
This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac. Most of the moving about was done with Sam's directions at: http://marc.info/?l=linux-sh&m=121724823706062&w=2 with subsequent hacking and fixups entirely my fault. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/mach-dreamcast')
-rw-r--r--arch/sh/include/mach-dreamcast/mach/dma.h34
-rw-r--r--arch/sh/include/mach-dreamcast/mach/maple.h37
-rw-r--r--arch/sh/include/mach-dreamcast/mach/pci.h25
-rw-r--r--arch/sh/include/mach-dreamcast/mach/sysasic.h43
4 files changed, 139 insertions, 0 deletions
diff --git a/arch/sh/include/mach-dreamcast/mach/dma.h b/arch/sh/include/mach-dreamcast/mach/dma.h
new file mode 100644
index 000000000000..ddd68e788705
--- /dev/null
+++ b/arch/sh/include/mach-dreamcast/mach/dma.h
@@ -0,0 +1,34 @@
1/*
2 * include/asm-sh/dreamcast/dma.h
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_SH_DREAMCAST_DMA_H
11#define __ASM_SH_DREAMCAST_DMA_H
12
13/* Number of DMA channels */
14#define ONCHIP_NR_DMA_CHANNELS 4
15#define G2_NR_DMA_CHANNELS 4
16#define PVR2_NR_DMA_CHANNELS 1
17
18/* Channels for cascading */
19#define PVR2_CASCADE_CHAN 2
20#define G2_CASCADE_CHAN 3
21
22/* PVR2 DMA Registers */
23#define PVR2_DMA_BASE 0xa05f6800
24#define PVR2_DMA_ADDR (PVR2_DMA_BASE + 0)
25#define PVR2_DMA_COUNT (PVR2_DMA_BASE + 4)
26#define PVR2_DMA_MODE (PVR2_DMA_BASE + 8)
27#define PVR2_DMA_LMMODE0 (PVR2_DMA_BASE + 132)
28#define PVR2_DMA_LMMODE1 (PVR2_DMA_BASE + 136)
29
30/* G2 DMA Register */
31#define G2_DMA_BASE 0xa05f7800
32
33#endif /* __ASM_SH_DREAMCAST_DMA_H */
34
diff --git a/arch/sh/include/mach-dreamcast/mach/maple.h b/arch/sh/include/mach-dreamcast/mach/maple.h
new file mode 100644
index 000000000000..51f6a87f1f11
--- /dev/null
+++ b/arch/sh/include/mach-dreamcast/mach/maple.h
@@ -0,0 +1,37 @@
1#ifndef __ASM_MAPLE_H
2#define __ASM_MAPLE_H
3
4#define MAPLE_PORTS 4
5#define MAPLE_PNP_INTERVAL HZ
6#define MAPLE_MAXPACKETS 8
7#define MAPLE_DMA_ORDER 14
8#define MAPLE_DMA_SIZE (1 << MAPLE_DMA_ORDER)
9#define MAPLE_DMA_PAGES ((MAPLE_DMA_ORDER > PAGE_SHIFT) ? \
10 MAPLE_DMA_ORDER - PAGE_SHIFT : 0)
11
12/* Maple Bus registers */
13#define MAPLE_BASE 0xa05f6c00
14#define MAPLE_DMAADDR (MAPLE_BASE+0x04)
15#define MAPLE_TRIGTYPE (MAPLE_BASE+0x10)
16#define MAPLE_ENABLE (MAPLE_BASE+0x14)
17#define MAPLE_STATE (MAPLE_BASE+0x18)
18#define MAPLE_SPEED (MAPLE_BASE+0x80)
19#define MAPLE_RESET (MAPLE_BASE+0x8c)
20
21#define MAPLE_MAGIC 0x6155404f
22#define MAPLE_2MBPS 0
23#define MAPLE_TIMEOUT(n) ((n)<<15)
24
25/* Function codes */
26#define MAPLE_FUNC_CONTROLLER 0x001
27#define MAPLE_FUNC_MEMCARD 0x002
28#define MAPLE_FUNC_LCD 0x004
29#define MAPLE_FUNC_CLOCK 0x008
30#define MAPLE_FUNC_MICROPHONE 0x010
31#define MAPLE_FUNC_ARGUN 0x020
32#define MAPLE_FUNC_KEYBOARD 0x040
33#define MAPLE_FUNC_LIGHTGUN 0x080
34#define MAPLE_FUNC_PURUPURU 0x100
35#define MAPLE_FUNC_MOUSE 0x200
36
37#endif /* __ASM_MAPLE_H */
diff --git a/arch/sh/include/mach-dreamcast/mach/pci.h b/arch/sh/include/mach-dreamcast/mach/pci.h
new file mode 100644
index 000000000000..9264ff46c63e
--- /dev/null
+++ b/arch/sh/include/mach-dreamcast/mach/pci.h
@@ -0,0 +1,25 @@
1/*
2 * include/asm-sh/dreamcast/pci.h
3 *
4 * Copyright (C) 2001, 2002 M. R. Brown
5 * Copyright (C) 2002, 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_SH_DREAMCAST_PCI_H
12#define __ASM_SH_DREAMCAST_PCI_H
13
14#include <mach/sysasic.h>
15
16#define GAPSPCI_REGS 0x01001400
17#define GAPSPCI_DMA_BASE 0x01840000
18#define GAPSPCI_DMA_SIZE 32768
19#define GAPSPCI_BBA_CONFIG 0x01001600
20#define GAPSPCI_BBA_CONFIG_SIZE 0x2000
21
22#define GAPSPCI_IRQ HW_EVENT_EXTERNAL
23
24#endif /* __ASM_SH_DREAMCAST_PCI_H */
25
diff --git a/arch/sh/include/mach-dreamcast/mach/sysasic.h b/arch/sh/include/mach-dreamcast/mach/sysasic.h
new file mode 100644
index 000000000000..f33426608a87
--- /dev/null
+++ b/arch/sh/include/mach-dreamcast/mach/sysasic.h
@@ -0,0 +1,43 @@
1/* include/asm-sh/dreamcast/sysasic.h
2 *
3 * Definitions for the Dreamcast System ASIC and related peripherals.
4 *
5 * Copyright (c) 2001 M. R. Brown <mrbrown@linuxdc.org>
6 * Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org>
7 *
8 * This file is part of the LinuxDC project (www.linuxdc.org)
9 *
10 * Released under the terms of the GNU GPL v2.0.
11 *
12 */
13#ifndef __ASM_SH_DREAMCAST_SYSASIC_H
14#define __ASM_SH_DREAMCAST_SYSASIC_H
15
16#include <asm/irq.h>
17
18/* Hardware events -
19
20 Each of these events correspond to a bit within the Event Mask Registers/
21 Event Status Registers. Because of the virtual IRQ numbering scheme, a
22 base offset must be used when calculating the virtual IRQ that each event
23 takes.
24*/
25
26#define HW_EVENT_IRQ_BASE 48
27
28/* IRQ 13 */
29#define HW_EVENT_VSYNC (HW_EVENT_IRQ_BASE + 5) /* VSync */
30#define HW_EVENT_MAPLE_DMA (HW_EVENT_IRQ_BASE + 12) /* Maple DMA complete */
31#define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */
32#define HW_EVENT_G2_DMA (HW_EVENT_IRQ_BASE + 15) /* G2 DMA complete */
33#define HW_EVENT_PVR2_DMA (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */
34
35/* IRQ 11 */
36#define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */
37#define HW_EVENT_AICA_SYS (HW_EVENT_IRQ_BASE + 33) /* AICA-related */
38#define HW_EVENT_EXTERNAL (HW_EVENT_IRQ_BASE + 35) /* Ext. (expansion) */
39
40#define HW_EVENT_IRQ_MAX (HW_EVENT_IRQ_BASE + 95)
41
42#endif /* __ASM_SH_DREAMCAST_SYSASIC_H */
43