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authorPaul Mundt <lethal@linux-sh.org>2012-05-19 05:06:12 -0400
committerPaul Mundt <lethal@linux-sh.org>2012-05-19 05:06:12 -0400
commit0c6012313c22154367c36cecbc949d0fc120042e (patch)
tree993f6bb6224062d78145a1e553b2cd5ef45f3846 /arch/sh/include/cpu-sh4
parentd8fd35fc586f74b2defe011d3a2bfb507871a407 (diff)
sh: Move sh4a dma header from cpu-sh4 to cpu-sh4a.
cpu-sh4a headers take priority over cpu-sh4 ones by virtue of the build system, there's no need to try and mingle sh4a stuff in cpu-sh4. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/cpu-sh4')
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-sh4a.h85
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma.h11
2 files changed, 1 insertions, 95 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
deleted file mode 100644
index f280410c93ae..000000000000
--- a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
+++ /dev/null
@@ -1,85 +0,0 @@
1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
2#define __ASM_SH_CPU_SH4_DMA_SH7780_H
3
4#include <linux/sh_intc.h>
5
6#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
7 defined(CONFIG_CPU_SUBTYPE_SH7730)
8#define DMTE0_IRQ evt2irq(0x800)
9#define DMTE4_IRQ evt2irq(0xb80)
10#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
11#define SH_DMAC_BASE0 0xFE008020
12#define SH_DMARS_BASE0 0xFE009000
13#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
14#define DMTE0_IRQ evt2irq(0x800)
15#define DMTE4_IRQ evt2irq(0xb80)
16#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17#define SH_DMAC_BASE0 0xFE008020
18#define SH_DMARS_BASE0 0xFE009000
19#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
20 defined(CONFIG_CPU_SUBTYPE_SH7764)
21#define DMTE0_IRQ evt2irq(0x640)
22#define DMTE4_IRQ evt2irq(0x780)
23#define DMAE0_IRQ evt2irq(0x6c0)
24#define SH_DMAC_BASE0 0xFF608020
25#define SH_DMARS_BASE0 0xFF609000
26#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
27#define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/
28#define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */
29#define DMTE6_IRQ evt2irq(0x700)
30#define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */
31#define DMTE9_IRQ evt2irq(0x760)
32#define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */
33#define DMTE11_IRQ evt2irq(0xb20)
34#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
35#define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/
36#define SH_DMAC_BASE0 0xFE008020
37#define SH_DMAC_BASE1 0xFDC08020
38#define SH_DMARS_BASE0 0xFDC09000
39#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
40#define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/
41#define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */
42#define DMTE6_IRQ evt2irq(0x700)
43#define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */
44#define DMTE9_IRQ evt2irq(0x760)
45#define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */
46#define DMTE11_IRQ evt2irq(0xb20)
47#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
48#define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/
49#define SH_DMAC_BASE0 0xFE008020
50#define SH_DMAC_BASE1 0xFDC08020
51#define SH_DMARS_BASE0 0xFE009000
52#define SH_DMARS_BASE1 0xFDC09000
53#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
54#define DMTE0_IRQ evt2irq(0x640)
55#define DMTE4_IRQ evt2irq(0x780)
56#define DMTE6_IRQ evt2irq(0x7c0)
57#define DMTE8_IRQ evt2irq(0xd80)
58#define DMTE9_IRQ evt2irq(0xda0)
59#define DMTE10_IRQ evt2irq(0xdc0)
60#define DMTE11_IRQ evt2irq(0xde0)
61#define DMAE0_IRQ evt2irq(0x6c0) /* DMA Error IRQ */
62#define SH_DMAC_BASE0 0xFC808020
63#define SH_DMAC_BASE1 0xFC818020
64#define SH_DMARS_BASE0 0xFC809000
65#else /* SH7785 */
66#define DMTE0_IRQ evt2irq(0x620)
67#define DMTE4_IRQ evt2irq(0x6a0)
68#define DMTE6_IRQ evt2irq(0x880)
69#define DMTE8_IRQ evt2irq(0x8c0)
70#define DMTE9_IRQ evt2irq(0x8e0)
71#define DMTE10_IRQ evt2irq(0x900)
72#define DMTE11_IRQ evt2irq(0x920)
73#define DMAE0_IRQ evt2irq(0x6e0) /* DMA Error IRQ0 */
74#define DMAE1_IRQ evt2irq(0x940) /* DMA Error IRQ1 */
75#define SH_DMAC_BASE0 0xFC808020
76#define SH_DMAC_BASE1 0xFCC08020
77#define SH_DMARS_BASE0 0xFC809000
78#endif
79
80#define REQ_HE 0x000000C0
81#define REQ_H 0x00000080
82#define REQ_LE 0x00000040
83#define TM_BURST 0x00000020
84
85#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma.h b/arch/sh/include/cpu-sh4/cpu/dma.h
index 9d32e2dd2554..6d7b66b6fe7e 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma.h
@@ -1,14 +1,6 @@
1#ifndef __ASM_CPU_SH4_DMA_H 1#ifndef __ASM_CPU_SH4_DMA_H
2#define __ASM_CPU_SH4_DMA_H 2#define __ASM_CPU_SH4_DMA_H
3 3
4/* SH7751/7760/7780 DMA IRQ sources */
5
6#ifdef CONFIG_CPU_SH4A
7
8#include <cpu/dma-sh4a.h>
9
10#else /* CONFIG_CPU_SH4A */
11
12#include <linux/sh_intc.h> 4#include <linux/sh_intc.h>
13 5
14/* 6/*
@@ -21,6 +13,7 @@
21 13
22#define SH_DMAC_BASE0 0xffa00000 14#define SH_DMAC_BASE0 0xffa00000
23#define SH_DMAC_BASE1 0xffa00070 15#define SH_DMAC_BASE1 0xffa00070
16
24/* Definitions for the SuperH DMAC */ 17/* Definitions for the SuperH DMAC */
25#define TM_BURST 0x00000080 18#define TM_BURST 0x00000080
26#define TS_8 0x00000010 19#define TS_8 0x00000010
@@ -30,6 +23,4 @@
30 23
31#define DMAOR_COD 0x00000008 24#define DMAOR_COD 0x00000008
32 25
33#endif
34
35#endif /* __ASM_CPU_SH4_DMA_H */ 26#endif /* __ASM_CPU_SH4_DMA_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-03 12:41:20 -0500