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authorKuninori Morimoto <morimoto.kuninori@renesas.com>2009-03-03 01:40:25 -0500
committerPaul Mundt <lethal@linux-sh.org>2009-03-03 01:40:25 -0500
commit55ba99eb211a06709237cb322ecd8c8b6faf6159 (patch)
treedc22ab87110e3e8fd26496fe6eebfbf261cc6c62 /arch/sh/include/cpu-sh4
parent93fde774546c947ac8563da431f0a6d47452551d (diff)
sh: Add support for SH7786 CPU subtype.
This adds preliminary support for the SH7786 CPU subtype. While this is a dual-core CPU, only UP is supported for now. L2 cache support is likewise not yet implemented. More information on this particular CPU subtype is available at: http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/ Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/cpu-sh4')
-rw-r--r--arch/sh/include/cpu-sh4/cpu/freq.h4
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7786.h192
2 files changed, 196 insertions, 0 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index c23af81c2e70..749d1c434337 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -29,6 +29,10 @@
29#define FRQCR0 0xffc80000 29#define FRQCR0 0xffc80000
30#define FRQCR1 0xffc80004 30#define FRQCR1 0xffc80004
31#define FRQMR1 0xffc80014 31#define FRQMR1 0xffc80014
32#elif defined(CONFIG_CPU_SUBTYPE_SH7786)
33#define FRQCR0 0xffc40000
34#define FRQCR1 0xffc40004
35#define FRQMR1 0xffc40014
32#elif defined(CONFIG_CPU_SUBTYPE_SHX3) 36#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
33#define FRQCR 0xffc00014 37#define FRQCR 0xffc00014
34#else 38#else
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7786.h b/arch/sh/include/cpu-sh4/cpu/sh7786.h
new file mode 100644
index 000000000000..48688adc0c84
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7786.h
@@ -0,0 +1,192 @@
1/*
2 * SH7786 Pinmux
3 *
4 * Copyright (C) 2008, 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on sh7785.h
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14#ifndef __CPU_SH7786_H__
15#define __CPU_SH7786_H__
16
17enum {
18 /* PA */
19 GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
20 GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
21
22 /* PB */
23 GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
24 GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0,
25
26 /* PC */
27 GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
28 GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
29
30 /* PD */
31 GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
32 GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
33
34 /* PE */
35 GPIO_PE5, GPIO_PE4, GPIO_PE3, GPIO_PE2,
36 GPIO_PE1, GPIO_PE0,
37
38 /* PF */
39 GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
40 GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
41
42 /* PG */
43 GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
44 GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
45
46 /* PH */
47 GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
48 GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
49
50 /* PJ */
51 GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
52 GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
53
54 GPIO_FN_CDE,
55 GPIO_FN_ETH_MAGIC,
56 GPIO_FN_DISP,
57 GPIO_FN_ETH_LINK,
58 GPIO_FN_DR5,
59 GPIO_FN_ETH_TX_ER,
60 GPIO_FN_DR4,
61 GPIO_FN_ETH_TX_EN,
62 GPIO_FN_DR3,
63 GPIO_FN_ETH_TXD3,
64 GPIO_FN_DR2,
65 GPIO_FN_ETH_TXD2,
66 GPIO_FN_DR1,
67 GPIO_FN_ETH_TXD1,
68 GPIO_FN_DR0,
69 GPIO_FN_ETH_TXD0,
70 GPIO_FN_VSYNC,
71 GPIO_FN_HSPI_CLK,
72 GPIO_FN_ODDF,
73 GPIO_FN_HSPI_CS,
74 GPIO_FN_DG5,
75 GPIO_FN_ETH_MDIO,
76 GPIO_FN_DG4,
77 GPIO_FN_ETH_RX_CLK,
78 GPIO_FN_DG3,
79 GPIO_FN_ETH_MDC,
80 GPIO_FN_DG2,
81 GPIO_FN_ETH_COL,
82 GPIO_FN_DG1,
83 GPIO_FN_ETH_TX_CLK,
84 GPIO_FN_DG0,
85 GPIO_FN_ETH_CRS,
86 GPIO_FN_DCLKIN,
87 GPIO_FN_HSPI_RX,
88 GPIO_FN_HSYNC,
89 GPIO_FN_HSPI_TX,
90 GPIO_FN_DB5,
91 GPIO_FN_ETH_RXD3,
92 GPIO_FN_DB4,
93 GPIO_FN_ETH_RXD2,
94 GPIO_FN_DB3,
95 GPIO_FN_ETH_RXD1,
96 GPIO_FN_DB2,
97 GPIO_FN_ETH_RXD0,
98 GPIO_FN_DB1,
99 GPIO_FN_ETH_RX_DV,
100 GPIO_FN_DB0,
101 GPIO_FN_ETH_RX_ER,
102 GPIO_FN_DCLKOUT,
103 GPIO_FN_SCIF1_SLK,
104 GPIO_FN_SCIF1_RXD,
105 GPIO_FN_SCIF1_TXD,
106 GPIO_FN_DACK1,
107 GPIO_FN_BACK,
108 GPIO_FN_FALE,
109 GPIO_FN_DACK0,
110 GPIO_FN_FCLE,
111 GPIO_FN_DREQ1,
112 GPIO_FN_BREQ,
113 GPIO_FN_USB_OVC1,
114 GPIO_FN_DREQ0,
115 GPIO_FN_USB_OVC0,
116 GPIO_FN_USB_PENC1,
117 GPIO_FN_USB_PENC0,
118 GPIO_FN_HAC1_SDOUT,
119 GPIO_FN_SSI1_SDATA,
120 GPIO_FN_SDIF1CMD,
121 GPIO_FN_HAC1_SDIN,
122 GPIO_FN_SSI1_SCK,
123 GPIO_FN_SDIF1CD,
124 GPIO_FN_HAC1_SYNC,
125 GPIO_FN_SSI1_WS,
126 GPIO_FN_SDIF1WP,
127 GPIO_FN_HAC1_BITCLK,
128 GPIO_FN_SSI1_CLK,
129 GPIO_FN_SDIF1CLK,
130 GPIO_FN_HAC0_SDOUT,
131 GPIO_FN_SSI0_SDATA,
132 GPIO_FN_SDIF1D3,
133 GPIO_FN_HAC0_SDIN,
134 GPIO_FN_SSI0_SCK,
135 GPIO_FN_SDIF1D2,
136 GPIO_FN_HAC0_SYNC,
137 GPIO_FN_SSI0_WS,
138 GPIO_FN_SDIF1D1,
139 GPIO_FN_HAC0_BITCLK,
140 GPIO_FN_SSI0_CLK,
141 GPIO_FN_SDIF1D0,
142 GPIO_FN_SCIF3_SCK,
143 GPIO_FN_SSI2_SDATA,
144 GPIO_FN_SCIF3_RXD,
145 GPIO_FN_TCLK,
146 GPIO_FN_SSI2_SCK,
147 GPIO_FN_SCIF3_TXD,
148 GPIO_FN_HAC_RES,
149 GPIO_FN_SSI2_WS,
150 GPIO_FN_DACK3,
151 GPIO_FN_SDIF0CMD,
152 GPIO_FN_DACK2,
153 GPIO_FN_SDIF0CD,
154 GPIO_FN_DREQ3,
155 GPIO_FN_SDIF0WP,
156 GPIO_FN_SCIF0_CTS,
157 GPIO_FN_DREQ2,
158 GPIO_FN_SDIF0CLK,
159 GPIO_FN_SCIF0_RTS,
160 GPIO_FN_IRL7,
161 GPIO_FN_SDIF0D3,
162 GPIO_FN_SCIF0_SCK,
163 GPIO_FN_IRL6,
164 GPIO_FN_SDIF0D2,
165 GPIO_FN_SCIF0_RXD,
166 GPIO_FN_IRL5,
167 GPIO_FN_SDIF0D1,
168 GPIO_FN_SCIF0_TXD,
169 GPIO_FN_IRL4,
170 GPIO_FN_SDIF0D0,
171 GPIO_FN_SCIF5_SCK,
172 GPIO_FN_FRB,
173 GPIO_FN_SCIF5_RXD,
174 GPIO_FN_IOIS16,
175 GPIO_FN_SCIF5_TXD,
176 GPIO_FN_CE2B,
177 GPIO_FN_DRAK3,
178 GPIO_FN_CE2A,
179 GPIO_FN_SCIF4_SCK,
180 GPIO_FN_DRAK2,
181 GPIO_FN_SSI3_WS,
182 GPIO_FN_SCIF4_RXD,
183 GPIO_FN_DRAK1,
184 GPIO_FN_SSI3_SDATA,
185 GPIO_FN_FSTATUS,
186 GPIO_FN_SCIF4_TXD,
187 GPIO_FN_DRAK0,
188 GPIO_FN_SSI3_SCK,
189 GPIO_FN_FSE,
190};
191
192#endif /* __CPU_SH7786_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 00:19:43 -0500