sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores.

This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores
that implement the PTAEX register and respective functionality. Presently
only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs).

The main change is in how the PTE is written out when loading the entry
in to the TLB, as well as in how the TLB entry is selectively flushed.

While SH-X2 extended mode splits out the memory-mapped U and I-TLB data
arrays for extra bits, extended ASID mode splits out the address arrays.
While we don't use the memory-mapped data array access, the address
array accesses are necessary for selective TLB flushes, so these are
implemented newly and replace the generic SH-4 implementation.

With this, TLB flushes in switch_mm() are almost non-existent on newer
parts.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

1 files changed, 16 insertions, 19 deletions

diff --git a/arch/sh/include/cpu-sh4/cpu/mmu_context.h b/arch/sh/include/cpu-sh4/cpu/mmu_context.h
index 9ea8eb27b18e..3ce7ef6c2978 100644
--- a/arch/sh/include/cpu-sh4/cpu/mmu_context.h
+++ b/arch/sh/include/cpu-sh4/cpu/mmu_context.h
@@ -14,28 +14,35 @@
 #define MMU_PTEL        0xFF000004      /* Page table entry register LOW */
 #define MMU_TTB         0xFF000008      /* Translation table base register */
 #define MMU_TEA         0xFF00000C      /* TLB Exception Address */
-#define MMU_PTEA        0xFF000034      /* Page table entry assistance register */
+#define MMU_PTEA        0xFF000034      /* PTE assistance register */
+#define MMU_PTEAEX      0xFF00007C      /* PTE ASID extension register */
 
 #define MMUCR           0xFF000010      /* MMU Control Register */
 
-#define MMU_ITLB_ADDRESS_ARRAY  0xF2000000
 #define MMU_UTLB_ADDRESS_ARRAY  0xF6000000
+#define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000
 #define MMU_PAGE_ASSOC_BIT      0x80
 
 #define MMUCR_TI                (1<<2)
 
-#ifdef CONFIG_X2TLB
-#define MMUCR_ME                (1 << 7)
-#else
-#define MMUCR_ME                (0)
-#endif
-
 #if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
 #define MMUCR_SE                (1 << 4)
 #else
 #define MMUCR_SE                (0)
 #endif
 
+#ifdef CONFIG_CPU_HAS_PTEAEX
+#define MMUCR_AEX               (1 << 6)
+#else
+#define MMUCR_AEX               (0)
+#endif
+
+#ifdef CONFIG_X2TLB
+#define MMUCR_ME                (1 << 7)
+#else
+#define MMUCR_ME                (0)
+#endif
+
 #ifdef CONFIG_SH_STORE_QUEUES
 #define MMUCR_SQMD              (1 << 9)
 #else
@@ -43,17 +50,7 @@
 #endif
 
 #define MMU_NTLB_ENTRIES        64
-#define MMU_CONTROL_INIT        (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE)
-
-#define MMU_ITLB_DATA_ARRAY     0xF3000000
-#define MMU_UTLB_DATA_ARRAY     0xF7000000
-
-#define MMU_UTLB_ENTRIES           64
-#define MMU_U_ENTRY_SHIFT           8
-#define MMU_UTLB_VALID          0x100
-#define MMU_ITLB_ENTRIES            4
-#define MMU_I_ENTRY_SHIFT           8
-#define MMU_ITLB_VALID          0x100
+#define MMU_CONTROL_INIT        (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE|MMUCR_AEX)
 
 #define TRA     0xff000020
 #define EXPEVT  0xff000024