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authorYoshinori Sato <ysato@users.sourceforge.jp>2008-08-04 03:33:47 -0400
committerPaul Mundt <lethal@linux-sh.org>2008-08-04 03:33:47 -0400
commitcce2d453e4940d3fccd42a6917d01027148e11c3 (patch)
treebf921bfd41e4a40e513a1994d474e03f44089c0e /arch/sh/include/cpu-sh2/cpu
parent1af446edfe3239b2b731f3458b3c285c397464cc (diff)
SH2(A) cache update
Includes: - SH2 (7619) Writeback support. - SH2A cache handling fix. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/cpu-sh2/cpu')
-rw-r--r--arch/sh/include/cpu-sh2/cpu/cache.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/sh/include/cpu-sh2/cpu/cache.h b/arch/sh/include/cpu-sh2/cpu/cache.h
index 4e0b16500686..673515bc4135 100644
--- a/arch/sh/include/cpu-sh2/cpu/cache.h
+++ b/arch/sh/include/cpu-sh2/cpu/cache.h
@@ -21,11 +21,11 @@
21#define CCR 0xffffffec 21#define CCR 0xffffffec
22 22
23#define CCR_CACHE_CE 0x01 /* Cache enable */ 23#define CCR_CACHE_CE 0x01 /* Cache enable */
24#define CCR_CACHE_WT 0x06 /* CCR[bit1=1,bit2=1] */ 24#define CCR_CACHE_WT 0x02 /* CCR[bit1=1,bit2=1] */
25 /* 0x00000000-0x7fffffff: Write-through */ 25 /* 0x00000000-0x7fffffff: Write-through */
26 /* 0x80000000-0x9fffffff: Write-back */ 26 /* 0x80000000-0x9fffffff: Write-back */
27 /* 0xc0000000-0xdfffffff: Write-through */ 27 /* 0xc0000000-0xdfffffff: Write-through */
28#define CCR_CACHE_CB 0x00 /* CCR[bit1=0,bit2=0] */ 28#define CCR_CACHE_CB 0x04 /* CCR[bit1=0,bit2=0] */
29 /* 0x00000000-0x7fffffff: Write-back */ 29 /* 0x00000000-0x7fffffff: Write-back */
30 /* 0x80000000-0x9fffffff: Write-through */ 30 /* 0x80000000-0x9fffffff: Write-through */
31 /* 0xc0000000-0xdfffffff: Write-back */ 31 /* 0xc0000000-0xdfffffff: Write-back */
@@ -36,6 +36,8 @@
36 36
37#define CCR_CACHE_ENABLE CCR_CACHE_CE 37#define CCR_CACHE_ENABLE CCR_CACHE_CE
38#define CCR_CACHE_INVALIDATE CCR_CACHE_CF 38#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
39#define CACHE_PHYSADDR_MASK 0x1ffffc00
40
39#endif 41#endif
40 42
41#endif /* __ASM_CPU_SH2_CACHE_H */ 43#endif /* __ASM_CPU_SH2_CACHE_H */