Merge branches 'sh/stable-updates' and 'sh/sparseirq'

16 files changed, 182 insertions, 191 deletions

diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h
index 09acbc32d6c7..4c5462daa74c 100644
--- a/arch/sh/include/asm/cacheflush.h
+++ b/arch/sh/include/asm/cacheflush.h
@@ -75,7 +75,5 @@ extern void copy_from_user_page(struct vm_area_struct *vma,
 #define flush_cache_vmap(start, end)            flush_cache_all()
 #define flush_cache_vunmap(start, end)          flush_cache_all()
 
-#define HAVE_ARCH_UNMAPPED_AREA
-
 #endif /* __KERNEL__ */
 #endif /* __ASM_SH_CACHEFLUSH_H */
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index 2f6c9627bc1f..b1f29199e4bd 100644
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -1,7 +1,6 @@
 #ifndef __ASM_SH_CLOCK_H
 #define __ASM_SH_CLOCK_H
 
-#include <linux/kref.h>
 #include <linux/list.h>
 #include <linux/seq_file.h>
 #include <linux/clk.h>
@@ -28,7 +27,7 @@ struct clk {
         struct clk              *parent;
         struct clk_ops          *ops;
 
-        struct kref             kref;
+        int                     usecount;
 
         unsigned long           rate;
         unsigned long           flags;
@@ -37,6 +36,7 @@ struct clk {
 
 #define CLK_ALWAYS_ENABLED      (1 << 0)
 #define CLK_RATE_PROPAGATES     (1 << 1)
+#define CLK_NEEDS_INIT          (1 << 2)
 
 /* Should be defined by processor-specific code */
 void arch_init_clk_ops(struct clk_ops **, int type);
diff --git a/arch/sh/include/asm/device.h b/arch/sh/include/asm/device.h
index efd511d0803a..8688a88303ee 100644
--- a/arch/sh/include/asm/device.h
+++ b/arch/sh/include/asm/device.h
@@ -10,3 +10,5 @@ struct platform_device;
 int platform_resource_setup_memory(struct platform_device *pdev,
                                    char *name, unsigned long memsize);
 
+void plat_early_device_setup(void);
+
diff --git a/arch/sh/include/asm/hd64461.h b/arch/sh/include/asm/hd64461.h
index 52b4b6238277..977355f0a483 100644
--- a/arch/sh/include/asm/hd64461.h
+++ b/arch/sh/include/asm/hd64461.h
@@ -13,18 +13,20 @@
 #define HD64461_PCC_WINDOW      0x01000000
 
 /* Area 6 - Slot 0 - memory and/or IO card */
-#define HD64461_PCC0_BASE       (CONFIG_HD64461_IOBASE + 0x8000000)
+#define HD64461_IOBASE          0xb0000000
+#define HD64461_IO_OFFSET(x)    (HD64461_IOBASE + (x))
+#define HD64461_PCC0_BASE       HD64461_IO_OFFSET(0x8000000)
 #define HD64461_PCC0_ATTR       (HD64461_PCC0_BASE)                             /* 0xb80000000 */
 #define HD64461_PCC0_COMM       (HD64461_PCC0_BASE+HD64461_PCC_WINDOW)          /* 0xb90000000 */
 #define HD64461_PCC0_IO         (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)        /* 0xba0000000 */
 
 /* Area 5 - Slot 1 - memory card only */
-#define HD64461_PCC1_BASE       (CONFIG_HD64461_IOBASE + 0x4000000)
+#define HD64461_PCC1_BASE       HD64461_IO_OFFSET(0x4000000)
 #define HD64461_PCC1_ATTR       (HD64461_PCC1_BASE)                             /* 0xb4000000 */
 #define HD64461_PCC1_COMM       (HD64461_PCC1_BASE+HD64461_PCC_WINDOW)          /* 0xb5000000 */
 
 /* Standby Control Register for HD64461 */
-#define HD64461_STBCR                   CONFIG_HD64461_IOBASE
+#define HD64461_STBCR                   HD64461_IO_OFFSET(0x00000000)
 #define HD64461_STBCR_CKIO_STBY         0x2000
 #define HD64461_STBCR_SAFECKE_IST       0x1000
 #define HD64461_STBCR_SLCKE_IST         0x0800
@@ -41,19 +43,19 @@
 #define HD64461_STBCR_SURTST            0x0001
 
 /* System Configuration Register */
-#define HD64461_SYSCR           (CONFIG_HD64461_IOBASE + 0x02)
+#define HD64461_SYSCR           HD64461_IO_OFFSET(0x02)
 
 /* CPU Data Bus Control Register */
-#define HD64461_SCPUCR          (CONFIG_HD64461_IOBASE + 0x04)
+#define HD64461_SCPUCR          HD64461_IO_OFFSET(0x04)
 
 /* Base Address Register */
-#define HD64461_LCDCBAR         (CONFIG_HD64461_IOBASE + 0x1000)
+#define HD64461_LCDCBAR         HD64461_IO_OFFSET(0x1000)
 
 /* Line increment address */
-#define HD64461_LCDCLOR         (CONFIG_HD64461_IOBASE + 0x1002)
+#define HD64461_LCDCLOR         HD64461_IO_OFFSET(0x1002)
 
 /* Controls LCD controller */
-#define HD64461_LCDCCR          (CONFIG_HD64461_IOBASE + 0x1004)
+#define HD64461_LCDCCR          HD64461_IO_OFFSET(0x1004)
 
 /* LCCDR control bits */
 #define HD64461_LCDCCR_STBACK   0x0400  /* Standby Back */
@@ -64,30 +66,30 @@
 #define HD64461_LCDCCR_SPON     0x0010  /* Start Power On */
 
 /* Controls LCD (1) */
-#define HD64461_LDR1            (CONFIG_HD64461_IOBASE + 0x1010)
+#define HD64461_LDR1            HD64461_IO_OFFSET(0x1010)
 #define HD64461_LDR1_DON        0x01    /* Display On */
 #define HD64461_LDR1_DINV       0x80    /* Display Invert */
 
 /* Controls LCD (2) */
-#define HD64461_LDR2            (CONFIG_HD64461_IOBASE + 0x1012)
-#define HD64461_LDHNCR          (CONFIG_HD64461_IOBASE + 0x1014)        /* Number of horizontal characters */
-#define HD64461_LDHNSR          (CONFIG_HD64461_IOBASE + 0x1016)        /* Specify output start position + width of CL1 */
-#define HD64461_LDVNTR          (CONFIG_HD64461_IOBASE + 0x1018)        /* Specify total vertical lines */
-#define HD64461_LDVNDR          (CONFIG_HD64461_IOBASE + 0x101a)        /* specify number of display vertical lines */
-#define HD64461_LDVSPR          (CONFIG_HD64461_IOBASE + 0x101c)        /* specify vertical synchronization pos and AC nr */
+#define HD64461_LDR2            HD64461_IO_OFFSET(0x1012)
+#define HD64461_LDHNCR          HD64461_IO_OFFSET(0x1014)       /* Number of horizontal characters */
+#define HD64461_LDHNSR          HD64461_IO_OFFSET(0x1016)       /* Specify output start position + width of CL1 */
+#define HD64461_LDVNTR          HD64461_IO_OFFSET(0x1018)       /* Specify total vertical lines */
+#define HD64461_LDVNDR          HD64461_IO_OFFSET(0x101a)       /* specify number of display vertical lines */
+#define HD64461_LDVSPR          HD64461_IO_OFFSET(0x101c)       /* specify vertical synchronization pos and AC nr */
 
 /* Controls LCD (3) */
-#define HD64461_LDR3            (CONFIG_HD64461_IOBASE + 0x101e)
+#define HD64461_LDR3            HD64461_IO_OFFSET(0x101e)
 
 /* Palette Registers */
-#define HD64461_CPTWAR          (CONFIG_HD64461_IOBASE + 0x1030)        /* Color Palette Write Address Register */
-#define HD64461_CPTWDR          (CONFIG_HD64461_IOBASE + 0x1032)        /* Color Palette Write Data Register */
-#define HD64461_CPTRAR          (CONFIG_HD64461_IOBASE + 0x1034)        /* Color Palette Read Address Register */
-#define HD64461_CPTRDR          (CONFIG_HD64461_IOBASE + 0x1036)        /* Color Palette Read Data Register */
+#define HD64461_CPTWAR          HD64461_IO_OFFSET(0x1030)       /* Color Palette Write Address Register */
+#define HD64461_CPTWDR          HD64461_IO_OFFSET(0x1032)       /* Color Palette Write Data Register */
+#define HD64461_CPTRAR          HD64461_IO_OFFSET(0x1034)       /* Color Palette Read Address Register */
+#define HD64461_CPTRDR          HD64461_IO_OFFSET(0x1036)       /* Color Palette Read Data Register */
 
-#define HD64461_GRDOR           (CONFIG_HD64461_IOBASE + 0x1040)        /* Display Resolution Offset Register */
-#define HD64461_GRSCR           (CONFIG_HD64461_IOBASE + 0x1042)        /* Solid Color Register */
-#define HD64461_GRCFGR          (CONFIG_HD64461_IOBASE + 0x1044)        /* Accelerator Configuration Register */
+#define HD64461_GRDOR           HD64461_IO_OFFSET(0x1040)       /* Display Resolution Offset Register */
+#define HD64461_GRSCR           HD64461_IO_OFFSET(0x1042)       /* Solid Color Register */
+#define HD64461_GRCFGR          HD64461_IO_OFFSET(0x1044)       /* Accelerator Configuration Register */
 
 #define HD64461_GRCFGR_ACCSTATUS        0x10    /* Accelerator Status */
 #define HD64461_GRCFGR_ACCRESET         0x08    /* Accelerator Reset */
@@ -97,41 +99,41 @@
 #define HD64461_GRCFGR_COLORDEPTH8      0x01    /* Sets Colordepth 8 for Accelerator */
 
 /* Line Drawing Registers */
-#define HD64461_LNSARH          (CONFIG_HD64461_IOBASE + 0x1046)        /* Line Start Address Register (H) */
-#define HD64461_LNSARL          (CONFIG_HD64461_IOBASE + 0x1048)        /* Line Start Address Register (L) */
-#define HD64461_LNAXLR          (CONFIG_HD64461_IOBASE + 0x104a)        /* Axis Pixel Length Register */
-#define HD64461_LNDGR           (CONFIG_HD64461_IOBASE + 0x104c)        /* Diagonal Register */
-#define HD64461_LNAXR           (CONFIG_HD64461_IOBASE + 0x104e)        /* Axial Register */
-#define HD64461_LNERTR          (CONFIG_HD64461_IOBASE + 0x1050)        /* Start Error Term Register */
-#define HD64461_LNMDR           (CONFIG_HD64461_IOBASE + 0x1052)        /* Line Mode Register */
+#define HD64461_LNSARH          HD64461_IO_OFFSET(0x1046)       /* Line Start Address Register (H) */
+#define HD64461_LNSARL          HD64461_IO_OFFSET(0x1048)       /* Line Start Address Register (L) */
+#define HD64461_LNAXLR          HD64461_IO_OFFSET(0x104a)       /* Axis Pixel Length Register */
+#define HD64461_LNDGR           HD64461_IO_OFFSET(0x104c)       /* Diagonal Register */
+#define HD64461_LNAXR           HD64461_IO_OFFSET(0x104e)       /* Axial Register */
+#define HD64461_LNERTR          HD64461_IO_OFFSET(0x1050)       /* Start Error Term Register */
+#define HD64461_LNMDR           HD64461_IO_OFFSET(0x1052)       /* Line Mode Register */
 
 /* BitBLT Registers */
-#define HD64461_BBTSSARH        (CONFIG_HD64461_IOBASE + 0x1054)        /* Source Start Address Register (H) */
-#define HD64461_BBTSSARL        (CONFIG_HD64461_IOBASE + 0x1056)        /* Source Start Address Register (L) */
-#define HD64461_BBTDSARH        (CONFIG_HD64461_IOBASE + 0x1058)        /* Destination Start Address Register (H) */
-#define HD64461_BBTDSARL        (CONFIG_HD64461_IOBASE + 0x105a)        /* Destination Start Address Register (L) */
-#define HD64461_BBTDWR          (CONFIG_HD64461_IOBASE + 0x105c)        /* Destination Block Width Register */
-#define HD64461_BBTDHR          (CONFIG_HD64461_IOBASE + 0x105e)        /* Destination Block Height Register */
-#define HD64461_BBTPARH         (CONFIG_HD64461_IOBASE + 0x1060)        /* Pattern Start Address Register (H) */
-#define HD64461_BBTPARL         (CONFIG_HD64461_IOBASE + 0x1062)        /* Pattern Start Address Register (L) */
-#define HD64461_BBTMARH         (CONFIG_HD64461_IOBASE + 0x1064)        /* Mask Start Address Register (H) */
-#define HD64461_BBTMARL         (CONFIG_HD64461_IOBASE + 0x1066)        /* Mask Start Address Register (L) */
-#define HD64461_BBTROPR         (CONFIG_HD64461_IOBASE + 0x1068)        /* ROP Register */
-#define HD64461_BBTMDR          (CONFIG_HD64461_IOBASE + 0x106a)        /* BitBLT Mode Register */
+#define HD64461_BBTSSARH        HD64461_IO_OFFSET(0x1054)       /* Source Start Address Register (H) */
+#define HD64461_BBTSSARL        HD64461_IO_OFFSET(0x1056)       /* Source Start Address Register (L) */
+#define HD64461_BBTDSARH        HD64461_IO_OFFSET(0x1058)       /* Destination Start Address Register (H) */
+#define HD64461_BBTDSARL        HD64461_IO_OFFSET(0x105a)       /* Destination Start Address Register (L) */
+#define HD64461_BBTDWR          HD64461_IO_OFFSET(0x105c)       /* Destination Block Width Register */
+#define HD64461_BBTDHR          HD64461_IO_OFFSET(0x105e)       /* Destination Block Height Register */
+#define HD64461_BBTPARH         HD64461_IO_OFFSET(0x1060)       /* Pattern Start Address Register (H) */
+#define HD64461_BBTPARL         HD64461_IO_OFFSET(0x1062)       /* Pattern Start Address Register (L) */
+#define HD64461_BBTMARH         HD64461_IO_OFFSET(0x1064)       /* Mask Start Address Register (H) */
+#define HD64461_BBTMARL         HD64461_IO_OFFSET(0x1066)       /* Mask Start Address Register (L) */
+#define HD64461_BBTROPR         HD64461_IO_OFFSET(0x1068)       /* ROP Register */
+#define HD64461_BBTMDR          HD64461_IO_OFFSET(0x106a)       /* BitBLT Mode Register */
 
 /* PC Card Controller Registers */
 /* Maps to Physical Area 6 */
-#define HD64461_PCC0ISR         (CONFIG_HD64461_IOBASE + 0x2000)        /* socket 0 interface status */
-#define HD64461_PCC0GCR         (CONFIG_HD64461_IOBASE + 0x2002)        /* socket 0 general control */
-#define HD64461_PCC0CSCR        (CONFIG_HD64461_IOBASE + 0x2004)        /* socket 0 card status change */
-#define HD64461_PCC0CSCIER      (CONFIG_HD64461_IOBASE + 0x2006)        /* socket 0 card status change interrupt enable */
-#define HD64461_PCC0SCR         (CONFIG_HD64461_IOBASE + 0x2008)        /* socket 0 software control */
+#define HD64461_PCC0ISR         HD64461_IO_OFFSET(0x2000)       /* socket 0 interface status */
+#define HD64461_PCC0GCR         HD64461_IO_OFFSET(0x2002)       /* socket 0 general control */
+#define HD64461_PCC0CSCR        HD64461_IO_OFFSET(0x2004)       /* socket 0 card status change */
+#define HD64461_PCC0CSCIER      HD64461_IO_OFFSET(0x2006)       /* socket 0 card status change interrupt enable */
+#define HD64461_PCC0SCR         HD64461_IO_OFFSET(0x2008)       /* socket 0 software control */
 /* Maps to Physical Area 5 */
-#define HD64461_PCC1ISR         (CONFIG_HD64461_IOBASE + 0x2010)        /* socket 1 interface status */
-#define HD64461_PCC1GCR         (CONFIG_HD64461_IOBASE + 0x2012)        /* socket 1 general control */
-#define HD64461_PCC1CSCR        (CONFIG_HD64461_IOBASE + 0x2014)        /* socket 1 card status change */
-#define HD64461_PCC1CSCIER      (CONFIG_HD64461_IOBASE + 0x2016)        /* socket 1 card status change interrupt enable */
-#define HD64461_PCC1SCR         (CONFIG_HD64461_IOBASE + 0x2018)        /* socket 1 software control */
+#define HD64461_PCC1ISR         HD64461_IO_OFFSET(0x2010)       /* socket 1 interface status */
+#define HD64461_PCC1GCR         HD64461_IO_OFFSET(0x2012)       /* socket 1 general control */
+#define HD64461_PCC1CSCR        HD64461_IO_OFFSET(0x2014)       /* socket 1 card status change */
+#define HD64461_PCC1CSCIER      HD64461_IO_OFFSET(0x2016)       /* socket 1 card status change interrupt enable */
+#define HD64461_PCC1SCR         HD64461_IO_OFFSET(0x2018)       /* socket 1 software control */
 
 /* PCC Interface Status Register */
 #define HD64461_PCCISR_READY            0x80    /* card ready */
@@ -189,41 +191,41 @@
 #define HD64461_PCCSCR_SWP              0x01    /* write protect */
 
 /* PCC0 Output Pins Control Register */
-#define HD64461_P0OCR           (CONFIG_HD64461_IOBASE + 0x202a)
+#define HD64461_P0OCR           HD64461_IO_OFFSET(0x202a)
 
 /* PCC1 Output Pins Control Register */
-#define HD64461_P1OCR           (CONFIG_HD64461_IOBASE + 0x202c)
+#define HD64461_P1OCR           HD64461_IO_OFFSET(0x202c)
 
 /* PC Card General Control Register */
-#define HD64461_PGCR            (CONFIG_HD64461_IOBASE + 0x202e)
+#define HD64461_PGCR            HD64461_IO_OFFSET(0x202e)
 
 /* Port Control Registers */
-#define HD64461_GPACR           (CONFIG_HD64461_IOBASE + 0x4000)        /* Port A - Handles IRDA/TIMER */
-#define HD64461_GPBCR           (CONFIG_HD64461_IOBASE + 0x4002)        /* Port B - Handles UART */
-#define HD64461_GPCCR           (CONFIG_HD64461_IOBASE + 0x4004)        /* Port C - Handles PCMCIA 1 */
-#define HD64461_GPDCR           (CONFIG_HD64461_IOBASE + 0x4006)        /* Port D - Handles PCMCIA 1 */
+#define HD64461_GPACR           HD64461_IO_OFFSET(0x4000)       /* Port A - Handles IRDA/TIMER */
+#define HD64461_GPBCR           HD64461_IO_OFFSET(0x4002)       /* Port B - Handles UART */
+#define HD64461_GPCCR           HD64461_IO_OFFSET(0x4004)       /* Port C - Handles PCMCIA 1 */
+#define HD64461_GPDCR           HD64461_IO_OFFSET(0x4006)       /* Port D - Handles PCMCIA 1 */
 
 /* Port Control Data Registers */
-#define HD64461_GPADR           (CONFIG_HD64461_IOBASE + 0x4010)        /* A */
-#define HD64461_GPBDR           (CONFIG_HD64461_IOBASE + 0x4012)        /* B */
-#define HD64461_GPCDR           (CONFIG_HD64461_IOBASE + 0x4014)        /* C */
-#define HD64461_GPDDR           (CONFIG_HD64461_IOBASE + 0x4016)        /* D */
+#define HD64461_GPADR           HD64461_IO_OFFSET(0x4010)       /* A */
+#define HD64461_GPBDR           HD64461_IO_OFFSET(0x4012)       /* B */
+#define HD64461_GPCDR           HD64461_IO_OFFSET(0x4014)       /* C */
+#define HD64461_GPDDR           HD64461_IO_OFFSET(0x4016)       /* D */
 
 /* Interrupt Control Registers */
-#define HD64461_GPAICR          (CONFIG_HD64461_IOBASE + 0x4020)        /* A */
-#define HD64461_GPBICR          (CONFIG_HD64461_IOBASE + 0x4022)        /* B */
-#define HD64461_GPCICR          (CONFIG_HD64461_IOBASE + 0x4024)        /* C */
-#define HD64461_GPDICR          (CONFIG_HD64461_IOBASE + 0x4026)        /* D */
+#define HD64461_GPAICR          HD64461_IO_OFFSET(0x4020)       /* A */
+#define HD64461_GPBICR          HD64461_IO_OFFSET(0x4022)       /* B */
+#define HD64461_GPCICR          HD64461_IO_OFFSET(0x4024)       /* C */
+#define HD64461_GPDICR          HD64461_IO_OFFSET(0x4026)       /* D */
 
 /* Interrupt Status Registers */
-#define HD64461_GPAISR          (CONFIG_HD64461_IOBASE + 0x4040)        /* A */
-#define HD64461_GPBISR          (CONFIG_HD64461_IOBASE + 0x4042)        /* B */
-#define HD64461_GPCISR          (CONFIG_HD64461_IOBASE + 0x4044)        /* C */
-#define HD64461_GPDISR          (CONFIG_HD64461_IOBASE + 0x4046)        /* D */
+#define HD64461_GPAISR          HD64461_IO_OFFSET(0x4040)       /* A */
+#define HD64461_GPBISR          HD64461_IO_OFFSET(0x4042)       /* B */
+#define HD64461_GPCISR          HD64461_IO_OFFSET(0x4044)       /* C */
+#define HD64461_GPDISR          HD64461_IO_OFFSET(0x4046)       /* D */
 
 /* Interrupt Request Register & Interrupt Mask Register */
-#define HD64461_NIRR            (CONFIG_HD64461_IOBASE + 0x5000)
-#define HD64461_NIMR            (CONFIG_HD64461_IOBASE + 0x5002)
+#define HD64461_NIRR            HD64461_IO_OFFSET(0x5000)
+#define HD64461_NIMR            HD64461_IO_OFFSET(0x5002)
 
 #define HD64461_IRQBASE         OFFCHIP_IRQ_BASE
 #define OFFCHIP_IRQ_BASE        64
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 0454f8d68059..25348141674b 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -123,10 +123,15 @@ static inline void __raw_reads##bwlq(volatile void __iomem *mem,	\
 
 __BUILD_MEMORY_STRING(b, u8)
 __BUILD_MEMORY_STRING(w, u16)
-__BUILD_MEMORY_STRING(q, u64)
 
+#ifdef CONFIG_SUPERH32
 void __raw_writesl(void __iomem *addr, const void *data, int longlen);
 void __raw_readsl(const void __iomem *addr, void *data, int longlen);
+#else
+__BUILD_MEMORY_STRING(l, u32)
+#endif
+
+__BUILD_MEMORY_STRING(q, u64)
 
 #define writesb                 __raw_writesb
 #define writesw                 __raw_writesw
@@ -224,17 +229,6 @@ void __iomem *__ioremap(unsigned long offset, unsigned long size,
                         unsigned long flags);
 void __iounmap(void __iomem *addr);
 
-/* arch/sh/mm/ioremap_64.c */
-unsigned long onchip_remap(unsigned long addr, unsigned long size,
-                           const char *name);
-extern void onchip_unmap(unsigned long vaddr);
-#else
-#define __ioremap(offset, size, flags)  ((void __iomem *)(offset))
-#define __iounmap(addr)                 do { } while (0)
-#define onchip_remap(addr, size, name)  (addr)
-#define onchip_unmap(addr)              do { } while (0)
-#endif /* CONFIG_MMU */
-
 static inline void __iomem *
 __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
 {
@@ -268,6 +262,10 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
 
         return __ioremap(offset, size, flags);
 }
+#else
+#define __ioremap_mode(offset, size, flags)     ((void __iomem *)(offset))
+#define __iounmap(addr)                         do { } while (0)
+#endif /* CONFIG_MMU */
 
 #define ioremap(offset, size)                           \
         __ioremap_mode((offset), (size), 0)
diff --git a/arch/sh/include/asm/kprobes.h b/arch/sh/include/asm/kprobes.h
index 613644a758e8..036c3311233c 100644
--- a/arch/sh/include/asm/kprobes.h
+++ b/arch/sh/include/asm/kprobes.h
@@ -6,7 +6,7 @@
 #include <linux/types.h>
 #include <linux/ptrace.h>
 
-typedef u16 kprobe_opcode_t;
+typedef insn_size_t kprobe_opcode_t;
 #define BREAKPOINT_INSTRUCTION  0xc33a
 
 #define MAX_INSN_SIZE 16
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index df1d383e18a5..5b2e0fcdfc22 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -17,54 +17,29 @@
  * external) PCI controllers.
  */
 struct pci_channel {
-        struct pci_ops *pci_ops;
-        struct resource *io_resource;
-        struct resource *mem_resource;
-        int first_devfn;
-        int last_devfn;
-};
+        struct pci_channel      *next;
 
-/*
- * Each board initializes this array and terminates it with a NULL entry.
- */
-extern struct pci_channel board_pci_channels[];
+        struct pci_ops          *pci_ops;
+        struct resource         *io_resource;
+        struct resource         *mem_resource;
 
-#define PCIBIOS_MIN_IO          board_pci_channels->io_resource->start
-#define PCIBIOS_MIN_MEM         board_pci_channels->mem_resource->start
+        unsigned long           io_offset;
+        unsigned long           mem_offset;
 
-/*
- * I/O routine helpers
- */
-#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
-#define PCI_IO_AREA             0xFE400000
-#define PCI_IO_SIZE             0x00400000
-#elif defined(CONFIG_CPU_SH5)
-extern unsigned long PCI_IO_AREA;
-#define PCI_IO_SIZE             0x00010000
-#else
-#define PCI_IO_AREA             0xFE240000
-#define PCI_IO_SIZE             0x00040000
-#endif
+        unsigned long           reg_base;
 
-#define PCI_MEM_SIZE            0x01000000
+        unsigned long           io_map_base;
+};
 
-#define SH4_PCIIOBR_MASK        0xFFFC0000
-#define pci_ioaddr(addr)        (PCI_IO_AREA + (addr & ~SH4_PCIIOBR_MASK))
+extern void register_pci_controller(struct pci_channel *hose);
 
-#if defined(CONFIG_PCI)
-#define is_pci_ioaddr(port)             \
-        (((port) >= PCIBIOS_MIN_IO) &&  \
-         ((port) < (PCIBIOS_MIN_IO + PCI_IO_SIZE)))
-#define is_pci_memaddr(port)            \
-        (((port) >= PCIBIOS_MIN_MEM) && \
-         ((port) < (PCIBIOS_MIN_MEM + PCI_MEM_SIZE)))
-#else
-#define is_pci_ioaddr(port)     (0)
-#define is_pci_memaddr(port)    (0)
-#endif
+extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
 
 struct pci_dev;
 
+#define HAVE_PCI_MMAP
+extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
+        enum pci_mmap_state mmap_state, int write_combine);
 extern void pcibios_set_master(struct pci_dev *dev);
 
 static inline void pcibios_penalize_isa_irq(int irq, int active)
@@ -123,22 +98,51 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 }
 #endif
 
+#ifdef CONFIG_SUPERH32
+/*
+ * If we're on an SH7751 or SH7780 PCI controller, PCI memory is mapped
+ * at the end of the address space in a special non-translatable area.
+ */
+#define PCI_MEM_FIXED_START     0xfd000000
+#define PCI_MEM_FIXED_END       (PCI_MEM_FIXED_START + 0x01000000)
+
+#define is_pci_memory_fixed_range(s, e) \
+        ((s) >= PCI_MEM_FIXED_START && (e) < PCI_MEM_FIXED_END)
+#else
+#define is_pci_memory_fixed_range(s, e) (0)
+#endif
+
 /* Board-specific fixup routines. */
-void pcibios_fixup(void);
-int pcibios_init_platform(void);
 int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
 
-#ifdef CONFIG_PCI_AUTO
-int pciauto_assign_resources(int busno, struct pci_channel *hose);
-#endif
+extern void pcibios_resource_to_bus(struct pci_dev *dev,
+        struct pci_bus_region *region, struct resource *res);
 
-#endif /* __KERNEL__ */
+extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+                                    struct pci_bus_region *region);
+
+static inline struct resource *
+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
+{
+        struct resource *root = NULL;
 
-/* generic pci stuff */
-#include <asm-generic/pci.h>
+        if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+
+        return root;
+}
+
+/* Chances are this interrupt is wired PC-style ...  */
+static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
+{
+        return channel ? 15 : 14;
+}
 
 /* generic DMA-mapping stuff */
 #include <asm-generic/pci-dma-compat.h>
 
+#endif /* __KERNEL__ */
 #endif /* __ASM_SH_PCI_H */
 
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index b517ae08b9c0..2a011b18090b 100644
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -154,6 +154,10 @@ extern void kmap_coherent_init(void);
 #define kmap_coherent_init()    do { } while (0)
 #endif
 
+/* arch/sh/mm/mmap.c */
+#define HAVE_ARCH_UNMAPPED_AREA
+#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
+
 #include <asm-generic/pgtable.h>
 
 #endif /* __ASM_SH_PGTABLE_H */
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 1fd58b421438..005c962c8b1c 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -32,7 +32,7 @@ enum cpu_type {
 
         /* SH-4A types */
         CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
-        CPU_SH7723, CPU_SHX3,
+        CPU_SH7723, CPU_SH7724, CPU_SHX3,
 
         /* SH4AL-DSP types */
         CPU_SH7343, CPU_SH7722, CPU_SH7366,
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
index 68e20ff9aa9b..1dc12cb44a2d 100644
--- a/arch/sh/include/asm/ptrace.h
+++ b/arch/sh/include/asm/ptrace.h
@@ -102,6 +102,11 @@ struct pt_dspregs {
 #define PTRACE_GETDSPREGS       55      /* DSP registers */
 #define PTRACE_SETDSPREGS       56
 
+#define PT_TEXT_END_ADDR        240
+#define PT_TEXT_ADDR            244     /* &(struct user)->start_code */
+#define PT_DATA_ADDR            248     /* &(struct user)->start_data */
+#define PT_TEXT_LEN             252
+
 #ifdef __KERNEL__
 #include <asm/addrspace.h>
 
diff --git a/arch/sh/include/asm/rtc.h b/arch/sh/include/asm/rtc.h
index f7b010d48af7..52b0c2dba979 100644
--- a/arch/sh/include/asm/rtc.h
+++ b/arch/sh/include/asm/rtc.h
@@ -6,6 +6,17 @@ extern void (*board_time_init)(void);
 extern void (*rtc_sh_get_time)(struct timespec *);
 extern int (*rtc_sh_set_time)(const time_t);
 
+/* some dummy definitions */
+#define RTC_BATT_BAD 0x100      /* battery bad */
+#define RTC_SQWE 0x08           /* enable square-wave output */
+#define RTC_DM_BINARY 0x04      /* all time/date values are BCD if clear */
+#define RTC_24H 0x02            /* 24 hour mode - else hours bit 7 means pm */
+#define RTC_DST_EN 0x01         /* auto switch DST - works f. USA only */
+
+struct rtc_time;
+unsigned int get_rtc_time(struct rtc_time *);
+int set_rtc_time(struct rtc_time *);
+
 #define RTC_CAP_4_DIGIT_YEAR    (1 << 0)
 
 struct sh_rtc_platform_info {
diff --git a/arch/sh/include/asm/swab.h b/arch/sh/include/asm/swab.h
index e69315935107..0e08fe54ad71 100644
--- a/arch/sh/include/asm/swab.h
+++ b/arch/sh/include/asm/swab.h
@@ -14,15 +14,15 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
 {
         __asm__(
 #ifdef __SH5__
-                "byterev        %0, %0\n\t"
+                "byterev        %1, %0\n\t"
                 "shari          %0, 32, %0"
 #else
-                "swap.b         %0, %0\n\t"
+                "swap.b         %1, %0\n\t"
                 "swap.w         %0, %0\n\t"
                 "swap.b         %0, %0"
 #endif
                 : "=r" (x)
-                : "0" (x));
+                : "r" (x));
 
         return x;
 }
@@ -32,13 +32,13 @@ static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
 {
         __asm__(
 #ifdef __SH5__
-                "byterev        %0, %0\n\t"
+                "byterev        %1, %0\n\t"
                 "shari          %0, 32, %0"
 #else
-                "swap.b         %0, %0"
+                "swap.b         %1, %0"
 #endif
                 : "=r" (x)
-                :  "0" (x));
+                :  "r" (x));
 
         return x;
 }
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h
index 240b31e1142c..6c68a51f1cc5 100644
--- a/arch/sh/include/asm/system_32.h
+++ b/arch/sh/include/asm/system_32.h
@@ -198,7 +198,7 @@ do {							\
 })
 #endif
 
-int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs,
+int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
                             struct mem_access *ma);
 
 asmlinkage void do_address_error(struct pt_regs *regs,
diff --git a/arch/sh/include/asm/timer.h b/arch/sh/include/asm/timer.h
deleted file mode 100644
index 4c3b66e30af2..000000000000
--- a/arch/sh/include/asm/timer.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#ifndef __ASM_SH_TIMER_H
-#define __ASM_SH_TIMER_H
-
-#include <linux/sysdev.h>
-#include <linux/clocksource.h>
-#include <cpu/timer.h>
-
-struct sys_timer_ops {
-        int (*init)(void);
-        int (*start)(void);
-        int (*stop)(void);
-#ifndef CONFIG_GENERIC_TIME
-        unsigned long (*get_offset)(void);
-#endif
-};
-
-struct sys_timer {
-        const char              *name;
-
-        struct sys_device       dev;
-        struct sys_timer_ops    *ops;
-};
-
-#define TICK_SIZE (tick_nsec / 1000)
-
-extern struct sys_timer tmu_timer, cmt_timer, mtu2_timer;
-extern struct sys_timer *sys_timer;
-
-#ifndef CONFIG_GENERIC_TIME
-static inline unsigned long get_timer_offset(void)
-{
-        return sys_timer->ops->get_offset();
-}
-#endif
-
-/* arch/sh/kernel/timers/timer.c */
-struct sys_timer *get_sys_timer(void);
-
-/* arch/sh/kernel/time.c */
-void handle_timer_tick(void);
-
-extern struct clocksource clocksource_sh;
-
-#endif /* __ASM_SH_TIMER_H */
diff --git a/arch/sh/include/asm/types.h b/arch/sh/include/asm/types.h
index beea4e6f8dfd..b13caca62a76 100644
--- a/arch/sh/include/asm/types.h
+++ b/arch/sh/include/asm/types.h
@@ -23,9 +23,9 @@ typedef unsigned short umode_t;
 typedef u32 dma_addr_t;
 
 #ifdef CONFIG_SUPERH32
-typedef u16 opcode_t;
+typedef u16 insn_size_t;
 #else
-typedef u32 opcode_t;
+typedef u32 insn_size_t;
 #endif
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/sh/include/asm/ubc.h b/arch/sh/include/asm/ubc.h
index a7b9028bbfbb..4ca4b7717371 100644
--- a/arch/sh/include/asm/ubc.h
+++ b/arch/sh/include/asm/ubc.h
@@ -42,12 +42,23 @@
 
 #define BRCR_CMFA               (1 << 15)
 #define BRCR_CMFB               (1 << 14)
+
+#if defined CONFIG_CPU_SH2A
+#define BRCR_CMFCA              (1 << 15)
+#define BRCR_CMFCB              (1 << 14)
+#define BRCR_CMFDA              (1 << 13)
+#define BRCR_CMFDB              (1 << 12)
+#define BRCR_PCBB               (1 << 6)        /* 1: after execution */
+#define BRCR_PCBA               (1 << 5)        /* 1: after execution */
+#define BRCR_PCTE               0
+#else
 #define BRCR_PCTE               (1 << 11)
 #define BRCR_PCBA               (1 << 10)       /* 1: after execution */
 #define BRCR_DBEB               (1 << 7)
 #define BRCR_PCBB               (1 << 6)
 #define BRCR_SEQ                (1 << 3)
 #define BRCR_UBDE               (1 << 0)
+#endif
 
 #ifndef __ASSEMBLY__
 /* arch/sh/kernel/cpu/ubc.S */