aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh/drivers
diff options
context:
space:
mode:
authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.zh@hitachi.com>2007-03-30 01:49:21 -0400
committerPaul Mundt <lethal@hera.kernel.org>2007-05-06 22:11:55 -0400
commitb7aee517c8302d651ff057fdcebee3c1f53c3b2e (patch)
tree35bcd214bd49175f32e2e2ab5bd8ce3b7e4c0d58 /arch/sh/drivers
parentb75762302e144b73f12b72c59b99401d036680aa (diff)
sh: se7780 PCI support.
Add support for the SH7780 PCIC on the Solution Engine 7780, missing from the previous board-support patch. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.zh@hitachi.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers')
-rw-r--r--arch/sh/drivers/pci/Makefile1
-rw-r--r--arch/sh/drivers/pci/fixups-se7780.c60
-rw-r--r--arch/sh/drivers/pci/ops-se7780.c96
3 files changed, 157 insertions, 0 deletions
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index b1391cb080d1..0e9b532b9fbc 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_SH_HIGHLANDER) += ops-r7780rp.o fixups-r7780rp.o
19obj-$(CONFIG_SH_TITAN) += ops-titan.o 19obj-$(CONFIG_SH_TITAN) += ops-titan.o
20obj-$(CONFIG_SH_LANDISK) += ops-landisk.o 20obj-$(CONFIG_SH_LANDISK) += ops-landisk.o
21obj-$(CONFIG_SH_LBOX_RE2) += ops-lboxre2.o fixups-lboxre2.o 21obj-$(CONFIG_SH_LBOX_RE2) += ops-lboxre2.o fixups-lboxre2.o
22obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += ops-se7780.o fixups-se7780.o
diff --git a/arch/sh/drivers/pci/fixups-se7780.c b/arch/sh/drivers/pci/fixups-se7780.c
new file mode 100644
index 000000000000..880cea1c0d89
--- /dev/null
+++ b/arch/sh/drivers/pci/fixups-se7780.c
@@ -0,0 +1,60 @@
1/*
2 * arch/sh/drivers/pci/fixups-se7780.c
3 *
4 * HITACHI UL Solution Engine 7780 PCI fixups
5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc.
7 * Copyright (C) 2004 - 2006 Paul Mundt
8 * Copyright (C) 2006 Nobuhiro Iwamatsu
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <linux/pci.h>
15#include "pci-sh4.h"
16#include <asm/io.h>
17
18int pci_fixup_pcic(void)
19{
20 ctrl_outl(0x00000001, SH7780_PCI_VCR2);
21
22 /* Enable all interrupts, so we know what to fix */
23 pci_write_reg(0x0000C3FF, SH7780_PCIIMR);
24 pci_write_reg(0x0000380F, SH7780_PCIAINTM);
25
26 /* Set up standard PCI config registers */
27 ctrl_outw(0xFB00, PCI_REG(SH7780_PCISTATUS));
28 ctrl_outw(0x0047, PCI_REG(SH7780_PCICMD));
29 ctrl_outb( 0x00, PCI_REG(SH7780_PCIPIF));
30 ctrl_outb( 0x00, PCI_REG(SH7780_PCISUB));
31 ctrl_outb( 0x06, PCI_REG(SH7780_PCIBCC));
32 ctrl_outw(0x1912, PCI_REG(SH7780_PCISVID));
33 ctrl_outw(0x0001, PCI_REG(SH7780_PCISID));
34
35 pci_write_reg(0x08000000, SH7780_PCIMBAR0); /* PCI */
36 pci_write_reg(0x08000000, SH7780_PCILAR0); /* SHwy */
37 pci_write_reg(0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */
38
39 pci_write_reg(0x00000000, SH7780_PCIMBAR1);
40 pci_write_reg(0x00000000, SH7780_PCILAR1);
41 pci_write_reg(0x00000000, SH7780_PCILSR1);
42
43 pci_write_reg(0xAB000801, SH7780_PCIIBAR);
44
45 /*
46 * Set the MBR so PCI address is one-to-one with window,
47 * meaning all calls go straight through... use ifdef to
48 * catch erroneous assumption.
49 */
50 pci_write_reg(0xFD000000 , SH7780_PCIMBR0);
51 pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
52
53 /* Set IOBR for window containing area specified in pci.h */
54 pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR);
55 pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR);
56
57 pci_write_reg(0xA5000C01, SH7780_PCICR);
58
59 return 0;
60}
diff --git a/arch/sh/drivers/pci/ops-se7780.c b/arch/sh/drivers/pci/ops-se7780.c
new file mode 100644
index 000000000000..212674df5e13
--- /dev/null
+++ b/arch/sh/drivers/pci/ops-se7780.c
@@ -0,0 +1,96 @@
1/*
2 * linux/arch/sh/drivers/pci/ops-se7780.c
3 *
4 * Copyright (C) 2006 Nobuhiro Iwamatsu
5 *
6 * PCI initialization for the Hitachi UL Solution Engine 7780SE03
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pci.h>
16#include <asm/se7780.h>
17#include <asm/io.h>
18#include "pci-sh4.h"
19
20/*
21 * IDSEL = AD16 PCI slot
22 * IDSEL = AD17 PCI slot
23 * IDSEL = AD18 Serial ATA Controller (Silicon Image SiL3512A)
24 * IDSEL = AD19 USB Host Controller (NEC uPD7210100A)
25 */
26
27/* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */
28static char se7780_irq_tab[4][16] __initdata = {
29 /* INTA */
30 { 65, 68, 67, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
31 /* INTB */
32 { 66, 65, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
33 /* INTC */
34 { 67, 66, -1, 66, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
35 /* INTD */
36 { 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
37};
38
39int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
40{
41 return se7780_irq_tab[pin-1][slot];
42}
43
44static struct resource se7780_io_resource = {
45 .name = "SH7780_IO",
46 .start = 0x2000,
47 .end = 0x2000 + SH7780_PCI_IO_SIZE - 1,
48 .flags = IORESOURCE_IO
49};
50
51static struct resource se7780_mem_resource = {
52 .name = "SH7780_mem",
53 .start = SH7780_PCI_MEMORY_BASE,
54 .end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
55 .flags = IORESOURCE_MEM
56};
57
58extern struct pci_ops se7780_pci_ops;
59
60struct pci_channel board_pci_channels[] = {
61 { &sh4_pci_ops, &se7780_io_resource, &se7780_mem_resource, 0, 0xff },
62 { NULL, NULL, NULL, 0, 0 },
63};
64EXPORT_SYMBOL(board_pci_channels);
65
66static struct sh4_pci_address_map se7780_pci_map = {
67 .window0 = {
68 .base = SH7780_CS2_BASE_ADDR,
69 .size = 0x04000000,
70 },
71 .flags = SH4_PCIC_NO_RESET,
72};
73
74int __init pcibios_init_platform(void)
75{
76 printk("SH7780 PCI: Finished initialization of the PCI controller\n");
77
78 /*
79 * FPGA PCISEL register initialize
80 *
81 * CPU || SLOT1 | SLOT2 | S-ATA | USB
82 * -------------------------------------
83 * INTA || INTA | INTD | -- | INTB
84 * -------------------------------------
85 * INTB || INTB | INTA | -- | INTC
86 * -------------------------------------
87 * INTC || INTC | INTB | INTA | --
88 * -------------------------------------
89 * INTD || INTD | INTC | -- | INTA
90 * -------------------------------------
91 */
92 ctrl_outw(0x0013, FPGA_PCI_INTSEL1);
93 ctrl_outw(0xE402, FPGA_PCI_INTSEL2);
94
95 return sh7780_pcic_init(&se7780_pci_map);
96}