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authorJamie Lenehan <lenehan@twibble.org>2006-10-30 22:35:02 -0500
committerPaul Mundt <lethal@linux-sh.org>2006-10-30 22:53:28 -0500
commitbd71ab88deab3358241f22ed6c035c427aacc4e7 (patch)
tree632aa998acac7feb7df79684f4c382a6d6bf2294 /arch/sh/drivers
parent1f6c526c409ed7ecdd02469c46ab4b4a50ebec45 (diff)
sh: Fix IPR-IRQ's for IRQ-chip change breakage.
The conversion from IPR-IRQ to IRQ-chip resulted in the ipr data being allocated in a local variable in make_ipr_irq - breaking anything using IPR interrupts. This changes all of the callers of make_ipr_irq to allocate a static structure containing the IPR data which is then passed to make_ipr_irq. This removes the need for make_ipr_irq to allocate any additional space for the IPR information. Signed-off-by: Jamie Lenehan <lenehan@twibble.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers')
-rw-r--r--arch/sh/drivers/dma/dma-sh.c42
1 files changed, 26 insertions, 16 deletions
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c
index d8ece20bb2cf..660786013350 100644
--- a/arch/sh/drivers/dma/dma-sh.c
+++ b/arch/sh/drivers/dma/dma-sh.c
@@ -19,23 +19,34 @@
19#include <asm/io.h> 19#include <asm/io.h>
20#include "dma-sh.h" 20#include "dma-sh.h"
21 21
22static inline unsigned int get_dmte_irq(unsigned int chan)
23{
24 unsigned int irq = 0;
25 22
23
24#ifdef CONFIG_CPU_SH4
25static struct ipr_data dmae_ipr_map[] = {
26 { DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
27};
28#endif
29static struct ipr_data dmte_ipr_map[] = {
26 /* 30 /*
27 * Normally we could just do DMTE0_IRQ + chan outright, though in the 31 * Normally we could just do DMTE0_IRQ + chan outright, though in the
28 * case of the 7751R, the DMTE IRQs for channels > 4 start right above 32 * case of the 7751R, the DMTE IRQs for channels > 4 start right above
29 * the SCIF 33 * the SCIF
30 */ 34 */
31 if (chan < 4) { 35 { DMTE0_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
32 irq = DMTE0_IRQ + chan; 36 { DMTE0_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
33 } else { 37 { DMTE0_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
34#ifdef DMTE4_IRQ 38 { DMTE0_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
35 irq = DMTE4_IRQ + chan - 4; 39 { DMTE4_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
36#endif 40 { DMTE4_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
37 } 41 { DMTE4_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
42 { DMTE4_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
43};
38 44
45static inline unsigned int get_dmte_irq(unsigned int chan)
46{
47 unsigned int irq = 0;
48 if (chan < ARRAY_SIZE(dmte_ipr_map))
49 irq = dmte_ipr_map[chan].irq;
39 return irq; 50 return irq;
40} 51}
41 52
@@ -258,17 +269,16 @@ static int __init sh_dmac_init(void)
258 int i; 269 int i;
259 270
260#ifdef CONFIG_CPU_SH4 271#ifdef CONFIG_CPU_SH4
261 make_ipr_irq(DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); 272 make_ipr_irq(dmae_ipr_map, ARRAY_SIZE(dmae_ipr_map));
262 i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0); 273 i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0);
263 if (unlikely(i < 0)) 274 if (unlikely(i < 0))
264 return i; 275 return i;
265#endif 276#endif
266 277
267 for (i = 0; i < info->nr_channels; i++) { 278 i = info->nr_channels;
268 int irq = get_dmte_irq(i); 279 if (i > ARRAY_SIZE(dmte_ipr_map))
269 280 i = ARRAY_SIZE(dmte_ipr_map);
270 make_ipr_irq(irq, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); 281 make_ipr_irq(dmte_ipr_map, i);
271 }
272 282
273 /* 283 /*
274 * Initialize DMAOR, and clean up any error flags that may have 284 * Initialize DMAOR, and clean up any error flags that may have