Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (197 commits)
  sh: add spi header and r2d platform data V3
  sh: update r7780rp interrupt code
  sh: remove consistent alloc stuff from the machine vector
  sh: use declared coherent memory for dreamcast pci ethernet adapter
  sh: declared coherent memory support V2
  sh: Add support for SDK7780 board.
  sh: constify function pointer tables
  sh: Kill off -traditional for linker script.
  cdrom: Add support for Sega Dreamcast GD-ROM.
  sh: Kill off hs7751rvoip reference from arch/sh/Kconfig.
  sh: Drop r7780rp_defconfig, use r7780mp_defconfig as kbuild default.
  sh: Kill off dead HS771RVoIP board support.
  sh: r7785rp: Fix up DECLARE_INTC_DESC() arg mismatch.
  sh: r7785rp: Hook up the rest of the HL7785 FPGA IRQ vectors.
  sh: r2d - enable sm501 usb host function
  sh: remove voyagergx
  sh: r2d - add lcd planel timings to sm501 platform data
  sh: Add OHCI and UDC platform devices for SH7720.
  sh: intc - remove default interrupt priority tables
  sh: Correct pte size mismatch for X2 TLB.
  ...

17 files changed, 686 insertions, 91 deletions

diff --git a/arch/sh/drivers/dma/Kconfig b/arch/sh/drivers/dma/Kconfig
index 4e711a0c3dae..01936368b8b0 100644
--- a/arch/sh/drivers/dma/Kconfig
+++ b/arch/sh/drivers/dma/Kconfig
@@ -12,7 +12,7 @@ config SH_DMA
 config NR_ONCHIP_DMA_CHANNELS
         int
         depends on SH_DMA
-        default "6" if CPU_SUBTYPE_SH7720
+        default "6" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
         default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
         default "12" if CPU_SUBTYPE_SH7780
         default "4"
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c
index 958bac1c585a..5c3359756a92 100644
--- a/arch/sh/drivers/dma/dma-sh.c
+++ b/arch/sh/drivers/dma/dma-sh.c
@@ -25,6 +25,7 @@ static int dmte_irq_map[] = {
         DMTE2_IRQ,
         DMTE3_IRQ,
 #if defined(CONFIG_CPU_SUBTYPE_SH7720)  ||      \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)  ||      \
     defined(CONFIG_CPU_SUBTYPE_SH7751R) ||      \
     defined(CONFIG_CPU_SUBTYPE_SH7760)  ||      \
     defined(CONFIG_CPU_SUBTYPE_SH7709)  ||      \
@@ -203,6 +204,7 @@ static int sh_dmac_get_dma_residue(struct dma_channel *chan)
 }
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721) || \
     defined(CONFIG_CPU_SUBTYPE_SH7780)
 #define dmaor_read_reg()        ctrl_inw(DMAOR)
 #define dmaor_write_reg(data)   ctrl_outw(data, DMAOR)
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index fba6b5ba0b3a..0718805774e8 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -7,16 +7,19 @@ obj-$(CONFIG_PCI_AUTO)			+= pci-auto.o
 
 obj-$(CONFIG_CPU_SUBTYPE_SH7751)        += pci-sh7751.o ops-sh4.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7751R)       += pci-sh7751.o ops-sh4.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7763)        += pci-sh7780.o ops-sh4.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7780)        += pci-sh7780.o ops-sh4.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7785)        += pci-sh7780.o ops-sh4.o
+obj-$(CONFIG_CPU_SH5)                   += pci-sh5.o ops-sh5.o
 
-obj-$(CONFIG_SH_DREAMCAST)              += ops-dreamcast.o fixups-dreamcast.o \
-                                           dma-dreamcast.o
+obj-$(CONFIG_SH_DREAMCAST)              += ops-dreamcast.o fixups-dreamcast.o
 obj-$(CONFIG_SH_SECUREEDGE5410)         += ops-snapgear.o
 obj-$(CONFIG_SH_RTS7751R2D)             += ops-rts7751r2d.o fixups-rts7751r2d.o
 obj-$(CONFIG_SH_SH03)                   += ops-sh03.o fixups-sh03.o
 obj-$(CONFIG_SH_HIGHLANDER)             += ops-r7780rp.o fixups-r7780rp.o
+obj-$(CONFIG_SH_SDK7780)                += ops-sdk7780.o fixups-sdk7780.o
 obj-$(CONFIG_SH_TITAN)                  += ops-titan.o
 obj-$(CONFIG_SH_LANDISK)                += ops-landisk.o
 obj-$(CONFIG_SH_LBOX_RE2)               += ops-lboxre2.o fixups-lboxre2.o
 obj-$(CONFIG_SH_7780_SOLUTION_ENGINE)   += ops-se7780.o fixups-se7780.o
+obj-$(CONFIG_SH_CAYMAN)                 += ops-cayman.o
diff --git a/arch/sh/drivers/pci/dma-dreamcast.c b/arch/sh/drivers/pci/dma-dreamcast.c
deleted file mode 100644
index 888a34050599..000000000000
--- a/arch/sh/drivers/pci/dma-dreamcast.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * arch/sh/drivers/pci/dma-dreamcast.c
- *
- * PCI DMA support for the Sega Dreamcast
- *
- * Copyright (C) 2001, 2002  M. R. Brown
- * Copyright (C) 2002, 2003  Paul Mundt
- *
- * This file originally bore the message (with enclosed-$):
- *      Id: pci.c,v 1.3 2003/05/04 19:29:46 lethal Exp
- *      Dreamcast PCI: Supports SEGA Broadband Adaptor only.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/pci.h>
-#include <linux/dma-mapping.h>
-#include <linux/device.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/mach/pci.h>
-
-static int gapspci_dma_used = 0;
-
-void *dreamcast_consistent_alloc(struct device *dev, size_t size,
-                                 dma_addr_t *dma_handle, gfp_t flag)
-{
-        unsigned long buf;
-
-        if (dev && dev->bus != &pci_bus_type)
-                return NULL;
-
-        if (gapspci_dma_used + size > GAPSPCI_DMA_SIZE)
-                return ERR_PTR(-EINVAL);
-
-        buf = GAPSPCI_DMA_BASE + gapspci_dma_used;
-
-        gapspci_dma_used = PAGE_ALIGN(gapspci_dma_used+size);
-
-        *dma_handle = (dma_addr_t)buf;
-
-        buf = P2SEGADDR(buf);
-
-        /* Flush the dcache before we hand off the buffer */
-        __flush_purge_region((void *)buf, size);
-
-        return (void *)buf;
-}
-
-int dreamcast_consistent_free(struct device *dev, size_t size,
-                         void *vaddr, dma_addr_t dma_handle)
-{
-        if (dev && dev->bus != &pci_bus_type)
-                return -EINVAL;
-
-        /* XXX */
-        gapspci_dma_used = 0;
-
-        return 0;
-}
-
diff --git a/arch/sh/drivers/pci/fixups-dreamcast.c b/arch/sh/drivers/pci/fixups-dreamcast.c
index 6f53f8200dc3..c44699301eeb 100644
--- a/arch/sh/drivers/pci/fixups-dreamcast.c
+++ b/arch/sh/drivers/pci/fixups-dreamcast.c
@@ -22,6 +22,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/pci.h>
+#include <linux/dma-mapping.h>
 
 #include <asm/io.h>
 #include <asm/irq.h>
@@ -40,6 +41,15 @@ static void __init gapspci_fixup_resources(struct pci_dev *dev)
                  */
                 dev->resource[1].start  = p->io_resource->start  + 0x100;
                 dev->resource[1].end    = dev->resource[1].start + 0x200 - 1;
+                /*
+                 * Redirect dma memory allocations to special memory window.
+                 */
+                BUG_ON(!dma_declare_coherent_memory(&dev->dev,
+                                                GAPSPCI_DMA_BASE,
+                                                GAPSPCI_DMA_BASE,
+                                                GAPSPCI_DMA_SIZE,
+                                                DMA_MEMORY_MAP |
+                                                DMA_MEMORY_EXCLUSIVE));
                 break;
         default:
                 printk("PCI: Failed resource fixup\n");
diff --git a/arch/sh/drivers/pci/fixups-sdk7780.c b/arch/sh/drivers/pci/fixups-sdk7780.c
new file mode 100644
index 000000000000..2f8863099dd1
--- /dev/null
+++ b/arch/sh/drivers/pci/fixups-sdk7780.c
@@ -0,0 +1,59 @@
+/*
+ * arch/sh/drivers/pci/fixups-sdk7780.c
+ *
+ * PCI fixups for the SDK7780SE03
+ *
+ * Copyright (C) 2003  Lineo uSolutions, Inc.
+ * Copyright (C) 2004 - 2006  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/pci.h>
+#include "pci-sh4.h"
+#include <asm/io.h>
+
+int pci_fixup_pcic(void)
+{
+        ctrl_outl(0x00000001, SH7780_PCI_VCR2);
+
+        /* Enable all interrupts, so we know what to fix */
+        pci_write_reg(0x0000C3FF, SH7780_PCIIMR);
+        pci_write_reg(0x0000380F, SH7780_PCIAINTM);
+
+        /* Set up standard PCI config registers */
+        pci_write_reg(0xFB00, SH7780_PCISTATUS);
+        pci_write_reg(0x0047, SH7780_PCICMD);
+        pci_write_reg(0x00, SH7780_PCIPIF);
+        pci_write_reg(0x00, SH7780_PCISUB);
+        pci_write_reg(0x06, SH7780_PCIBCC);
+        pci_write_reg(0x1912, SH7780_PCISVID);
+        pci_write_reg(0x0001, SH7780_PCISID);
+
+        pci_write_reg(0x08000000, SH7780_PCIMBAR0);     /* PCI */
+        pci_write_reg(0x08000000, SH7780_PCILAR0);      /* SHwy */
+        pci_write_reg(0x07F00001, SH7780_PCILSR);       /* size 128M w/ MBAR */
+
+        pci_write_reg(0x00000000, SH7780_PCIMBAR1);
+        pci_write_reg(0x00000000, SH7780_PCILAR1);
+        pci_write_reg(0x00000000, SH7780_PCILSR1);
+
+        pci_write_reg(0xAB000801, SH7780_PCIIBAR);
+
+        /*
+         * Set the MBR so PCI address is one-to-one with window,
+         * meaning all calls go straight through... use ifdef to
+         * catch erroneous assumption.
+         */
+        pci_write_reg(0xFD000000 , SH7780_PCIMBR0);
+        pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0);    /* 16M */
+
+        /* Set IOBR for window containing area specified in pci.h */
+        pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR);
+        pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR);
+
+        pci_write_reg(0xA5000C01, SH7780_PCICR);
+
+        return 0;
+}
diff --git a/arch/sh/drivers/pci/ops-cayman.c b/arch/sh/drivers/pci/ops-cayman.c
new file mode 100644
index 000000000000..980275ffa30b
--- /dev/null
+++ b/arch/sh/drivers/pci/ops-cayman.c
@@ -0,0 +1,94 @@
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <asm/cpu/irq.h>
+#include "pci-sh5.h"
+
+static inline u8 bridge_swizzle(u8 pin, u8 slot)
+{
+        return (((pin - 1) + slot) % 4) + 1;
+}
+
+int __init pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int result = -1;
+
+        /* The complication here is that the PCI IRQ lines from the Cayman's 2
+           5V slots get into the CPU via a different path from the IRQ lines
+           from the 3 3.3V slots.  Thus, we have to detect whether the card's
+           interrupts go via the 5V or 3.3V path, i.e. the 'bridge swizzling'
+           at the point where we cross from 5V to 3.3V is not the normal case.
+
+           The added complication is that we don't know that the 5V slots are
+           always bus 2, because a card containing a PCI-PCI bridge may be
+           plugged into a 3.3V slot, and this changes the bus numbering.
+
+           Also, the Cayman has an intermediate PCI bus that goes a custom
+           expansion board header (and to the secondary bridge).  This bus has
+           never been used in practice.
+
+           The 1ary onboard PCI-PCI bridge is device 3 on bus 0
+           The 2ary onboard PCI-PCI bridge is device 0 on the 2ary bus of
+           the 1ary bridge.
+           */
+
+        struct slot_pin {
+                int slot;
+                int pin;
+        } path[4];
+        int i=0;
+
+        while (dev->bus->number > 0) {
+
+                slot = path[i].slot = PCI_SLOT(dev->devfn);
+                pin = path[i].pin = bridge_swizzle(pin, slot);
+                dev = dev->bus->self;
+                i++;
+                if (i > 3) panic("PCI path to root bus too long!\n");
+        }
+
+        slot = PCI_SLOT(dev->devfn);
+        /* This is the slot on bus 0 through which the device is eventually
+           reachable. */
+
+        /* Now work back up. */
+        if ((slot < 3) || (i == 0)) {
+                /* Bus 0 (incl. PCI-PCI bridge itself) : perform the final
+                   swizzle now. */
+                result = IRQ_INTA + bridge_swizzle(pin, slot) - 1;
+        } else {
+                i--;
+                slot = path[i].slot;
+                pin  = path[i].pin;
+                if (slot > 0) {
+                        panic("PCI expansion bus device found - not handled!\n");
+                } else {
+                        if (i > 0) {
+                                /* 5V slots */
+                                i--;
+                                slot = path[i].slot;
+                                pin  = path[i].pin;
+                                /* 'pin' was swizzled earlier wrt slot, don't do it again. */
+                                result = IRQ_P2INTA + (pin - 1);
+                        } else {
+                                /* IRQ for 2ary PCI-PCI bridge : unused */
+                                result = -1;
+                        }
+                }
+        }
+
+        return result;
+}
+
+struct pci_channel board_pci_channels[] = {
+        { &sh5_pci_ops, NULL, NULL, 0, 0xff },
+        { NULL, NULL, NULL, 0, 0 },
+};
+EXPORT_SYMBOL(board_pci_channels);
+
+int __init pcibios_init_platform(void)
+{
+        return sh5pci_init(__pa(memory_start),
+                           __pa(memory_end) - __pa(memory_start));
+}
diff --git a/arch/sh/drivers/pci/ops-r7780rp.c b/arch/sh/drivers/pci/ops-r7780rp.c
index 48fe4032ebea..5fdadaeed6fc 100644
--- a/arch/sh/drivers/pci/ops-r7780rp.c
+++ b/arch/sh/drivers/pci/ops-r7780rp.c
@@ -17,25 +17,13 @@
 #include <asm/io.h>
 #include "pci-sh4.h"
 
-static char r7780rp_irq_tab[] __initdata = {
-        0, 1, 2, 3,
-};
-
-static char r7780mp_irq_tab[] __initdata = {
+static char irq_tab[] __initdata = {
         65, 66, 67, 68,
 };
 
 int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
 {
-        if (mach_is_r7780rp())
-                return r7780rp_irq_tab[slot];
-        if (mach_is_r7780mp() || mach_is_r7785rp())
-                return r7780mp_irq_tab[slot];
-
-        printk(KERN_ERR "PCI: Bad IRQ mapping "
-               "request for slot %d, func %d\n", slot, pin-1);
-
-        return -1;
+        return irq_tab[slot];
 }
 
 static struct resource sh7780_io_resource = {
diff --git a/arch/sh/drivers/pci/ops-sdk7780.c b/arch/sh/drivers/pci/ops-sdk7780.c
new file mode 100644
index 000000000000..66a9b4047f26
--- /dev/null
+++ b/arch/sh/drivers/pci/ops-sdk7780.c
@@ -0,0 +1,73 @@
+/*
+ * linux/arch/sh/drivers/pci/ops-sdk7780.c
+ *
+ * Copyright (C) 2006  Nobuhiro Iwamatsu
+ *
+ * PCI initialization for the SDK7780SE03
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <asm/sdk7780.h>
+#include <asm/io.h>
+#include "pci-sh4.h"
+
+/* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */
+static char sdk7780_irq_tab[4][16] __initdata = {
+        /* INTA */
+        { 65, 68, 67, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
+        /* INTB */
+        { 66, 65, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
+        /* INTC */
+        { 67, 66, -1, 66, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
+        /* INTD */
+        { 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
+};
+
+int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
+{
+       return sdk7780_irq_tab[pin-1][slot];
+}
+
+static struct resource sdk7780_io_resource = {
+        .name   = "SH7780_IO",
+        .start  = SH7780_PCI_IO_BASE,
+        .end    = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
+        .flags  = IORESOURCE_IO
+};
+
+static struct resource sdk7780_mem_resource = {
+        .name   = "SH7780_mem",
+        .start  = SH7780_PCI_MEMORY_BASE,
+        .end    = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
+        .flags  = IORESOURCE_MEM
+};
+
+struct pci_channel board_pci_channels[] = {
+        { &sh4_pci_ops, &sdk7780_io_resource, &sdk7780_mem_resource, 0, 0xff },
+        { NULL, NULL, NULL, 0, 0 },
+};
+EXPORT_SYMBOL(board_pci_channels);
+
+static struct sh4_pci_address_map sdk7780_pci_map = {
+        .window0        = {
+                .base   = SH7780_CS2_BASE_ADDR,
+                .size   = 0x04000000,
+        },
+        .window1        = {
+                .base   = SH7780_CS3_BASE_ADDR,
+                .size   = 0x04000000,
+        },
+        .flags  = SH4_PCIC_NO_RESET,
+};
+
+int __init pcibios_init_platform(void)
+{
+        printk(KERN_INFO "SH7780 PCI: Finished initializing PCI controller\n");
+        return sh7780_pcic_init(&sdk7780_pci_map);
+}
diff --git a/arch/sh/drivers/pci/ops-sh5.c b/arch/sh/drivers/pci/ops-sh5.c
new file mode 100644
index 000000000000..729e38a6fe07
--- /dev/null
+++ b/arch/sh/drivers/pci/ops-sh5.c
@@ -0,0 +1,93 @@
+/*
+ * Support functions for the SH5 PCI hardware.
+ *
+ * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
+ * Copyright (C) 2003, 2004 Paul Mundt
+ * Copyright (C) 2004 Richard Curnow
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ */
+#include <linux/kernel.h>
+#include <linux/rwsem.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/types.h>
+#include <linux/irq.h>
+#include <asm/pci.h>
+#include <asm/io.h>
+#include "pci-sh5.h"
+
+static void __init pci_fixup_ide_bases(struct pci_dev *d)
+{
+        int i;
+
+        /*
+         * PCI IDE controllers use non-standard I/O port decoding, respect it.
+         */
+        if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
+                return;
+        printk("PCI: IDE base address fixup for %s\n", pci_name(d));
+        for(i=0; i<4; i++) {
+                struct resource *r = &d->resource[i];
+                if ((r->start & ~0x80) == 0x374) {
+                        r->start |= 2;
+                        r->end = r->start;
+                }
+        }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
+
+char * __devinit pcibios_setup(char *str)
+{
+        return str;
+}
+
+static int sh5pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+                        int size, u32 *val)
+{
+        SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
+
+        switch (size) {
+                case 1:
+                        *val = (u8)SH5PCI_READ_BYTE(PDR + (where & 3));
+                        break;
+                case 2:
+                        *val = (u16)SH5PCI_READ_SHORT(PDR + (where & 2));
+                        break;
+                case 4:
+                        *val = SH5PCI_READ(PDR);
+                        break;
+        }
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int sh5pci_write(struct pci_bus *bus, unsigned int devfn, int where,
+                         int size, u32 val)
+{
+        SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
+
+        switch (size) {
+                case 1:
+                        SH5PCI_WRITE_BYTE(PDR + (where & 3), (u8)val);
+                        break;
+                case 2:
+                        SH5PCI_WRITE_SHORT(PDR + (where & 2), (u16)val);
+                        break;
+                case 4:
+                        SH5PCI_WRITE(PDR, val);
+                        break;
+        }
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+struct pci_ops sh5_pci_ops = {
+        .read           = sh5pci_read,
+        .write          = sh5pci_write,
+};
diff --git a/arch/sh/drivers/pci/pci-auto.c b/arch/sh/drivers/pci/pci-auto.c
index 224e007736fb..ea404704ace8 100644
--- a/arch/sh/drivers/pci/pci-auto.c
+++ b/arch/sh/drivers/pci/pci-auto.c
@@ -516,10 +516,8 @@ pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
                                          PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
                                          PCI_COMMAND_MEMORY |
                                          PCI_COMMAND_MASTER);
-#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
                 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
                                         PCI_LATENCY_TIMER, 0x80);
-#endif
 
                 /* Allocate PCI I/O and/or memory space */
                 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_5);
diff --git a/arch/sh/drivers/pci/pci-sh4.h b/arch/sh/drivers/pci/pci-sh4.h
index 1901c33cde6a..4925c79ea959 100644
--- a/arch/sh/drivers/pci/pci-sh4.h
+++ b/arch/sh/drivers/pci/pci-sh4.h
@@ -1,7 +1,9 @@
 #ifndef __PCI_SH4_H
 #define __PCI_SH4_H
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
+#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7785) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7763)
 #include "pci-sh7780.h"
 #else
 #include "pci-sh7751.h"
diff --git a/arch/sh/drivers/pci/pci-sh5.c b/arch/sh/drivers/pci/pci-sh5.c
new file mode 100644
index 000000000000..a00a4df8c02d
--- /dev/null
+++ b/arch/sh/drivers/pci/pci-sh5.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
+ * Copyright (C) 2003, 2004 Paul Mundt
+ * Copyright (C) 2004 Richard Curnow
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * Support functions for the SH5 PCI hardware.
+ */
+
+#include <linux/kernel.h>
+#include <linux/rwsem.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/types.h>
+#include <linux/irq.h>
+#include <asm/cpu/irq.h>
+#include <asm/pci.h>
+#include <asm/io.h>
+#include "pci-sh5.h"
+
+unsigned long pcicr_virt;
+unsigned long PCI_IO_AREA;
+
+/* Rounds a number UP to the nearest power of two. Used for
+ * sizing the PCI window.
+ */
+static u32 __init r2p2(u32 num)
+{
+        int i = 31;
+        u32 tmp = num;
+
+        if (num == 0)
+                return 0;
+
+        do {
+                if (tmp & (1 << 31))
+                        break;
+                i--;
+                tmp <<= 1;
+        } while (i >= 0);
+
+        tmp = 1 << i;
+        /* If the original number isn't a power of 2, round it up */
+        if (tmp != num)
+                tmp <<= 1;
+
+        return tmp;
+}
+
+static irqreturn_t pcish5_err_irq(int irq, void *dev_id)
+{
+        struct pt_regs *regs = get_irq_regs();
+        unsigned pci_int, pci_air, pci_cir, pci_aint;
+
+        pci_int = SH5PCI_READ(INT);
+        pci_cir = SH5PCI_READ(CIR);
+        pci_air = SH5PCI_READ(AIR);
+
+        if (pci_int) {
+                printk("PCI INTERRUPT (at %08llx)!\n", regs->pc);
+                printk("PCI INT -> 0x%x\n", pci_int & 0xffff);
+                printk("PCI AIR -> 0x%x\n", pci_air);
+                printk("PCI CIR -> 0x%x\n", pci_cir);
+                SH5PCI_WRITE(INT, ~0);
+        }
+
+        pci_aint = SH5PCI_READ(AINT);
+        if (pci_aint) {
+                printk("PCI ARB INTERRUPT!\n");
+                printk("PCI AINT -> 0x%x\n", pci_aint);
+                printk("PCI AIR -> 0x%x\n", pci_air);
+                printk("PCI CIR -> 0x%x\n", pci_cir);
+                SH5PCI_WRITE(AINT, ~0);
+        }
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t pcish5_serr_irq(int irq, void *dev_id)
+{
+        printk("SERR IRQ\n");
+
+        return IRQ_NONE;
+}
+
+int __init sh5pci_init(unsigned long memStart, unsigned long memSize)
+{
+        u32 lsr0;
+        u32 uval;
+
+        if (request_irq(IRQ_ERR, pcish5_err_irq,
+                        IRQF_DISABLED, "PCI Error",NULL) < 0) {
+                printk(KERN_ERR "PCISH5: Cannot hook PCI_PERR interrupt\n");
+                return -EINVAL;
+        }
+
+        if (request_irq(IRQ_SERR, pcish5_serr_irq,
+                        IRQF_DISABLED, "PCI SERR interrupt", NULL) < 0) {
+                printk(KERN_ERR "PCISH5: Cannot hook PCI_SERR interrupt\n");
+                return -EINVAL;
+        }
+
+        pcicr_virt = onchip_remap(SH5PCI_ICR_BASE, 1024, "PCICR");
+        if (!pcicr_virt) {
+                panic("Unable to remap PCICR\n");
+        }
+
+        PCI_IO_AREA = onchip_remap(SH5PCI_IO_BASE, 0x10000, "PCIIO");
+        if (!PCI_IO_AREA) {
+                panic("Unable to remap PCIIO\n");
+        }
+
+        /* Clear snoop registers */
+        SH5PCI_WRITE(CSCR0, 0);
+        SH5PCI_WRITE(CSCR1, 0);
+
+        /* Switch off interrupts */
+        SH5PCI_WRITE(INTM,  0);
+        SH5PCI_WRITE(AINTM, 0);
+        SH5PCI_WRITE(PINTM, 0);
+
+        /* Set bus active, take it out of reset */
+        uval = SH5PCI_READ(CR);
+
+        /* Set command Register */
+        SH5PCI_WRITE(CR, uval | CR_LOCK_MASK | CR_CFINT| CR_FTO | CR_PFE |
+                     CR_PFCS | CR_BMAM);
+
+        uval=SH5PCI_READ(CR);
+
+        /* Allow it to be a master */
+        /* NB - WE DISABLE I/O ACCESS to stop overlap */
+        /* set WAIT bit to enable stepping, an attempt to improve stability */
+        SH5PCI_WRITE_SHORT(CSR_CMD,
+                            PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+                            PCI_COMMAND_WAIT);
+
+        /*
+        ** Set translation mapping memory in order to convert the address
+        ** used for the main bus, to the PCI internal address.
+        */
+        SH5PCI_WRITE(MBR,0x40000000);
+
+        /* Always set the max size 512M */
+        SH5PCI_WRITE(MBMR, PCISH5_MEM_SIZCONV(512*1024*1024));
+
+        /*
+        ** I/O addresses are mapped at internal PCI specific address
+        ** as is described into the configuration bridge table.
+        ** These are changed to 0, to allow cards that have legacy
+        ** io such as vga to function correctly. We set the SH5 IOBAR to
+        ** 256K, which is a bit big as we can only have 64K of address space
+        */
+
+        SH5PCI_WRITE(IOBR,0x0);
+
+        /* Set up a 256K window. Totally pointless waste  of address space */
+        SH5PCI_WRITE(IOBMR,0);
+
+        /* The SH5 has a HUGE 256K I/O region, which breaks the PCI spec.
+         * Ideally, we would want to map the I/O region somewhere, but it
+         * is so big this is not that easy!
+         */
+        SH5PCI_WRITE(CSR_IBAR0,~0);
+        /* Set memory size value */
+        memSize = memory_end - memory_start;
+
+        /* Now we set up the mbars so the PCI bus can see the memory of
+         * the machine */
+        if (memSize < (1024 * 1024)) {
+                printk(KERN_ERR "PCISH5: Ridiculous memory size of 0x%lx?\n",
+                       memSize);
+                return -EINVAL;
+        }
+
+        /* Set LSR 0 */
+        lsr0 = (memSize > (512 * 1024 * 1024)) ? 0x1ff00001 :
+                ((r2p2(memSize) - 0x100000) | 0x1);
+        SH5PCI_WRITE(LSR0, lsr0);
+
+        /* Set MBAR 0 */
+        SH5PCI_WRITE(CSR_MBAR0, memory_start);
+        SH5PCI_WRITE(LAR0, memory_start);
+
+        SH5PCI_WRITE(CSR_MBAR1,0);
+        SH5PCI_WRITE(LAR1,0);
+        SH5PCI_WRITE(LSR1,0);
+
+        /* Enable the PCI interrupts on the device */
+        SH5PCI_WRITE(INTM,  ~0);
+        SH5PCI_WRITE(AINTM, ~0);
+        SH5PCI_WRITE(PINTM, ~0);
+
+        return 0;
+}
+
+void __devinit pcibios_fixup_bus(struct pci_bus *bus)
+{
+        struct pci_dev *dev = bus->self;
+        int i;
+
+        if (dev) {
+                for (i= 0; i < 3; i++) {
+                        bus->resource[i] =
+                                &dev->resource[PCI_BRIDGE_RESOURCES+i];
+                        bus->resource[i]->name = bus->name;
+                }
+                bus->resource[0]->flags |= IORESOURCE_IO;
+                bus->resource[1]->flags |= IORESOURCE_MEM;
+
+                /* For now, propagate host limits to the bus;
+                 * we'll adjust them later. */
+                bus->resource[0]->end = 64*1024 - 1 ;
+                bus->resource[1]->end = PCIBIOS_MIN_MEM+(256*1024*1024)-1;
+                bus->resource[0]->start = PCIBIOS_MIN_IO;
+                bus->resource[1]->start = PCIBIOS_MIN_MEM;
+
+                /* Turn off downstream PF memory address range by default */
+                bus->resource[2]->start = 1024*1024;
+                bus->resource[2]->end = bus->resource[2]->start - 1;
+        }
+}
diff --git a/arch/sh/drivers/pci/pci-sh5.h b/arch/sh/drivers/pci/pci-sh5.h
new file mode 100644
index 000000000000..7cff3fc04d30
--- /dev/null
+++ b/arch/sh/drivers/pci/pci-sh5.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * Definitions for the SH5 PCI hardware.
+ */
+#ifndef __PCI_SH5_H
+#define __PCI_SH5_H
+
+/* Product ID */
+#define PCISH5_PID              0x350d
+
+/* vendor ID */
+#define PCISH5_VID              0x1054
+
+/* Configuration types */
+#define ST_TYPE0                0x00    /* Configuration cycle type 0 */
+#define ST_TYPE1                0x01    /* Configuration cycle type 1 */
+
+/* VCR data */
+#define PCISH5_VCR_STATUS      0x00
+#define PCISH5_VCR_VERSION     0x08
+
+/*
+** ICR register offsets and bits
+*/
+#define PCISH5_ICR_CR          0x100   /* PCI control register values */
+#define CR_PBAM                 (1<<12)
+#define CR_PFCS                 (1<<11)
+#define CR_FTO                  (1<<10)
+#define CR_PFE                  (1<<9)
+#define CR_TBS                  (1<<8)
+#define CR_SPUE                 (1<<7)
+#define CR_BMAM                 (1<<6)
+#define CR_HOST                 (1<<5)
+#define CR_CLKEN                (1<<4)
+#define CR_SOCS                 (1<<3)
+#define CR_IOCS                 (1<<2)
+#define CR_RSTCTL               (1<<1)
+#define CR_CFINT                (1<<0)
+#define CR_LOCK_MASK            0xa5000000
+
+#define PCISH5_ICR_INT         0x114   /* Interrupt registert values     */
+#define INT_MADIM               (1<<2)
+
+#define PCISH5_ICR_LSR0        0X104   /* Local space register values    */
+#define PCISH5_ICR_LSR1        0X108   /* Local space register values    */
+#define PCISH5_ICR_LAR0        0x10c   /* Local address register values  */
+#define PCISH5_ICR_LAR1        0x110   /* Local address register values  */
+#define PCISH5_ICR_INTM        0x118   /* Interrupt mask register values                         */
+#define PCISH5_ICR_AIR         0x11c   /* Interrupt error address information register values    */
+#define PCISH5_ICR_CIR         0x120   /* Interrupt error command information register values    */
+#define PCISH5_ICR_AINT        0x130   /* Interrupt error arbiter interrupt register values      */
+#define PCISH5_ICR_AINTM       0x134   /* Interrupt error arbiter interrupt mask register values */
+#define PCISH5_ICR_BMIR        0x138   /* Interrupt error info register of bus master values     */
+#define PCISH5_ICR_PAR         0x1c0   /* Pio address register values                            */
+#define PCISH5_ICR_MBR         0x1c4   /* Memory space bank register values                      */
+#define PCISH5_ICR_IOBR        0x1c8   /* I/O space bank register values                         */
+#define PCISH5_ICR_PINT        0x1cc   /* power management interrupt register values             */
+#define PCISH5_ICR_PINTM       0x1d0   /* power management interrupt mask register values        */
+#define PCISH5_ICR_MBMR        0x1d8   /* memory space bank mask register values                 */
+#define PCISH5_ICR_IOBMR       0x1dc   /* I/O space bank mask register values                    */
+#define PCISH5_ICR_CSCR0       0x210   /* PCI cache snoop control register 0                     */
+#define PCISH5_ICR_CSCR1       0x214   /* PCI cache snoop control register 1                     */
+#define PCISH5_ICR_PDR         0x220   /* Pio data register values                               */
+
+/* These are configs space registers */
+#define PCISH5_ICR_CSR_VID     0x000    /* Vendor id                           */
+#define PCISH5_ICR_CSR_DID     0x002   /* Device id                           */
+#define PCISH5_ICR_CSR_CMD     0x004   /* Command register                    */
+#define PCISH5_ICR_CSR_STATUS  0x006   /* Stautus                             */
+#define PCISH5_ICR_CSR_IBAR0   0x010   /* I/O base address register           */
+#define PCISH5_ICR_CSR_MBAR0   0x014   /* First  Memory base address register */
+#define PCISH5_ICR_CSR_MBAR1   0x018   /* Second Memory base address register */
+
+/* Base address of registers */
+#define SH5PCI_ICR_BASE (PHYS_PCI_BLOCK + 0x00040000)
+#define SH5PCI_IO_BASE  (PHYS_PCI_BLOCK + 0x00800000)
+/* #define SH5PCI_VCR_BASE (P2SEG_PCICB_BLOCK + P2SEG)    */
+
+extern unsigned long pcicr_virt;
+/* Register selection macro */
+#define PCISH5_ICR_REG(x)                ( pcicr_virt + (PCISH5_ICR_##x))
+/* #define PCISH5_VCR_REG(x)                ( SH5PCI_VCR_BASE (PCISH5_VCR_##x)) */
+
+/* Write I/O functions */
+#define SH5PCI_WRITE(reg,val)        ctrl_outl((u32)(val),PCISH5_ICR_REG(reg))
+#define SH5PCI_WRITE_SHORT(reg,val)  ctrl_outw((u16)(val),PCISH5_ICR_REG(reg))
+#define SH5PCI_WRITE_BYTE(reg,val)   ctrl_outb((u8)(val),PCISH5_ICR_REG(reg))
+
+/* Read I/O functions */
+#define SH5PCI_READ(reg)             ctrl_inl(PCISH5_ICR_REG(reg))
+#define SH5PCI_READ_SHORT(reg)       ctrl_inw(PCISH5_ICR_REG(reg))
+#define SH5PCI_READ_BYTE(reg)        ctrl_inb(PCISH5_ICR_REG(reg))
+
+/* Set PCI config bits */
+#define SET_CONFIG_BITS(bus,devfn,where)  ((((bus) << 16) | ((devfn) << 8) | ((where) & ~3)) | 0x80000000)
+
+/* Set PCI command register */
+#define CONFIG_CMD(bus, devfn, where)            SET_CONFIG_BITS(bus->number,devfn,where)
+
+/* Size converters */
+#define PCISH5_MEM_SIZCONV(x)             (((x / 0x40000) - 1) << 18)
+#define PCISH5_IO_SIZCONV(x)              (((x / 0x40000) - 1) << 18)
+
+extern struct pci_ops sh5_pci_ops;
+
+/* arch/sh/drivers/pci/pci-sh5.c */
+int sh5pci_init(unsigned long memStart, unsigned long memSize);
+
+#endif /* __PCI_SH5_H */
diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c
index e516087fb435..7d797f4de5e7 100644
--- a/arch/sh/drivers/pci/pci-sh7780.c
+++ b/arch/sh/drivers/pci/pci-sh7780.c
@@ -58,6 +58,7 @@ static int __init sh7780_pci_init(void)
         id = pci_read_reg(SH7780_PCIVID);
         if ((id & 0xffff) == SH7780_VENDOR_ID) {
                 switch ((id >> 16) & 0xffff) {
+                case SH7763_DEVICE_ID:
                 case SH7780_DEVICE_ID:
                 case SH7781_DEVICE_ID:
                 case SH7785_DEVICE_ID:
diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h
index 1d069a859de2..97b2c98f05c4 100644
--- a/arch/sh/drivers/pci/pci-sh7780.h
+++ b/arch/sh/drivers/pci/pci-sh7780.h
@@ -16,6 +16,7 @@
 #define SH7780_VENDOR_ID        0x1912
 #define SH7781_DEVICE_ID        0x0001
 #define SH7780_DEVICE_ID        0x0002
+#define SH7763_DEVICE_ID        0x0004
 #define SH7785_DEVICE_ID        0x0007
 
 /* SH7780 Control Registers */
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index ccaba368ac9b..49b435c3a57a 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -71,7 +71,7 @@ subsys_initcall(pcibios_init);
  *  Called after each bus is probed, but before its children
  *  are examined.
  */
-void __devinit pcibios_fixup_bus(struct pci_bus *bus)
+void __devinit __weak pcibios_fixup_bus(struct pci_bus *bus)
 {
         pci_read_bridge_bases(bus);
 }