Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6

* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (38 commits)
  sh: R7785RP board updates.
  sh: Update r7780rp defconfig.
  sh: Add die chain notifiers.
  sh: Fix APM emulation on hp6xx.
  sh: Wire up more IRQs for SH7709.
  sh: Solution Engine 7722 board support.
  sh: Fix r7780rp build.
  sh: kdump support.
  sh: Move clock reporting to its own proc entry.
  sh: Solution Engine SH7705 board and CPU updates.
  serial: sh-sci: Fix module clock refcount for serial console.
  serial: sh-sci: Fix module clock refcounting.
  sh: SH7722 clock framework support.
  sh: hp6xx pata_platform support.
  sh: Obey CONFIG_HZ for HZ definition.
  sh: Fix fstatat64() syscall.
  sh: se7780 PCI support.
  sh: SH7780 Solution Engine board support.
  sh: Add a dummy SH-4 PCIC fixup.
  sh: Tidy up L-BOX area5 addresses.
  ...

14 files changed, 361 insertions, 45 deletions

diff --git a/arch/sh/drivers/Kconfig b/arch/sh/drivers/Kconfig
index c54c758e6243..420c6b2f33a5 100644
--- a/arch/sh/drivers/Kconfig
+++ b/arch/sh/drivers/Kconfig
@@ -1,5 +1,15 @@
+source "arch/sh/drivers/dma/Kconfig"
+source "arch/sh/cchips/Kconfig"
+
 menu "Additional SuperH Device Drivers"
 
+config HEARTBEAT
+        bool "Heartbeat LED"
+        help
+          Use the power-on LED on your machine as a load meter.  The exact
+          behavior is platform-dependent, but normally the flash frequency is
+          a hyperbolic function of the 5-minute load average.
+
 config PUSH_SWITCH
         tristate "Push switch support"
         help
diff --git a/arch/sh/drivers/heartbeat.c b/arch/sh/drivers/heartbeat.c
index bc59cb6cd78b..23dd6080422f 100644
--- a/arch/sh/drivers/heartbeat.c
+++ b/arch/sh/drivers/heartbeat.c
@@ -40,16 +40,9 @@ static void heartbeat_timer(unsigned long data)
         static unsigned bit = 0, up = 1;
 
         ctrl_outw(1 << hd->bit_pos[bit], (unsigned long)hd->base);
-        if (up)
-                if (bit == (ARRAY_SIZE(hd->bit_pos) - 1)) {
-                        bit--;
-                        up = 0;
-                } else
-                        bit++;
-        else if (bit == 0)
-                up = 1;
-        else
-                bit--;
+        bit += up;
+        if ((bit == 0) || (bit == ARRAY_SIZE(hd->bit_pos)-1))
+                up = -up;
 
         mod_timer(&hd->timer, jiffies + (110 - ((300 << FSHIFT) /
                         ((avenrun[0] / 5) + (3 << FSHIFT)))));
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index cc8d0d0b1427..0e9b532b9fbc 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -8,12 +8,15 @@ obj-$(CONFIG_PCI_AUTO)			+= pci-auto.o
 obj-$(CONFIG_CPU_SUBTYPE_ST40STB1)      += pci-st40.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7751)        += pci-sh7751.o ops-sh4.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7780)        += pci-sh7780.o ops-sh4.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7785)        += pci-sh7780.o ops-sh4.o
 
 obj-$(CONFIG_SH_DREAMCAST)              += ops-dreamcast.o fixups-dreamcast.o \
                                            dma-dreamcast.o
 obj-$(CONFIG_SH_SECUREEDGE5410)         += ops-snapgear.o
 obj-$(CONFIG_SH_RTS7751R2D)             += ops-rts7751r2d.o fixups-rts7751r2d.o
 obj-$(CONFIG_SH_SH03)                   += ops-sh03.o fixups-sh03.o
-obj-$(CONFIG_SH_R7780RP)                += ops-r7780rp.o fixups-r7780rp.o
+obj-$(CONFIG_SH_HIGHLANDER)             += ops-r7780rp.o fixups-r7780rp.o
 obj-$(CONFIG_SH_TITAN)                  += ops-titan.o
 obj-$(CONFIG_SH_LANDISK)                += ops-landisk.o
+obj-$(CONFIG_SH_LBOX_RE2)               += ops-lboxre2.o fixups-lboxre2.o
+obj-$(CONFIG_SH_7780_SOLUTION_ENGINE)   += ops-se7780.o fixups-se7780.o
diff --git a/arch/sh/drivers/pci/fixups-lboxre2.c b/arch/sh/drivers/pci/fixups-lboxre2.c
new file mode 100644
index 000000000000..40b19bdfb891
--- /dev/null
+++ b/arch/sh/drivers/pci/fixups-lboxre2.c
@@ -0,0 +1,41 @@
+/*
+ * arch/sh/drivers/pci/fixups-lboxre2.c
+ *
+ * L-BOX RE2 PCI fixups
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include "pci-sh4.h"
+
+#define PCIMCR_MRSET_OFF        0xBFFFFFFF
+#define PCIMCR_RFSH_OFF         0xFFFFFFFB
+
+int pci_fixup_pcic(void)
+{
+        unsigned long bcr1, mcr;
+
+        bcr1 = inl(SH7751_BCR1);
+        bcr1 |= 0x40080000;     /* Enable Bit 19 BREQEN, set PCIC to slave */
+        pci_write_reg(bcr1, SH4_PCIBCR1);
+
+        /* Enable all interrupts, so we known what to fix */
+        pci_write_reg(0x0000c3ff, SH4_PCIINTM);
+        pci_write_reg(0x0000380f, SH4_PCIAINTM);
+        pci_write_reg(0xfb900047, SH7751_PCICONF1);
+        pci_write_reg(0xab000001, SH7751_PCICONF4);
+
+        mcr = inl(SH7751_MCR);
+        mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
+        pci_write_reg(mcr, SH4_PCIMCR);
+
+        pci_write_reg(0x0c000000, SH7751_PCICONF5);
+        pci_write_reg(0xd0000000, SH7751_PCICONF6);
+        pci_write_reg(0x0c000000, SH4_PCILAR0);
+        pci_write_reg(0x00000000, SH4_PCILAR1);
+
+        return 0;
+}
diff --git a/arch/sh/drivers/pci/fixups-se7780.c b/arch/sh/drivers/pci/fixups-se7780.c
new file mode 100644
index 000000000000..880cea1c0d89
--- /dev/null
+++ b/arch/sh/drivers/pci/fixups-se7780.c
@@ -0,0 +1,60 @@
+/*
+ * arch/sh/drivers/pci/fixups-se7780.c
+ *
+ * HITACHI UL Solution Engine 7780  PCI fixups
+ *
+ * Copyright (C) 2003  Lineo uSolutions, Inc.
+ * Copyright (C) 2004 - 2006  Paul Mundt
+ * Copyright (C) 2006  Nobuhiro Iwamatsu
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/pci.h>
+#include "pci-sh4.h"
+#include <asm/io.h>
+
+int pci_fixup_pcic(void)
+{
+        ctrl_outl(0x00000001, SH7780_PCI_VCR2);
+
+        /* Enable all interrupts, so we know what to fix */
+        pci_write_reg(0x0000C3FF, SH7780_PCIIMR);
+        pci_write_reg(0x0000380F, SH7780_PCIAINTM);
+
+        /* Set up standard PCI config registers */
+        ctrl_outw(0xFB00, PCI_REG(SH7780_PCISTATUS));
+        ctrl_outw(0x0047, PCI_REG(SH7780_PCICMD));
+        ctrl_outb(  0x00, PCI_REG(SH7780_PCIPIF));
+        ctrl_outb(  0x00, PCI_REG(SH7780_PCISUB));
+        ctrl_outb(  0x06, PCI_REG(SH7780_PCIBCC));
+        ctrl_outw(0x1912, PCI_REG(SH7780_PCISVID));
+        ctrl_outw(0x0001, PCI_REG(SH7780_PCISID));
+
+        pci_write_reg(0x08000000, SH7780_PCIMBAR0);     /* PCI */
+        pci_write_reg(0x08000000, SH7780_PCILAR0);     /* SHwy */
+        pci_write_reg(0x07F00001, SH7780_PCILSR);      /* size 128M w/ MBAR */
+
+        pci_write_reg(0x00000000, SH7780_PCIMBAR1);
+        pci_write_reg(0x00000000, SH7780_PCILAR1);
+        pci_write_reg(0x00000000, SH7780_PCILSR1);
+
+        pci_write_reg(0xAB000801, SH7780_PCIIBAR);
+
+        /*
+         * Set the MBR so PCI address is one-to-one with window,
+         * meaning all calls go straight through... use ifdef to
+         * catch erroneous assumption.
+         */
+        pci_write_reg(0xFD000000 , SH7780_PCIMBR0);
+        pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0);    /* 16M */
+
+        /* Set IOBR for window containing area specified in pci.h */
+        pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR);
+        pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR);
+
+        pci_write_reg(0xA5000C01, SH7780_PCICR);
+
+        return 0;
+}
diff --git a/arch/sh/drivers/pci/ops-landisk.c b/arch/sh/drivers/pci/ops-landisk.c
index d06030815a96..bff09ecf3419 100644
--- a/arch/sh/drivers/pci/ops-landisk.c
+++ b/arch/sh/drivers/pci/ops-landisk.c
@@ -17,8 +17,8 @@
 
 static struct resource sh7751_io_resource = {
         .name = "SH7751 IO",
-        .start = 0x4000,
-        .end = 0x4000 + SH7751_PCI_IO_SIZE - 1,
+        .start = SH7751_PCI_IO_BASE,
+        .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
         .flags = IORESOURCE_IO
 };
 
diff --git a/arch/sh/drivers/pci/ops-lboxre2.c b/arch/sh/drivers/pci/ops-lboxre2.c
new file mode 100644
index 000000000000..a13cb764b0b9
--- /dev/null
+++ b/arch/sh/drivers/pci/ops-lboxre2.c
@@ -0,0 +1,63 @@
+/*
+ * linux/arch/sh/drivers/pci/ops-lboxre2.c
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu
+ *
+ * PCI initialization for the NTT COMWARE L-BOX RE2
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/io.h>
+#include <asm/lboxre2.h>
+#include "pci-sh4.h"
+
+static char lboxre2_irq_tab[] __initdata = {
+        IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD,
+};
+
+int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
+{
+        return lboxre2_irq_tab[slot];
+}
+
+static struct resource sh7751_io_resource = {
+        .name   = "SH7751_IO",
+        .start  = SH7751_PCI_IO_BASE ,
+        .end    = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
+        .flags  = IORESOURCE_IO
+};
+
+static struct resource sh7751_mem_resource = {
+        .name   = "SH7751_mem",
+        .start  = SH7751_PCI_MEMORY_BASE,
+        .end    = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
+        .flags  = IORESOURCE_MEM
+};
+
+extern struct pci_ops sh7751_pci_ops;
+
+struct pci_channel board_pci_channels[] = {
+        { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
+        { NULL, NULL, NULL, 0, 0 },
+};
+
+EXPORT_SYMBOL(board_pci_channels);
+
+static struct sh4_pci_address_map sh7751_pci_map = {
+        .window0        = {
+                .base   = SH7751_CS3_BASE_ADDR,
+                .size   = 0x04000000,
+        },
+        .window1        = {
+                .base   = 0x00000000,   /* Unused */
+                .size   = 0x00000000,   /* Unused */
+        },
+        .flags  = SH4_PCIC_NO_RESET,
+};
+
+int __init pcibios_init_platform(void)
+{
+        return sh7751_pcic_init(&sh7751_pci_map);
+}
diff --git a/arch/sh/drivers/pci/ops-r7780rp.c b/arch/sh/drivers/pci/ops-r7780rp.c
index eeea1577e112..f2216081ab85 100644
--- a/arch/sh/drivers/pci/ops-r7780rp.c
+++ b/arch/sh/drivers/pci/ops-r7780rp.c
@@ -17,18 +17,25 @@
 #include <asm/io.h>
 #include "pci-sh4.h"
 
+static char r7780rp_irq_tab[] __initdata = {
+        0, 1, 2, 3,
+};
+
+static char r7780mp_irq_tab[] __initdata = {
+        65, 66, 67, 68,
+};
+
 int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
 {
-        switch (slot) {
-        case 0: return IRQ_PCISLOT1;            /* PCI Interrupt #1 */
-        case 1: return IRQ_PCISLOT2;            /* PCI Interrupt #2 */
-        case 2: return IRQ_PCISLOT3;            /* PCI Interrupt #3 */
-        case 3: return IRQ_PCISLOT4;            /* PCI Interrupt E4 */
-        default:
-                printk(KERN_ERR "PCI: Bad IRQ mapping "
-                       "request for slot %d, func %d\n", slot, pin-1);
-                return -1;
-        }
+        if (mach_is_r7780rp())
+                return r7780rp_irq_tab[slot];
+        if (mach_is_r7780mp() || mach_is_r7785rp())
+                return r7780mp_irq_tab[slot];
+
+        printk(KERN_ERR "PCI: Bad IRQ mapping "
+               "request for slot %d, func %d\n", slot, pin-1);
+
+        return -1;
 }
 
 static struct resource sh7780_io_resource = {
diff --git a/arch/sh/drivers/pci/ops-se7780.c b/arch/sh/drivers/pci/ops-se7780.c
new file mode 100644
index 000000000000..212674df5e13
--- /dev/null
+++ b/arch/sh/drivers/pci/ops-se7780.c
@@ -0,0 +1,96 @@
+/*
+ * linux/arch/sh/drivers/pci/ops-se7780.c
+ *
+ * Copyright (C) 2006  Nobuhiro Iwamatsu
+ *
+ * PCI initialization for the Hitachi UL Solution Engine 7780SE03
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <asm/se7780.h>
+#include <asm/io.h>
+#include "pci-sh4.h"
+
+/*
+ * IDSEL = AD16  PCI slot
+ * IDSEL = AD17  PCI slot
+ * IDSEL = AD18  Serial ATA Controller (Silicon Image SiL3512A)
+ * IDSEL = AD19  USB Host Controller (NEC uPD7210100A)
+ */
+
+/* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */
+static char se7780_irq_tab[4][16] __initdata = {
+        /* INTA */
+        { 65, 68, 67, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
+        /* INTB */
+        { 66, 65, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
+        /* INTC */
+        { 67, 66, -1, 66, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
+        /* INTD */
+        { 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
+};
+
+int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
+{
+       return se7780_irq_tab[pin-1][slot];
+}
+
+static struct resource se7780_io_resource = {
+        .name   = "SH7780_IO",
+        .start  = 0x2000,
+        .end    = 0x2000 + SH7780_PCI_IO_SIZE - 1,
+        .flags  = IORESOURCE_IO
+};
+
+static struct resource se7780_mem_resource = {
+        .name   = "SH7780_mem",
+        .start  = SH7780_PCI_MEMORY_BASE,
+        .end    = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
+        .flags  = IORESOURCE_MEM
+};
+
+extern struct pci_ops se7780_pci_ops;
+
+struct pci_channel board_pci_channels[] = {
+        { &sh4_pci_ops, &se7780_io_resource, &se7780_mem_resource, 0, 0xff },
+        { NULL, NULL, NULL, 0, 0 },
+};
+EXPORT_SYMBOL(board_pci_channels);
+
+static struct sh4_pci_address_map se7780_pci_map = {
+        .window0        = {
+                .base   = SH7780_CS2_BASE_ADDR,
+                .size   = 0x04000000,
+        },
+        .flags  = SH4_PCIC_NO_RESET,
+};
+
+int __init pcibios_init_platform(void)
+{
+        printk("SH7780 PCI: Finished initialization of the PCI controller\n");
+
+        /*
+         * FPGA PCISEL register initialize
+         *
+         *  CPU  || SLOT1 | SLOT2 | S-ATA | USB
+         *  -------------------------------------
+         *  INTA || INTA  | INTD  |  --   | INTB
+         *  -------------------------------------
+         *  INTB || INTB  | INTA  |  --   | INTC
+         *  -------------------------------------
+         *  INTC || INTC  | INTB  | INTA  |  --
+         *  -------------------------------------
+         *  INTD || INTD  | INTC  |  --   | INTA
+         *  -------------------------------------
+         */
+        ctrl_outw(0x0013, FPGA_PCI_INTSEL1);
+        ctrl_outw(0xE402, FPGA_PCI_INTSEL2);
+
+        return sh7780_pcic_init(&se7780_pci_map);
+}
diff --git a/arch/sh/drivers/pci/ops-sh4.c b/arch/sh/drivers/pci/ops-sh4.c
index 2d4371009a5e..54232f13e406 100644
--- a/arch/sh/drivers/pci/ops-sh4.c
+++ b/arch/sh/drivers/pci/ops-sh4.c
@@ -162,3 +162,9 @@ char * __init pcibios_setup(char *str)
 
         return str;
 }
+
+int __attribute__((weak)) pci_fixup_pcic(void)
+{
+        /* Nothing to do. */
+        return 0;
+}
diff --git a/arch/sh/drivers/pci/pci-sh4.h b/arch/sh/drivers/pci/pci-sh4.h
index 5a61d6041f2c..1901c33cde6a 100644
--- a/arch/sh/drivers/pci/pci-sh4.h
+++ b/arch/sh/drivers/pci/pci-sh4.h
@@ -1,7 +1,7 @@
 #ifndef __PCI_SH4_H
 #define __PCI_SH4_H
 
-#ifdef CONFIG_CPU_SUBTYPE_SH7780
+#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
 #include "pci-sh7780.h"
 #else
 #include "pci-sh7751.h"
diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c
index 9ddff760d3c6..1aca7fe5783b 100644
--- a/arch/sh/drivers/pci/pci-sh7751.c
+++ b/arch/sh/drivers/pci/pci-sh7751.c
@@ -12,7 +12,6 @@
  *  License.  See linux/COPYING for more information.
  *
  */
-
 #undef DEBUG
 
 #include <linux/init.h>
@@ -28,7 +27,7 @@
  * Initialization. Try all known PCI access methods. Note that we support
  * using both PCI BIOS and direct access: in such cases, we use I/O ports
  * to access config space.
- * 
+ *
  * Note that the platform specific initialization (BSC registers, and memory
  * space mapping) will be called via the platform defined function
  * pcibios_init_platform().
@@ -115,7 +114,7 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
          * Wait Cycle Control + Parity Enable + Bus Master +
          * Mem space enable
          */
-        word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER | 
+        word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
                SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
         pci_write_reg(word, SH7751_PCICONF1);
 
@@ -123,10 +122,10 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
         word = PCI_BASE_CLASS_BRIDGE << 24;
         pci_write_reg(word, SH7751_PCICONF2);
 
-        /* Set IO and Mem windows to local address 
-         * Make PCI and local address the same for easy 1 to 1 mapping 
+        /* Set IO and Mem windows to local address
+         * Make PCI and local address the same for easy 1 to 1 mapping
          * Window0 = map->window0.size @ non-cached area base = SDRAM
-         * Window1 = map->window1.size @ cached area base = SDRAM 
+         * Window1 = map->window1.size @ cached area base = SDRAM
          */
         word = map->window0.size - 1;
         pci_write_reg(word, SH4_PCILSR0);
@@ -175,7 +174,7 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
         case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(5); break;
         case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(6); break;
         }
-        
+
         if (!word)
                 return 0;
 
@@ -194,9 +193,7 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
          * DMA interrupts...
          */
 
-#ifdef CONFIG_SH_RTS7751R2D
         pci_fixup_pcic();
-#endif
 
         /* SH7751 init done, set central function init complete */
         /* use round robin mode to stop a device starving/overruning */
diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c
index 602b644c35ad..5508e45d4838 100644
--- a/arch/sh/drivers/pci/pci-sh7780.c
+++ b/arch/sh/drivers/pci/pci-sh7780.c
@@ -48,7 +48,7 @@
 static int __init sh7780_pci_init(void)
 {
         unsigned int id;
-        int ret;
+        int ret, match = 0;
 
         pr_debug("PCI: Starting intialization.\n");
 
@@ -56,19 +56,43 @@ static int __init sh7780_pci_init(void)
 
         /* check for SH7780/SH7780R hardware */
         id = pci_read_reg(SH7780_PCIVID);
-        if ((id != ((SH7780_DEVICE_ID << 16) | SH7780_VENDOR_ID)) &&
-            (id != ((SH7781_DEVICE_ID << 16) | SH7780_VENDOR_ID))) {
+        if ((id & 0xffff) == SH7780_VENDOR_ID) {
+                switch ((id >> 16) & 0xffff) {
+                case SH7780_DEVICE_ID:
+                case SH7781_DEVICE_ID:
+                case SH7785_DEVICE_ID:
+                        match = 1;
+                        break;
+                }
+        }
+
+        if (unlikely(!match)) {
                 printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id);
                 return -ENODEV;
         }
 
         /* Setup the INTC */
-        ctrl_outl(0x00200000, INTC_ICR0);       /* INTC SH-4 Mode */
-        ctrl_outl(0x00078000, INTC_INT2MSKCR);  /* enable PCIINTA - PCIINTD */
-        ctrl_outl(0x40000000, INTC_INTMSK1);    /* disable IRL4-7 Interrupt */
-        ctrl_outl(0x0000fffe, INTC_INTMSK2);    /* disable IRL4-7 Interrupt */
-        ctrl_outl(0x80000000, INTC_INTMSKCLR1); /* enable IRL0-3 Interrupt */
-        ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); /* enable IRL0-3 Interrupt */
+        if (mach_is_7780se()) {
+                /* ICR0: IRL=use separately */
+                ctrl_outl(0x00C00020, INTC_ICR0);
+                /* ICR1: detect low level(for 2ndcut) */
+                ctrl_outl(0xAAAA0000, INTC_ICR1);
+                /* INTPRI: priority=3(all) */
+                ctrl_outl(0x33333333, INTC_INTPRI);
+        } else {
+                /* INTC SH-4 Mode */
+                ctrl_outl(0x00200000, INTC_ICR0);
+                /* enable PCIINTA - PCIINTD */
+                ctrl_outl(0x00078000, INTC_INT2MSKCR);
+                /* disable IRL4-7 Interrupt */
+                ctrl_outl(0x40000000, INTC_INTMSK1);
+                /* disable IRL4-7 Interrupt */
+                ctrl_outl(0x0000fffe, INTC_INTMSK2);
+                /* enable IRL0-3 Interrupt */
+                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                /* enable IRL0-3 Interrupt */
+                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+        }
 
         if ((ret = sh4_pci_check_direct()) != 0)
                 return ret;
@@ -138,9 +162,8 @@ int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
          * DMA interrupts...
          */
 
-#ifdef CONFIG_SH_R7780RP
+        /* Apply any last-minute PCIC fixups */
         pci_fixup_pcic();
-#endif
 
         /* SH7780 init done, set central function init complete */
         /* use round robin mode to stop a device starving/overruning */
diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h
index f02d2180a4bc..00d12d0f8c1f 100644
--- a/arch/sh/drivers/pci/pci-sh7780.h
+++ b/arch/sh/drivers/pci/pci-sh7780.h
@@ -14,8 +14,9 @@
 
 /* Platform Specific Values */
 #define SH7780_VENDOR_ID        0x1912
-#define SH7780_DEVICE_ID        0x0002
 #define SH7781_DEVICE_ID        0x0001
+#define SH7780_DEVICE_ID        0x0002
+#define SH7785_DEVICE_ID        0x0007
 
 /* SH7780 Control Registers */
 #define SH7780_PCI_VCR0         0xFE000000
@@ -65,6 +66,22 @@
 #define SH7780_PCIPMCSR_BSE     0x046
 #define SH7780_PCICDD           0x047
 
+#define SH7780_PCICR            0x100           /* PCI Control Register */
+#define SH7780_PCILSR           0x104           /* PCI Local Space Register0 */
+#define SH7780_PCILSR1          0x108           /* PCI Local Space Register1 */
+#define SH7780_PCILAR0          0x10C           /* PCI Local Address Register1 */
+#define SH7780_PCILAR1          0x110           /* PCI Local Address Register1 */
+#define SH7780_PCIIR            0x114           /* PCI Interrupt Register */
+#define SH7780_PCIIMR           0x118           /* PCI Interrupt Mask Register */
+#define SH7780_PCIAIR           0x11C           /* Error Address Register */
+#define SH7780_PCICIR           0x120           /* Error Command/Data Register */
+#define SH7780_PCIAINT          0x130           /* Arbiter Interrupt Register */
+#define SH7780_PCIAINTM         0x134           /* Arbiter Int. Mask Register */
+#define SH7780_PCIBMIR          0x138           /* Error Bus Master Register */
+#define SH7780_PCIPAR           0x1C0           /* PIO Address Register */
+#define SH7780_PCIPINT          0x1CC           /* Power Mgmnt Int. Register */
+#define SH7780_PCIPINTM         0x1D0           /* Power Mgmnt Mask Register */
+
 #define SH7780_PCIMBR0          0x1E0
 #define SH7780_PCIMBMR0         0x1E4
 #define SH7780_PCIMBR2          0x1F0