sh: Mass ctrl_in/outX to __raw_read/writeX conversion.

The old ctrl in/out routines are non-portable and unsuitable for
cross-platform use. While drivers/sh has already been sanitized, there
is still quite a lot of code that is not. This converts the arch/sh/ bits
over, which permits us to flag the routines as deprecated whilst still
building with -Werror for the architecture code, and to ensure that
future users are not added.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

8 files changed, 49 insertions, 49 deletions

diff --git a/arch/sh/drivers/dma/dma-pvr2.c b/arch/sh/drivers/dma/dma-pvr2.c
index 391cbe1c2956..3cee58e7f1e5 100644
--- a/arch/sh/drivers/dma/dma-pvr2.c
+++ b/arch/sh/drivers/dma/dma-pvr2.c
@@ -40,10 +40,10 @@ static irqreturn_t pvr2_dma_interrupt(int irq, void *dev_id)
 
 static int pvr2_request_dma(struct dma_channel *chan)
 {
-        if (ctrl_inl(PVR2_DMA_MODE) != 0)
+        if (__raw_readl(PVR2_DMA_MODE) != 0)
                 return -EBUSY;
 
-        ctrl_outl(0, PVR2_DMA_LMMODE0);
+        __raw_writel(0, PVR2_DMA_LMMODE0);
 
         return 0;
 }
@@ -60,9 +60,9 @@ static int pvr2_xfer_dma(struct dma_channel *chan)
 
         xfer_complete = 0;
 
-        ctrl_outl(chan->dar, PVR2_DMA_ADDR);
-        ctrl_outl(chan->count, PVR2_DMA_COUNT);
-        ctrl_outl(chan->mode & DMA_MODE_MASK, PVR2_DMA_MODE);
+        __raw_writel(chan->dar, PVR2_DMA_ADDR);
+        __raw_writel(chan->count, PVR2_DMA_COUNT);
+        __raw_writel(chan->mode & DMA_MODE_MASK, PVR2_DMA_MODE);
 
         return 0;
 }
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c
index 37fb5b8bbc3f..565cc1a4cbba 100644
--- a/arch/sh/drivers/dma/dma-sh.c
+++ b/arch/sh/drivers/dma/dma-sh.c
@@ -54,7 +54,7 @@ static inline unsigned int get_dmte_irq(unsigned int chan)
  */
 static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
 {
-        u32 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
+        u32 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
 
         return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
 }
@@ -70,13 +70,13 @@ static irqreturn_t dma_tei(int irq, void *dev_id)
         struct dma_channel *chan = dev_id;
         u32 chcr;
 
-        chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
+        chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
 
         if (!(chcr & CHCR_TE))
                 return IRQ_NONE;
 
         chcr &= ~(CHCR_IE | CHCR_DE);
-        ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
+        __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
 
         wake_up(&chan->wait_queue);
 
@@ -115,7 +115,7 @@ sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
                 chan->flags &= ~DMA_TEI_CAPABLE;
         }
 
-        ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
+        __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
 
         chan->flags |= DMA_CONFIGURED;
         return 0;
@@ -126,13 +126,13 @@ static void sh_dmac_enable_dma(struct dma_channel *chan)
         int irq;
         u32 chcr;
 
-        chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
+        chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
         chcr |= CHCR_DE;
 
         if (chan->flags & DMA_TEI_CAPABLE)
                 chcr |= CHCR_IE;
 
-        ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
+        __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
 
         if (chan->flags & DMA_TEI_CAPABLE) {
                 irq = get_dmte_irq(chan->chan);
@@ -150,9 +150,9 @@ static void sh_dmac_disable_dma(struct dma_channel *chan)
                 disable_irq(irq);
         }
 
-        chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
+        chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
         chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
-        ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
+        __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
 }
 
 static int sh_dmac_xfer_dma(struct dma_channel *chan)
@@ -183,12 +183,12 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
          */
         if (chan->sar || (mach_is_dreamcast() &&
                           chan->chan == PVR2_CASCADE_CHAN))
-                ctrl_outl(chan->sar, (dma_base_addr[chan->chan]+SAR));
+                __raw_writel(chan->sar, (dma_base_addr[chan->chan]+SAR));
         if (chan->dar || (mach_is_dreamcast() &&
                           chan->chan == PVR2_CASCADE_CHAN))
-                ctrl_outl(chan->dar, (dma_base_addr[chan->chan] + DAR));
+                __raw_writel(chan->dar, (dma_base_addr[chan->chan] + DAR));
 
-        ctrl_outl(chan->count >> calc_xmit_shift(chan),
+        __raw_writel(chan->count >> calc_xmit_shift(chan),
                 (dma_base_addr[chan->chan] + TCR));
 
         sh_dmac_enable_dma(chan);
@@ -198,10 +198,10 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
 
 static int sh_dmac_get_dma_residue(struct dma_channel *chan)
 {
-        if (!(ctrl_inl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE))
+        if (!(__raw_readl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE))
                 return 0;
 
-        return ctrl_inl(dma_base_addr[chan->chan] + TCR)
+        return __raw_readl(dma_base_addr[chan->chan] + TCR)
                  << calc_xmit_shift(chan);
 }
 
diff --git a/arch/sh/drivers/dma/dmabrg.c b/arch/sh/drivers/dma/dmabrg.c
index 5e22689c2fcf..72622e307613 100644
--- a/arch/sh/drivers/dma/dmabrg.c
+++ b/arch/sh/drivers/dma/dmabrg.c
@@ -86,8 +86,8 @@ static irqreturn_t dmabrg_irq(int irq, void *data)
         unsigned long dcr;
         unsigned int i;
 
-        dcr = ctrl_inl(DMABRGCR);
-        ctrl_outl(dcr & ~0x00ff0003, DMABRGCR); /* ack all */
+        dcr = __raw_readl(DMABRGCR);
+        __raw_writel(dcr & ~0x00ff0003, DMABRGCR);      /* ack all */
         dcr &= dcr >> 8;        /* ignore masked */
 
         /* USB stuff, get it out of the way first */
@@ -109,17 +109,17 @@ static irqreturn_t dmabrg_irq(int irq, void *data)
 static void dmabrg_disable_irq(unsigned int dmairq)
 {
         unsigned long dcr;
-        dcr = ctrl_inl(DMABRGCR);
+        dcr = __raw_readl(DMABRGCR);
         dcr &= ~(1 << ((dmairq > 1) ? dmairq + 22 : dmairq + 8));
-        ctrl_outl(dcr, DMABRGCR);
+        __raw_writel(dcr, DMABRGCR);
 }
 
 static void dmabrg_enable_irq(unsigned int dmairq)
 {
         unsigned long dcr;
-        dcr = ctrl_inl(DMABRGCR);
+        dcr = __raw_readl(DMABRGCR);
         dcr |= (1 << ((dmairq > 1) ? dmairq + 22 : dmairq + 8));
-        ctrl_outl(dcr, DMABRGCR);
+        __raw_writel(dcr, DMABRGCR);
 }
 
 int dmabrg_request_irq(unsigned int dmairq, void(*handler)(void*),
@@ -165,13 +165,13 @@ static int __init dmabrg_init(void)
                 printk(KERN_INFO "DMABRG: DMAC ch0 not reserved!\n");
 #endif
 
-        ctrl_outl(0, DMABRGCR);
-        ctrl_outl(0, DMACHCR0);
-        ctrl_outl(0x94000000, DMARSRA); /* enable DMABRG in DMAC 0 */
+        __raw_writel(0, DMABRGCR);
+        __raw_writel(0, DMACHCR0);
+        __raw_writel(0x94000000, DMARSRA);      /* enable DMABRG in DMAC 0 */
 
         /* enable DMABRG mode, enable the DMAC */
-        or = ctrl_inl(DMAOR);
-        ctrl_outl(or | DMAOR_BRG | DMAOR_DMEN, DMAOR);
+        or = __raw_readl(DMAOR);
+        __raw_writel(or | DMAOR_BRG | DMAOR_DMEN, DMAOR);
 
         ret = request_irq(DMABRGI0, dmabrg_irq, IRQF_DISABLED,
                         "DMABRG USB address error", NULL);
diff --git a/arch/sh/drivers/pci/fixups-rts7751r2d.c b/arch/sh/drivers/pci/fixups-rts7751r2d.c
index 7898f14d6641..e248516118a9 100644
--- a/arch/sh/drivers/pci/fixups-rts7751r2d.c
+++ b/arch/sh/drivers/pci/fixups-rts7751r2d.c
@@ -43,7 +43,7 @@ int pci_fixup_pcic(struct pci_channel *chan)
 {
         unsigned long bcr1, mcr;
 
-        bcr1 = ctrl_inl(SH7751_BCR1);
+        bcr1 = __raw_readl(SH7751_BCR1);
         bcr1 |= 0x40080000;     /* Enable Bit 19 BREQEN, set PCIC to slave */
         pci_write_reg(chan, bcr1, SH4_PCIBCR1);
 
@@ -54,7 +54,7 @@ int pci_fixup_pcic(struct pci_channel *chan)
         pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
         pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
 
-        mcr = ctrl_inl(SH7751_MCR);
+        mcr = __raw_readl(SH7751_MCR);
         mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
         pci_write_reg(chan, mcr, SH4_PCIMCR);
 
diff --git a/arch/sh/drivers/pci/pci-sh4.h b/arch/sh/drivers/pci/pci-sh4.h
index 3d5296cde622..4744a7dede0c 100644
--- a/arch/sh/drivers/pci/pci-sh4.h
+++ b/arch/sh/drivers/pci/pci-sh4.h
@@ -167,13 +167,13 @@ struct sh4_pci_address_map {
 static inline void pci_write_reg(struct pci_channel *chan,
                                  unsigned long val, unsigned long reg)
 {
-        ctrl_outl(val, chan->reg_base + reg);
+        __raw_writel(val, chan->reg_base + reg);
 }
 
 static inline unsigned long pci_read_reg(struct pci_channel *chan,
                                          unsigned long reg)
 {
-        return ctrl_inl(chan->reg_base + reg);
+        return __raw_readl(chan->reg_base + reg);
 }
 
 #endif /* __PCI_SH4_H */
diff --git a/arch/sh/drivers/pci/pci-sh5.h b/arch/sh/drivers/pci/pci-sh5.h
index f277628221f3..3f01decb4307 100644
--- a/arch/sh/drivers/pci/pci-sh5.h
+++ b/arch/sh/drivers/pci/pci-sh5.h
@@ -86,14 +86,14 @@ extern unsigned long pcicr_virt;
 /* #define PCISH5_VCR_REG(x)                ( SH5PCI_VCR_BASE (PCISH5_VCR_##x)) */
 
 /* Write I/O functions */
-#define SH5PCI_WRITE(reg,val)        ctrl_outl((u32)(val),PCISH5_ICR_REG(reg))
-#define SH5PCI_WRITE_SHORT(reg,val)  ctrl_outw((u16)(val),PCISH5_ICR_REG(reg))
-#define SH5PCI_WRITE_BYTE(reg,val)   ctrl_outb((u8)(val),PCISH5_ICR_REG(reg))
+#define SH5PCI_WRITE(reg,val)        __raw_writel((u32)(val),PCISH5_ICR_REG(reg))
+#define SH5PCI_WRITE_SHORT(reg,val)  __raw_writew((u16)(val),PCISH5_ICR_REG(reg))
+#define SH5PCI_WRITE_BYTE(reg,val)   __raw_writeb((u8)(val),PCISH5_ICR_REG(reg))
 
 /* Read I/O functions */
-#define SH5PCI_READ(reg)             ctrl_inl(PCISH5_ICR_REG(reg))
-#define SH5PCI_READ_SHORT(reg)       ctrl_inw(PCISH5_ICR_REG(reg))
-#define SH5PCI_READ_BYTE(reg)        ctrl_inb(PCISH5_ICR_REG(reg))
+#define SH5PCI_READ(reg)             __raw_readl(PCISH5_ICR_REG(reg))
+#define SH5PCI_READ_SHORT(reg)       __raw_readw(PCISH5_ICR_REG(reg))
+#define SH5PCI_READ_BYTE(reg)        __raw_readb(PCISH5_ICR_REG(reg))
 
 /* Set PCI config bits */
 #define SET_CONFIG_BITS(bus,devfn,where)  ((((bus) << 16) | ((devfn) << 8) | ((where) & ~3)) | 0x80000000)
diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c
index 70c1999a0ec4..2455cf32db5a 100644
--- a/arch/sh/drivers/pci/pci-sh7751.c
+++ b/arch/sh/drivers/pci/pci-sh7751.c
@@ -97,9 +97,9 @@ static int __init sh7751_pci_init(void)
                 return ret;
 
         /* Set the BCR's to enable PCI access */
-        reg = ctrl_inl(SH7751_BCR1);
+        reg = __raw_readl(SH7751_BCR1);
         reg |= 0x80000;
-        ctrl_outl(reg, SH7751_BCR1);
+        __raw_writel(reg, SH7751_BCR1);
 
         /* Turn the clocks back on (not done in reset)*/
         pci_write_reg(chan, 0, SH4_PCICLKR);
@@ -159,13 +159,13 @@ static int __init sh7751_pci_init(void)
                 return -1;
 
         /* configure the wait control registers */
-        word = ctrl_inl(SH7751_WCR1);
+        word = __raw_readl(SH7751_WCR1);
         pci_write_reg(chan, word, SH4_PCIWCR1);
-        word = ctrl_inl(SH7751_WCR2);
+        word = __raw_readl(SH7751_WCR2);
         pci_write_reg(chan, word, SH4_PCIWCR2);
-        word = ctrl_inl(SH7751_WCR3);
+        word = __raw_readl(SH7751_WCR3);
         pci_write_reg(chan, word, SH4_PCIWCR3);
-        word = ctrl_inl(SH7751_MCR);
+        word = __raw_readl(SH7751_MCR);
         pci_write_reg(chan, word, SH4_PCIMCR);
 
         /* NOTE: I'm ignoring the PCI error IRQs for now..
diff --git a/arch/sh/drivers/superhyway/ops-sh4-202.c b/arch/sh/drivers/superhyway/ops-sh4-202.c
index 3b14bf860db6..6da62e9475c4 100644
--- a/arch/sh/drivers/superhyway/ops-sh4-202.c
+++ b/arch/sh/drivers/superhyway/ops-sh4-202.c
@@ -134,8 +134,8 @@ static int sh4202_read_vcr(unsigned long base, struct superhyway_vcr_info *vcr)
          *
          * Do not trust the documentation, for it is evil.
          */
-        vcrh = ctrl_inl(base);
-        vcrl = ctrl_inl(base + sizeof(u32));
+        vcrh = __raw_readl(base);
+        vcrl = __raw_readl(base + sizeof(u32));
 
         tmp = ((u64)vcrh << 32) | vcrl;
         memcpy(vcr, &tmp, sizeof(u64));
@@ -147,8 +147,8 @@ static int sh4202_write_vcr(unsigned long base, struct superhyway_vcr_info vcr)
 {
         u64 tmp = *(u64 *)&vcr;
 
-        ctrl_outl((tmp >> 32) & 0xffffffff, base);
-        ctrl_outl(tmp & 0xffffffff, base + sizeof(u32));
+        __raw_writel((tmp >> 32) & 0xffffffff, base);
+        __raw_writel(tmp & 0xffffffff, base + sizeof(u32));
 
         return 0;
 }