sh: Mass ctrl_in/outX to __raw_read/writeX conversion.

The old ctrl in/out routines are non-portable and unsuitable for
cross-platform use. While drivers/sh has already been sanitized, there
is still quite a lot of code that is not. This converts the arch/sh/ bits
over, which permits us to flag the routines as deprecated whilst still
building with -Werror for the architecture code, and to ensure that
future users are not added.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

4 files changed, 16 insertions, 16 deletions

diff --git a/arch/sh/drivers/pci/fixups-rts7751r2d.c b/arch/sh/drivers/pci/fixups-rts7751r2d.c
index 7898f14d6641..e248516118a9 100644
--- a/arch/sh/drivers/pci/fixups-rts7751r2d.c
+++ b/arch/sh/drivers/pci/fixups-rts7751r2d.c
@@ -43,7 +43,7 @@ int pci_fixup_pcic(struct pci_channel *chan)
 {
         unsigned long bcr1, mcr;
 
-        bcr1 = ctrl_inl(SH7751_BCR1);
+        bcr1 = __raw_readl(SH7751_BCR1);
         bcr1 |= 0x40080000;     /* Enable Bit 19 BREQEN, set PCIC to slave */
         pci_write_reg(chan, bcr1, SH4_PCIBCR1);
 
@@ -54,7 +54,7 @@ int pci_fixup_pcic(struct pci_channel *chan)
         pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
         pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
 
-        mcr = ctrl_inl(SH7751_MCR);
+        mcr = __raw_readl(SH7751_MCR);
         mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
         pci_write_reg(chan, mcr, SH4_PCIMCR);
 
diff --git a/arch/sh/drivers/pci/pci-sh4.h b/arch/sh/drivers/pci/pci-sh4.h
index 3d5296cde622..4744a7dede0c 100644
--- a/arch/sh/drivers/pci/pci-sh4.h
+++ b/arch/sh/drivers/pci/pci-sh4.h
@@ -167,13 +167,13 @@ struct sh4_pci_address_map {
 static inline void pci_write_reg(struct pci_channel *chan,
                                  unsigned long val, unsigned long reg)
 {
-        ctrl_outl(val, chan->reg_base + reg);
+        __raw_writel(val, chan->reg_base + reg);
 }
 
 static inline unsigned long pci_read_reg(struct pci_channel *chan,
                                          unsigned long reg)
 {
-        return ctrl_inl(chan->reg_base + reg);
+        return __raw_readl(chan->reg_base + reg);
 }
 
 #endif /* __PCI_SH4_H */
diff --git a/arch/sh/drivers/pci/pci-sh5.h b/arch/sh/drivers/pci/pci-sh5.h
index f277628221f3..3f01decb4307 100644
--- a/arch/sh/drivers/pci/pci-sh5.h
+++ b/arch/sh/drivers/pci/pci-sh5.h
@@ -86,14 +86,14 @@ extern unsigned long pcicr_virt;
 /* #define PCISH5_VCR_REG(x)                ( SH5PCI_VCR_BASE (PCISH5_VCR_##x)) */
 
 /* Write I/O functions */
-#define SH5PCI_WRITE(reg,val)        ctrl_outl((u32)(val),PCISH5_ICR_REG(reg))
-#define SH5PCI_WRITE_SHORT(reg,val)  ctrl_outw((u16)(val),PCISH5_ICR_REG(reg))
-#define SH5PCI_WRITE_BYTE(reg,val)   ctrl_outb((u8)(val),PCISH5_ICR_REG(reg))
+#define SH5PCI_WRITE(reg,val)        __raw_writel((u32)(val),PCISH5_ICR_REG(reg))
+#define SH5PCI_WRITE_SHORT(reg,val)  __raw_writew((u16)(val),PCISH5_ICR_REG(reg))
+#define SH5PCI_WRITE_BYTE(reg,val)   __raw_writeb((u8)(val),PCISH5_ICR_REG(reg))
 
 /* Read I/O functions */
-#define SH5PCI_READ(reg)             ctrl_inl(PCISH5_ICR_REG(reg))
-#define SH5PCI_READ_SHORT(reg)       ctrl_inw(PCISH5_ICR_REG(reg))
-#define SH5PCI_READ_BYTE(reg)        ctrl_inb(PCISH5_ICR_REG(reg))
+#define SH5PCI_READ(reg)             __raw_readl(PCISH5_ICR_REG(reg))
+#define SH5PCI_READ_SHORT(reg)       __raw_readw(PCISH5_ICR_REG(reg))
+#define SH5PCI_READ_BYTE(reg)        __raw_readb(PCISH5_ICR_REG(reg))
 
 /* Set PCI config bits */
 #define SET_CONFIG_BITS(bus,devfn,where)  ((((bus) << 16) | ((devfn) << 8) | ((where) & ~3)) | 0x80000000)
diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c
index 70c1999a0ec4..2455cf32db5a 100644
--- a/arch/sh/drivers/pci/pci-sh7751.c
+++ b/arch/sh/drivers/pci/pci-sh7751.c
@@ -97,9 +97,9 @@ static int __init sh7751_pci_init(void)
                 return ret;
 
         /* Set the BCR's to enable PCI access */
-        reg = ctrl_inl(SH7751_BCR1);
+        reg = __raw_readl(SH7751_BCR1);
         reg |= 0x80000;
-        ctrl_outl(reg, SH7751_BCR1);
+        __raw_writel(reg, SH7751_BCR1);
 
         /* Turn the clocks back on (not done in reset)*/
         pci_write_reg(chan, 0, SH4_PCICLKR);
@@ -159,13 +159,13 @@ static int __init sh7751_pci_init(void)
                 return -1;
 
         /* configure the wait control registers */
-        word = ctrl_inl(SH7751_WCR1);
+        word = __raw_readl(SH7751_WCR1);
         pci_write_reg(chan, word, SH4_PCIWCR1);
-        word = ctrl_inl(SH7751_WCR2);
+        word = __raw_readl(SH7751_WCR2);
         pci_write_reg(chan, word, SH4_PCIWCR2);
-        word = ctrl_inl(SH7751_WCR3);
+        word = __raw_readl(SH7751_WCR3);
         pci_write_reg(chan, word, SH4_PCIWCR3);
-        word = ctrl_inl(SH7751_MCR);
+        word = __raw_readl(SH7751_MCR);
         pci_write_reg(chan, word, SH4_PCIMCR);
 
         /* NOTE: I'm ignoring the PCI error IRQs for now..