Merge branch 'sh/pci-express-integration'

2 files changed, 36 insertions, 21 deletions

diff --git a/arch/sh/drivers/pci/ops-sh7786.c b/arch/sh/drivers/pci/ops-sh7786.c
index 48f594b9582b..79a5ddae733d 100644
--- a/arch/sh/drivers/pci/ops-sh7786.c
+++ b/arch/sh/drivers/pci/ops-sh7786.c
@@ -1,7 +1,7 @@
 /*
  * Generic SH7786 PCI-Express operations.
  *
- *  Copyright (C) 2009  Paul Mundt
+ *  Copyright (C) 2009 - 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License v2. See the file "COPYING" in the main directory of this archive
@@ -25,32 +25,39 @@ static int sh7786_pcie_config_access(unsigned char access_type,
                 struct pci_bus *bus, unsigned int devfn, int where, u32 *data)
 {
         struct pci_channel *chan = bus->sysdata;
-        int dev, func;
+        int dev, func, type;
 
         dev = PCI_SLOT(devfn);
         func = PCI_FUNC(devfn);
+        type = !!bus->parent;
 
         if (bus->number > 255 || dev > 31 || func > 7)
                 return PCIBIOS_FUNC_NOT_SUPPORTED;
-        if (devfn)
+        if (bus->parent == NULL && dev)
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
+        /* Clear errors */
+        pci_write_reg(chan, pci_read_reg(chan, SH4A_PCIEERRFR), SH4A_PCIEERRFR);
+
         /* Set the PIO address */
         pci_write_reg(chan, (bus->number << 24) | (dev << 19) |
                                 (func << 16) | (where & ~3), SH4A_PCIEPAR);
 
         /* Enable the configuration access */
-        pci_write_reg(chan, (1 << 31), SH4A_PCIEPCTLR);
+        pci_write_reg(chan, (1 << 31) | (type << 8), SH4A_PCIEPCTLR);
+
+        /* Check for errors */
+        if (pci_read_reg(chan, SH4A_PCIEERRFR) & 0x10)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        /* Check for master and target aborts */
+        if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28)))
+                return PCIBIOS_DEVICE_NOT_FOUND;
 
         if (access_type == PCI_ACCESS_READ)
                 *data = pci_read_reg(chan, SH4A_PCIEPDR);
         else
                 pci_write_reg(chan, *data, SH4A_PCIEPDR);
 
-        /* Check for master and target aborts */
-        if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28)))
-                return PCIBIOS_DEVICE_NOT_FOUND;
-
         return PCIBIOS_SUCCESSFUL;
 }
 
@@ -69,8 +76,10 @@ static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn,
         spin_lock_irqsave(&sh7786_pcie_lock, flags);
         ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
                                         devfn, where, &data);
-        if (ret != PCIBIOS_SUCCESSFUL)
+        if (ret != PCIBIOS_SUCCESSFUL) {
+                *val = 0xffffffff;
                 goto out;
+        }
 
         if (size == 1)
                 *val = (data >> ((where & 3) << 3)) & 0xff;
diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index 78f378731858..d053ffca8196 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -148,16 +148,11 @@ static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
 static void phy_write_reg(struct pci_channel *chan, unsigned int addr,
                           unsigned int lane, unsigned int data)
 {
-        unsigned long phyaddr, ctrl;
+        unsigned long phyaddr;
 
         phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) +
                         ((addr & 0xff) << BITS_ADR);
 
-        /* Enable clock */
-        ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
-        ctrl |= (1 << BITS_CKE);
-        pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
-
         /* Set write data */
         pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
         pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);
@@ -165,20 +160,22 @@ static void phy_write_reg(struct pci_channel *chan, unsigned int addr,
         phy_wait_for_ack(chan);
 
         /* Clear command */
+        pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);
         pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);
 
         phy_wait_for_ack(chan);
-
-        /* Disable clock */
-        ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
-        ctrl &= ~(1 << BITS_CKE);
-        pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
 }
 
 static int phy_init(struct pci_channel *chan)
 {
+        unsigned long ctrl;
         unsigned int timeout = 100;
 
+        /* Enable clock */
+        ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
+        ctrl |= (1 << BITS_CKE);
+        pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
+
         /* Initialize the phy */
         phy_write_reg(chan, 0x60, 0xf, 0x004b008b);
         phy_write_reg(chan, 0x61, 0xf, 0x00007b41);
@@ -187,9 +184,15 @@ static int phy_init(struct pci_channel *chan)
         phy_write_reg(chan, 0x66, 0xf, 0x00000010);
         phy_write_reg(chan, 0x74, 0xf, 0x0007001c);
         phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);
+        phy_write_reg(chan, 0xb0, 0xf, 0x00000610);
 
         /* Deassert Standby */
-        phy_write_reg(chan, 0x67, 0xf, 0x00000400);
+        phy_write_reg(chan, 0x67, 0x1, 0x00000400);
+
+        /* Disable clock */
+        ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
+        ctrl &= ~(1 << BITS_CKE);
+        pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
 
         while (timeout--) {
                 if (pci_read_reg(chan, SH4A_PCIEPHYSR))
@@ -287,6 +290,9 @@ static int pcie_init(struct sh7786_pcie_port *port)
         __raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);
         __raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0);
 
+        __raw_writel(memphys, chan->reg_base + SH4A_PCIEPCICONF4);
+        __raw_writel(0, chan->reg_base + SH4A_PCIEPCICONF5);
+
         /* Finish initialization */
         data = pci_read_reg(chan, SH4A_PCIETCTLR);
         data |= 0x1;