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authorLinus Torvalds <torvalds@linux-foundation.org>2009-06-11 13:08:33 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-11 13:08:33 -0400
commitd3d07d941fd80c173b6d690ded00ee5fb8302e06 (patch)
treef1a82c956e393df9933c8544bb564ef1735384ee /arch/sh/drivers/pci/pci-sh7780.h
parent6cd8e300b49332eb9eeda45816c711c198d31505 (diff)
parent54ff328b46e58568c4b3350c2fa3223ef862e5a4 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (266 commits) sh: Tie sparseirq in to Kconfig. sh: Wire up sys_rt_tgsigqueueinfo. sh: Fix sys_pwritev() syscall table entry for sh32. sh: Fix sh4a llsc-based cmpxchg() sh: sh7724: Add JPU support sh: sh7724: INTC setting update sh: sh7722 clock framework rewrite sh: sh7366 clock framework rewrite sh: sh7343 clock framework rewrite sh: sh7724 clock framework rewrite V3 sh: sh7723 clock framework rewrite V2 sh: add enable()/disable()/set_rate() to div6 code sh: add AP325RXA mode pin configuration sh: add Migo-R mode pin configuration sh: sh7722 mode pin definitions sh: sh7724 mode pin comments sh: sh7723 mode pin V2 sh: rework mode pin code sh: clock div6 helper code sh: clock div4 frequency table offset fix ...
Diffstat (limited to 'arch/sh/drivers/pci/pci-sh7780.h')
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.h16
1 files changed, 2 insertions, 14 deletions
diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h
index 93adc7119b79..4a52478c97cf 100644
--- a/arch/sh/drivers/pci/pci-sh7780.h
+++ b/arch/sh/drivers/pci/pci-sh7780.h
@@ -20,9 +20,8 @@
20#define SH7785_DEVICE_ID 0x0007 20#define SH7785_DEVICE_ID 0x0007
21 21
22/* SH7780 Control Registers */ 22/* SH7780 Control Registers */
23#define SH7780_PCI_VCR0 0xFE000000 23#define PCIECR 0xFE000008
24#define SH7780_PCI_VCR1 0xFE000004 24#define PCIECR_ENBL 0x01
25#define SH7780_PCI_VCR2 0xFE000008
26 25
27/* SH7780 Specific Values */ 26/* SH7780 Specific Values */
28#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */ 27#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
@@ -35,7 +34,6 @@
35#define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */ 34#define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */
36 35
37#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */ 36#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
38#define PCI_REG(n) (SH7780_PCIREG_BASE+n)
39 37
40/* SH7780 PCI Config Registers */ 38/* SH7780 PCI Config Registers */
41#define SH7780_PCIVID 0x000 /* Vendor ID */ 39#define SH7780_PCIVID 0x000 /* Vendor ID */
@@ -67,11 +65,6 @@
67#define SH7780_PCIPMCSR_BSE 0x046 65#define SH7780_PCIPMCSR_BSE 0x046
68#define SH7780_PCICDD 0x047 66#define SH7780_PCICDD 0x047
69 67
70#define SH7780_PCICR 0x100 /* PCI Control Register */
71#define SH7780_PCILSR 0x104 /* PCI Local Space Register0 */
72#define SH7780_PCILSR1 0x108 /* PCI Local Space Register1 */
73#define SH7780_PCILAR0 0x10C /* PCI Local Address Register1 */
74#define SH7780_PCILAR1 0x110 /* PCI Local Address Register1 */
75#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */ 68#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
76#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */ 69#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
77#define SH7780_PCIAIR 0x11C /* Error Address Register */ 70#define SH7780_PCIAIR 0x11C /* Error Address Register */
@@ -106,9 +99,4 @@
106 99
107#define SH7780_32BIT_DDR_BASE_ADDR 0x40000000 100#define SH7780_32BIT_DDR_BASE_ADDR 0x40000000
108 101
109struct sh4_pci_address_map;
110
111/* arch/sh/drivers/pci/pci-sh7780.c */
112int sh7780_pcic_init(struct sh4_pci_address_map *map);
113
114#endif /* _PCI_SH7780_H_ */ 102#endif /* _PCI_SH7780_H_ */