diff options
author | Paul Mundt <lethal@linux-sh.org> | 2006-09-27 03:43:28 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2006-09-27 03:43:28 -0400 |
commit | 959f85f8a3223c116bbe95dd8a9b207790b5d4d3 (patch) | |
tree | e7da9ccf292f860bfa0ff9cc8b2682cd1d6bad4d /arch/sh/drivers/pci/pci-sh7780.h | |
parent | e108b2ca2349f510ce7d7f910eda89f71d710d84 (diff) |
sh: Consolidated SH7751/SH7780 PCI support.
This cleans up quite a lot of the PCI mess that we
currently have, and attempts to consolidate the
duplication in the SH7780 and SH7751 PCI controllers.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers/pci/pci-sh7780.h')
-rw-r--r-- | arch/sh/drivers/pci/pci-sh7780.h | 94 |
1 files changed, 10 insertions, 84 deletions
diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h index 750d5d7753a2..f02d2180a4bc 100644 --- a/arch/sh/drivers/pci/pci-sh7780.h +++ b/arch/sh/drivers/pci/pci-sh7780.h | |||
@@ -12,28 +12,6 @@ | |||
12 | #ifndef _PCI_SH7780_H_ | 12 | #ifndef _PCI_SH7780_H_ |
13 | #define _PCI_SH7780_H_ | 13 | #define _PCI_SH7780_H_ |
14 | 14 | ||
15 | #include <linux/pci.h> | ||
16 | |||
17 | /* set debug level 4=verbose...1=terse */ | ||
18 | //#define DEBUG_PCI 3 | ||
19 | #undef DEBUG_PCI | ||
20 | |||
21 | #ifdef DEBUG_PCI | ||
22 | #define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); } | ||
23 | #else | ||
24 | #define PCIDBG(n, x...) | ||
25 | #endif | ||
26 | |||
27 | /* startup values */ | ||
28 | #define PCI_PROBE_BIOS 1 | ||
29 | #define PCI_PROBE_CONF1 2 | ||
30 | #define PCI_PROBE_CONF2 4 | ||
31 | #define PCI_NO_SORT 0x100 | ||
32 | #define PCI_BIOS_SORT 0x200 | ||
33 | #define PCI_NO_CHECKS 0x400 | ||
34 | #define PCI_ASSIGN_ROMS 0x1000 | ||
35 | #define PCI_BIOS_IRQ_SCAN 0x2000 | ||
36 | |||
37 | /* Platform Specific Values */ | 15 | /* Platform Specific Values */ |
38 | #define SH7780_VENDOR_ID 0x1912 | 16 | #define SH7780_VENDOR_ID 0x1912 |
39 | #define SH7780_DEVICE_ID 0x0002 | 17 | #define SH7780_DEVICE_ID 0x0002 |
@@ -47,15 +25,12 @@ | |||
47 | /* SH7780 Specific Values */ | 25 | /* SH7780 Specific Values */ |
48 | #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */ | 26 | #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */ |
49 | #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */ | 27 | #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */ |
28 | |||
50 | #define SH7780_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */ | 29 | #define SH7780_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */ |
51 | #define SH7780_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ | 30 | #define SH7780_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ |
52 | #if 1 | 31 | |
53 | #define SH7780_PCI_IO_BASE 0xFE400000 /* IO space base address */ | 32 | #define SH7780_PCI_IO_BASE 0xFE400000 /* IO space base address */ |
54 | #define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */ | 33 | #define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */ |
55 | #else | ||
56 | #define SH7780_PCI_IO_BASE 0xFE200000 /* IO space base address */ | ||
57 | #define SH7780_PCI_IO_SIZE 0x00200000 /* Size of IO window */ | ||
58 | #endif | ||
59 | 34 | ||
60 | #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */ | 35 | #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */ |
61 | #define PCI_REG(n) (SH7780_PCIREG_BASE+n) | 36 | #define PCI_REG(n) (SH7780_PCIREG_BASE+n) |
@@ -90,44 +65,16 @@ | |||
90 | #define SH7780_PCIPMCSR_BSE 0x046 | 65 | #define SH7780_PCIPMCSR_BSE 0x046 |
91 | #define SH7780_PCICDD 0x047 | 66 | #define SH7780_PCICDD 0x047 |
92 | 67 | ||
93 | /* SH7780 PCI Local Registers */ | 68 | #define SH7780_PCIMBR0 0x1E0 |
94 | #define SH7780_PCICR 0x100 /* PCI Control Register */ | 69 | #define SH7780_PCIMBMR0 0x1E4 |
95 | #define SH7780_PCICR_PREFIX 0xA5000000 /* CR prefix for write */ | 70 | #define SH7780_PCIMBR2 0x1F0 |
96 | #define SH7780_PCICR_PFCS 0x00000800 /* TRDY/IRDY Enable */ | 71 | #define SH7780_PCIMBMR2 0x1F4 |
97 | #define SH7780_PCICR_FTO 0x00000400 /* TRDY/IRDY Enable */ | 72 | #define SH7780_PCIIOBR 0x1F8 |
98 | #define SH7780_PCICR_PFE 0x00000200 /* Target Read Single */ | 73 | #define SH7780_PCIIOBMR 0x1FC |
99 | #define SH7780_PCICR_TBS 0x00000100 /* Target Byte Swap */ | ||
100 | #define SH7780_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */ | ||
101 | #define SH7780_PCICR_IOCS 0x00000004 /* INTA output assert */ | ||
102 | #define SH7780_PCICR_PRST 0x00000002 /* PCI Reset Assert */ | ||
103 | #define SH7780_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */ | ||
104 | #define SH7780_PCILSR0 0x104 /* PCI Local Space Register0 */ | ||
105 | #define SH7780_PCILSR1 0x108 /* PCI Local Space Register1 */ | ||
106 | #define SH7780_PCILAR0 0x10C /* PCI Local Address Register1 */ | ||
107 | #define SH7780_PCILAR1 0x110 /* PCI Local Address Register1 */ | ||
108 | #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */ | ||
109 | #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */ | ||
110 | #define SH7780_PCIAIR 0x11C /* Error Address Register */ | ||
111 | #define SH7780_PCICIR 0x120 /* Error Command/Data Register */ | ||
112 | #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */ | ||
113 | #define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */ | ||
114 | #define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */ | ||
115 | #define SH7780_PCIPAR 0x1C0 /* PIO Address Register */ | ||
116 | #define SH7780_PCIPINT 0x1CC /* Power Management Int. Register */ | ||
117 | #define SH7780_PCIPINTM 0x1D0 /* Power Management Mask Register */ | ||
118 | #define SH7780_PCIMBR0 0x1E0 /* Memory Bank0 Register */ | ||
119 | #define SH7780_PCIMBMR0 0x1E4 /* Memory Bank0 Mask Register */ | ||
120 | #define SH7780_PCIMBR1 0x1E8 /* Memory Bank1 Register */ | ||
121 | #define SH7780_PCIMBMR1 0x1EC /* Memory Bank1 Mask Register */ | ||
122 | #define SH7780_PCIMBR2 0x1F0 /* Memory Bank2 Register */ | ||
123 | #define SH7780_PCIMBMR2 0x1F4 /* Memory Bank2 Mask Register */ | ||
124 | #define SH7780_PCIIOBR 0x1F8 /* Bank Register */ | ||
125 | #define SH7780_PCIIOBMR 0x1FC /* Bank Mask Register */ | ||
126 | #define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */ | 74 | #define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */ |
127 | #define SH7780_PCICSCR1 0x214 /* Cache Snoop2 Cnt. Register */ | 75 | #define SH7780_PCICSCR1 0x214 /* Cache Snoop2 Cnt. Register */ |
128 | #define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */ | 76 | #define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */ |
129 | #define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */ | 77 | #define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */ |
130 | #define SH7780_PCIPDR 0x220 /* Port IO Data Register */ | ||
131 | 78 | ||
132 | /* General Memory Config Addresses */ | 79 | /* General Memory Config Addresses */ |
133 | #define SH7780_CS0_BASE_ADDR 0x0 | 80 | #define SH7780_CS0_BASE_ADDR 0x0 |
@@ -139,30 +86,9 @@ | |||
139 | #define SH7780_CS5_BASE_ADDR (SH7780_CS4_BASE_ADDR + SH7780_MEM_REGION_SIZE) | 86 | #define SH7780_CS5_BASE_ADDR (SH7780_CS4_BASE_ADDR + SH7780_MEM_REGION_SIZE) |
140 | #define SH7780_CS6_BASE_ADDR (SH7780_CS5_BASE_ADDR + SH7780_MEM_REGION_SIZE) | 87 | #define SH7780_CS6_BASE_ADDR (SH7780_CS5_BASE_ADDR + SH7780_MEM_REGION_SIZE) |
141 | 88 | ||
142 | /* General PCI values */ | 89 | struct sh4_pci_address_map; |
143 | #define SH7780_PCI_HOST_BRIDGE 0x6 | ||
144 | |||
145 | /* Flags */ | ||
146 | #define SH7780_PCIC_NO_RESET 0x0001 | ||
147 | |||
148 | /* External functions defined per platform i.e. Big Sur, SE... (these could be routed | ||
149 | * through the machine vectors... */ | ||
150 | extern int pcibios_init_platform(void); | ||
151 | extern int pcibios_map_platform_irq(u8 slot, u8 pin); | ||
152 | |||
153 | struct sh7780_pci_address_space { | ||
154 | unsigned long base; | ||
155 | unsigned long size; | ||
156 | }; | ||
157 | |||
158 | struct sh7780_pci_address_map { | ||
159 | struct sh7780_pci_address_space window0; | ||
160 | struct sh7780_pci_address_space window1; | ||
161 | unsigned long flags; | ||
162 | }; | ||
163 | 90 | ||
164 | /* arch/sh/drivers/pci/pci-sh7780.c */ | 91 | /* arch/sh/drivers/pci/pci-sh7780.c */ |
165 | extern int sh7780_pcic_init(struct sh7780_pci_address_map *map); | 92 | int sh7780_pcic_init(struct sh4_pci_address_map *map); |
166 | 93 | ||
167 | #endif /* _PCI_SH7780_H_ */ | 94 | #endif /* _PCI_SH7780_H_ */ |
168 | |||