diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2010-01-29 08:19:04 -0500 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2010-01-29 08:19:04 -0500 |
| commit | a45635dfb08a1fa2cf77bf1f2c4074961ce2e625 (patch) | |
| tree | 9c8401158280d33137b6ffa3566743734da552c7 /arch/sh/drivers/pci/pci-sh7780.h | |
| parent | 9762528f37ddc7071509dddb10e7b4b3b957fd01 (diff) | |
sh: Reworked SH7780 PCI initialization.
This consolidates the PCI initialization code for all of the pci-sh7780
users, and sets up the memory window dynamically as opposed to using
hardcoded window positions.
A number of bugs were fixed at the same time, including the PIO handling
and master abort timeout settings being incorrect.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers/pci/pci-sh7780.h')
| -rw-r--r-- | arch/sh/drivers/pci/pci-sh7780.h | 54 |
1 files changed, 7 insertions, 47 deletions
diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h index 4a52478c97cf..dee069c3865d 100644 --- a/arch/sh/drivers/pci/pci-sh7780.h +++ b/arch/sh/drivers/pci/pci-sh7780.h | |||
| @@ -12,12 +12,11 @@ | |||
| 12 | #ifndef _PCI_SH7780_H_ | 12 | #ifndef _PCI_SH7780_H_ |
| 13 | #define _PCI_SH7780_H_ | 13 | #define _PCI_SH7780_H_ |
| 14 | 14 | ||
| 15 | /* Platform Specific Values */ | 15 | #define PCI_VENDOR_ID_RENESAS 0x1912 |
| 16 | #define SH7780_VENDOR_ID 0x1912 | 16 | #define PCI_DEVICE_ID_RENESAS_SH7781 0x0001 |
| 17 | #define SH7781_DEVICE_ID 0x0001 | 17 | #define PCI_DEVICE_ID_RENESAS_SH7780 0x0002 |
| 18 | #define SH7780_DEVICE_ID 0x0002 | 18 | #define PCI_DEVICE_ID_RENESAS_SH7763 0x0004 |
| 19 | #define SH7763_DEVICE_ID 0x0004 | 19 | #define PCI_DEVICE_ID_RENESAS_SH7785 0x0007 |
| 20 | #define SH7785_DEVICE_ID 0x0007 | ||
| 21 | 20 | ||
| 22 | /* SH7780 Control Registers */ | 21 | /* SH7780 Control Registers */ |
| 23 | #define PCIECR 0xFE000008 | 22 | #define PCIECR 0xFE000008 |
| @@ -36,35 +35,6 @@ | |||
| 36 | #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */ | 35 | #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */ |
| 37 | 36 | ||
| 38 | /* SH7780 PCI Config Registers */ | 37 | /* SH7780 PCI Config Registers */ |
| 39 | #define SH7780_PCIVID 0x000 /* Vendor ID */ | ||
| 40 | #define SH7780_PCIDID 0x002 /* Device ID */ | ||
| 41 | #define SH7780_PCICMD 0x004 /* Command */ | ||
| 42 | #define SH7780_PCISTATUS 0x006 /* Status */ | ||
| 43 | #define SH7780_PCIRID 0x008 /* Revision ID */ | ||
| 44 | #define SH7780_PCIPIF 0x009 /* Program Interface */ | ||
| 45 | #define SH7780_PCISUB 0x00a /* Sub class code */ | ||
| 46 | #define SH7780_PCIBCC 0x00b /* Base class code */ | ||
| 47 | #define SH7780_PCICLS 0x00c /* Cache line size */ | ||
| 48 | #define SH7780_PCILTM 0x00d /* latency timer */ | ||
| 49 | #define SH7780_PCIHDR 0x00e /* Header type */ | ||
| 50 | #define SH7780_PCIBIST 0x00f /* BIST */ | ||
| 51 | #define SH7780_PCIIBAR 0x010 /* IO Base address */ | ||
| 52 | #define SH7780_PCIMBAR0 0x014 /* Memory base address0 */ | ||
| 53 | #define SH7780_PCIMBAR1 0x018 /* Memory base address1 */ | ||
| 54 | #define SH7780_PCISVID 0x02c /* Sub system vendor ID */ | ||
| 55 | #define SH7780_PCISID 0x02e /* Sub system ID */ | ||
| 56 | #define SH7780_PCICP 0x034 | ||
| 57 | #define SH7780_PCIINTLINE 0x03c /* Interrupt line */ | ||
| 58 | #define SH7780_PCIINTPIN 0x03d /* Interrupt pin */ | ||
| 59 | #define SH7780_PCIMINGNT 0x03e /* Minumum grand */ | ||
| 60 | #define SH7780_PCIMAXLAT 0x03f /* Maxmum latency */ | ||
| 61 | #define SH7780_PCICID 0x040 | ||
| 62 | #define SH7780_PCINIP 0x041 | ||
| 63 | #define SH7780_PCIPMC 0x042 | ||
| 64 | #define SH7780_PCIPMCSR 0x044 | ||
| 65 | #define SH7780_PCIPMCSR_BSE 0x046 | ||
| 66 | #define SH7780_PCICDD 0x047 | ||
| 67 | |||
| 68 | #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */ | 38 | #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */ |
| 69 | #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */ | 39 | #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */ |
| 70 | #define SH7780_PCIAIR 0x11C /* Error Address Register */ | 40 | #define SH7780_PCIAIR 0x11C /* Error Address Register */ |
| @@ -78,6 +48,8 @@ | |||
| 78 | 48 | ||
| 79 | #define SH7780_PCIMBR0 0x1E0 | 49 | #define SH7780_PCIMBR0 0x1E0 |
| 80 | #define SH7780_PCIMBMR0 0x1E4 | 50 | #define SH7780_PCIMBMR0 0x1E4 |
| 51 | #define SH7780_PCIMBR1 0x1E8 | ||
| 52 | #define SH7780_PCIMBMR1 0x1EC | ||
| 81 | #define SH7780_PCIMBR2 0x1F0 | 53 | #define SH7780_PCIMBR2 0x1F0 |
| 82 | #define SH7780_PCIMBMR2 0x1F4 | 54 | #define SH7780_PCIMBMR2 0x1F4 |
| 83 | #define SH7780_PCIIOBR 0x1F8 | 55 | #define SH7780_PCIIOBR 0x1F8 |
| @@ -87,16 +59,4 @@ | |||
| 87 | #define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */ | 59 | #define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */ |
| 88 | #define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */ | 60 | #define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */ |
| 89 | 61 | ||
| 90 | /* General Memory Config Addresses */ | ||
| 91 | #define SH7780_CS0_BASE_ADDR 0x0 | ||
| 92 | #define SH7780_MEM_REGION_SIZE 0x04000000 | ||
| 93 | #define SH7780_CS1_BASE_ADDR (SH7780_CS0_BASE_ADDR + SH7780_MEM_REGION_SIZE) | ||
| 94 | #define SH7780_CS2_BASE_ADDR (SH7780_CS1_BASE_ADDR + SH7780_MEM_REGION_SIZE) | ||
| 95 | #define SH7780_CS3_BASE_ADDR (SH7780_CS2_BASE_ADDR + SH7780_MEM_REGION_SIZE) | ||
| 96 | #define SH7780_CS4_BASE_ADDR (SH7780_CS3_BASE_ADDR + SH7780_MEM_REGION_SIZE) | ||
| 97 | #define SH7780_CS5_BASE_ADDR (SH7780_CS4_BASE_ADDR + SH7780_MEM_REGION_SIZE) | ||
| 98 | #define SH7780_CS6_BASE_ADDR (SH7780_CS5_BASE_ADDR + SH7780_MEM_REGION_SIZE) | ||
| 99 | |||
| 100 | #define SH7780_32BIT_DDR_BASE_ADDR 0x40000000 | ||
| 101 | |||
| 102 | #endif /* _PCI_SH7780_H_ */ | 62 | #endif /* _PCI_SH7780_H_ */ |