Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (266 commits)
  sh: Tie sparseirq in to Kconfig.
  sh: Wire up sys_rt_tgsigqueueinfo.
  sh: Fix sys_pwritev() syscall table entry for sh32.
  sh: Fix sh4a llsc-based cmpxchg()
  sh: sh7724: Add JPU support
  sh: sh7724: INTC setting update
  sh: sh7722 clock framework rewrite
  sh: sh7366 clock framework rewrite
  sh: sh7343 clock framework rewrite
  sh: sh7724 clock framework rewrite V3
  sh: sh7723 clock framework rewrite V2
  sh: add enable()/disable()/set_rate() to div6 code
  sh: add AP325RXA mode pin configuration
  sh: add Migo-R mode pin configuration
  sh: sh7722 mode pin definitions
  sh: sh7724 mode pin comments
  sh: sh7723 mode pin V2
  sh: rework mode pin code
  sh: clock div6 helper code
  sh: clock div4 frequency table offset fix
  ...

1 files changed, 16 insertions, 25 deletions

diff --git a/arch/sh/drivers/pci/fixups-r7780rp.c b/arch/sh/drivers/pci/fixups-r7780rp.c
index 3e321df65d22..15ca65cb667e 100644
--- a/arch/sh/drivers/pci/fixups-r7780rp.c
+++ b/arch/sh/drivers/pci/fixups-r7780rp.c
@@ -11,35 +11,26 @@
  * for more details.
  */
 #include <linux/pci.h>
+#include <linux/io.h>
 #include "pci-sh4.h"
-#include <asm/io.h>
 
-int pci_fixup_pcic(void)
-{
-        pci_write_reg(0x000043ff, SH4_PCIINTM);
-        pci_write_reg(0x0000380f, SH4_PCIAINTM);
-
-        pci_write_reg(0xfbb00047, SH7780_PCICMD);
-        pci_write_reg(0x00000000, SH7780_PCIIBAR);
-
-        pci_write_reg(0x00011912, SH7780_PCISVID);
-        pci_write_reg(0x08000000, SH7780_PCICSCR0);
-        pci_write_reg(0x0000001b, SH7780_PCICSAR0);
-        pci_write_reg(0xfd000000, SH7780_PCICSCR1);
-        pci_write_reg(0x0000000f, SH7780_PCICSAR1);
-
-        pci_write_reg(0xfd000000, SH7780_PCIMBR0);
-        pci_write_reg(0x00fc0000, SH7780_PCIMBMR0);
+static char irq_tab[] __initdata = {
+        65, 66, 67, 68,
+};
 
-#ifdef CONFIG_32BIT
-        pci_write_reg(0xc0000000, SH7780_PCIMBR2);
-        pci_write_reg(0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
-#endif
+int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
+{
+        return irq_tab[slot];
+}
 
-        /* Set IOBR for windows containing area specified in pci.h */
-        pci_write_reg((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)),
-                      SH7780_PCIIOBR);
-        pci_write_reg(((SH7780_PCI_IO_SIZE-1) & (7<<18)), SH7780_PCIIOBMR);
+int pci_fixup_pcic(struct pci_channel *chan)
+{
+        pci_write_reg(chan, 0x000043ff, SH4_PCIINTM);
+        pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR);
+        pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0);
+        pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0);
+        pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1);
+        pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1);
 
         return 0;
 }