aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh/boards
diff options
context:
space:
mode:
authorPaul Mundt <lethal@linux-sh.org>2008-01-15 02:55:55 -0500
committerPaul Mundt <lethal@linux-sh.org>2008-01-27 23:19:03 -0500
commit03bbc0e6ba23700aea7fec801ac7e6c5a80f78f9 (patch)
tree8e57ecb5bdb1ba1bfdf581118967ab832e2920e8 /arch/sh/boards
parentd1eea50b0c6c998b713d824024c25c5001a5a8a4 (diff)
sh: r7785rp: Hook up the rest of the HL7785 FPGA IRQ vectors.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/boards')
-rw-r--r--arch/sh/boards/renesas/r7780rp/irq-r7785rp.c45
1 files changed, 33 insertions, 12 deletions
diff --git a/arch/sh/boards/renesas/r7780rp/irq-r7785rp.c b/arch/sh/boards/renesas/r7780rp/irq-r7785rp.c
index bbf18afc29a7..af5ec74b2b1e 100644
--- a/arch/sh/boards/renesas/r7780rp/irq-r7785rp.c
+++ b/arch/sh/boards/renesas/r7780rp/irq-r7785rp.c
@@ -2,7 +2,7 @@
2 * Renesas Solutions Highlander R7785RP Support. 2 * Renesas Solutions Highlander R7785RP Support.
3 * 3 *
4 * Copyright (C) 2002 Atom Create Engineering Co., Ltd. 4 * Copyright (C) 2002 Atom Create Engineering Co., Ltd.
5 * Copyright (C) 2006 Paul Mundt 5 * Copyright (C) 2006 - 2008 Paul Mundt
6 * Copyright (C) 2007 Magnus Damm 6 * Copyright (C) 2007 Magnus Damm
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
@@ -17,31 +17,52 @@
17enum { 17enum {
18 UNUSED = 0, 18 UNUSED = 0,
19 19
20 /* board specific interrupt sources */ 20 /* FPGA specific interrupt sources */
21 AX88796, /* Ethernet controller */ 21 CF, /* Compact Flash */
22 CF, /* Compact Flash */ 22 SMBUS, /* SMBUS */
23 TP, /* Touch panel */
24 RTC, /* RTC Alarm */
25 TH_ALERT, /* Temperature sensor */
26 AX88796, /* Ethernet controller */
27
28 /* external bus connector */
29 EXT0, EXT1, EXT2, EXT3, EXT4, EXT5, EXT6, EXT7,
23}; 30};
24 31
25static struct intc_vect vectors[] __initdata = { 32static struct intc_vect vectors[] __initdata = {
26 INTC_IRQ(CF, IRQ_CF), 33 INTC_IRQ(CF, IRQ_CF),
34 INTC_IRQ(SMBUS, IRQ_SMBUS),
35 INTC_IRQ(TP, IRQ_TP),
36 INTC_IRQ(RTC, IRQ_RTC),
37 INTC_IRQ(TH_ALERT, IRQ_TH_ALERT),
38
39 INTC_IRQ(EXT0, IRQ_EXT0), INTC_IRQ(EXT1, IRQ_EXT1),
40 INTC_IRQ(EXT2, IRQ_EXT2), INTC_IRQ(EXT3, IRQ_EXT3),
41
42 INTC_IRQ(EXT4, IRQ_EXT4), INTC_IRQ(EXT5, IRQ_EXT5),
43 INTC_IRQ(EXT6, IRQ_EXT6), INTC_IRQ(EXT7, IRQ_EXT7),
44
27 INTC_IRQ(AX88796, IRQ_AX88796), 45 INTC_IRQ(AX88796, IRQ_AX88796),
28}; 46};
29 47
30static struct intc_mask_reg mask_registers[] __initdata = { 48static struct intc_mask_reg mask_registers[] __initdata = {
31 { 0xa4000010, 0, 16, /* IRLMCR1 */ 49 { 0xa4000010, 0, 16, /* IRLMCR1 */
32 { 0, 0, 0, 0, CF, AX88796, 0, 0, 50 { 0, 0, 0, 0, CF, AX88796, SMBUS, TP,
33 0, 0, 0, 0, 0, 0, 0, 0 } }, 51 RTC, 0, TH_ALERT, 0, 0, 0, 0, 0 } },
52 { 0xa4000012, 0, 16, /* IRLMCR2 */
53 { 0, 0, 0, 0, 0, 0, 0, 0,
54 EXT7, EXT6, EXT5, EXT4, EXT3, EXT2, EXT1, EXT0 } },
34}; 55};
35 56
36static unsigned char irl2irq[HL_NR_IRL] __initdata = { 57static unsigned char irl2irq[HL_NR_IRL] __initdata = {
37 0, IRQ_CF, 0, 0, 58 0, IRQ_CF, IRQ_EXT4, IRQ_EXT5,
38 0, 0, 0, 0, 59 IRQ_EXT6, IRQ_EXT7, IRQ_SMBUS, IRQ_TP,
39 0, 0, IRQ_AX88796, 0, 60 IRQ_RTC, IRQ_TH_ALERT, IRQ_AX88796, IRQ_EXT0,
40 0, 0, 0, 61 IRQ_EXT1, IRQ_EXT2, IRQ_EXT3,
41}; 62};
42 63
43static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors, 64static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors,
44 NULL, mask_registers, NULL, NULL); 65 NULL, NULL, mask_registers, NULL, NULL);
45 66
46unsigned char * __init highlander_init_irq_r7785rp(void) 67unsigned char * __init highlander_init_irq_r7785rp(void)
47{ 68{
@@ -58,7 +79,7 @@ unsigned char * __init highlander_init_irq_r7785rp(void)
58 ctrl_outw(0x7060, PA_IRLPRC); /* FPGA IRLC */ 79 ctrl_outw(0x7060, PA_IRLPRC); /* FPGA IRLC */
59 ctrl_outw(0x0000, PA_IRLPRD); /* FPGA IRLD */ 80 ctrl_outw(0x0000, PA_IRLPRD); /* FPGA IRLD */
60 ctrl_outw(0x4321, PA_IRLPRE); /* FPGA IRLE */ 81 ctrl_outw(0x4321, PA_IRLPRE); /* FPGA IRLE */
61 ctrl_outw(0x0000, PA_IRLPRF); /* FPGA IRLF */ 82 ctrl_outw(0xdcba, PA_IRLPRF); /* FPGA IRLF */
62 83
63 register_intc_controller(&intc_desc); 84 register_intc_controller(&intc_desc);
64 return irl2irq; 85 return irl2irq;