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authorPaul Mundt <lethal@linux-sh.org>2008-12-16 23:14:22 -0500
committerPaul Mundt <lethal@linux-sh.org>2008-12-22 04:44:45 -0500
commit0ef0e6ca426d28561b752e5f576932659295b928 (patch)
treed725eb9b4ab122ddb0ab1fdd31569389767c387f /arch/sh/boards
parent43eeb0fb9f4e2aaefc4ae9dc964308ce8f55998b (diff)
sh: mach-microdev: Split out the fdc37c93xapm initialization code.
This makes the microdev code a bit more readable, and moves the setup for the SuperIO out on its own. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/boards')
-rw-r--r--arch/sh/boards/mach-microdev/Makefile2
-rw-r--r--arch/sh/boards/mach-microdev/fdc37c93xapm.c160
-rw-r--r--arch/sh/boards/mach-microdev/setup.c186
3 files changed, 167 insertions, 181 deletions
diff --git a/arch/sh/boards/mach-microdev/Makefile b/arch/sh/boards/mach-microdev/Makefile
index 57f6375043f4..4e3588e8806b 100644
--- a/arch/sh/boards/mach-microdev/Makefile
+++ b/arch/sh/boards/mach-microdev/Makefile
@@ -2,4 +2,4 @@
2# Makefile for the SuperH MicroDev specific parts of the kernel 2# Makefile for the SuperH MicroDev specific parts of the kernel
3# 3#
4 4
5obj-y := setup.o irq.o io.o 5obj-y := setup.o irq.o io.o fdc37c93xapm.o
diff --git a/arch/sh/boards/mach-microdev/fdc37c93xapm.c b/arch/sh/boards/mach-microdev/fdc37c93xapm.c
new file mode 100644
index 000000000000..458a7cf5fb46
--- /dev/null
+++ b/arch/sh/boards/mach-microdev/fdc37c93xapm.c
@@ -0,0 +1,160 @@
1/*
2 *
3 * Setup for the SMSC FDC37C93xAPM
4 *
5 * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
6 * Copyright (C) 2003, 2004 SuperH, Inc.
7 * Copyright (C) 2004, 2005 Paul Mundt
8 *
9 * SuperH SH4-202 MicroDev board support.
10 *
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
13 */
14#include <linux/init.h>
15#include <linux/ioport.h>
16#include <linux/io.h>
17#include <linux/err.h>
18#include <mach/microdev.h>
19
20#define SMSC_CONFIG_PORT_ADDR (0x3F0)
21#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR
22#define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1)
23
24#define SMSC_ENTER_CONFIG_KEY 0x55
25#define SMSC_EXIT_CONFIG_KEY 0xaa
26
27#define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */
28#define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */
29#define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */
30#define SMSC_ACTIVATE_INDEX 0x30 /* Activate */
31#define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */
32#define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */
33#define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */
34#define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */
35#define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */
36#define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */
37
38#define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */
39#define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */
40#define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */
41#define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */
42#define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */
43#define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */
44#define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */
45
46#define SMSC_READ_INDEXED(index) ({ \
47 outb((index), SMSC_INDEX_PORT_ADDR); \
48 inb(SMSC_DATA_PORT_ADDR); })
49#define SMSC_WRITE_INDEXED(val, index) ({ \
50 outb((index), SMSC_INDEX_PORT_ADDR); \
51 outb((val), SMSC_DATA_PORT_ADDR); })
52
53#define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */
54#define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */
55#define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */
56#define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */
57
58#define SERIAL1_PRIMARY_BASE 0x03f8
59#define SERIAL2_PRIMARY_BASE 0x02f8
60
61#define MSB(x) ( (x) >> 8 )
62#define LSB(x) ( (x) & 0xff )
63
64 /* General-Purpose base address on CPU-board FPGA */
65#define MICRODEV_FPGA_GP_BASE 0xa6100000ul
66
67static int __init smsc_superio_setup(void)
68{
69
70 unsigned char devid, devrev;
71
72 /* Initially the chip is in run state */
73 /* Put it into configuration state */
74 outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
75
76 /* Read device ID info */
77 devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
78 devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
79
80 if ((devid == 0x30) && (devrev == 0x01))
81 printk("SMSC FDC37C93xAPM SuperIO device detected\n");
82 else
83 return -ENODEV;
84
85 /* Select the keyboard device */
86 SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
87 /* enable it */
88 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
89 /* enable the interrupts */
90 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX);
91 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX);
92
93 /* Select the Serial #1 device */
94 SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
95 /* enable it */
96 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
97 /* program with port addresses */
98 SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
99 SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
100 SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
101 /* enable the interrupts */
102 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX);
103
104 /* Select the Serial #2 device */
105 SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
106 /* enable it */
107 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
108 /* program with port addresses */
109 SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
110 SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
111 SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
112 /* enable the interrupts */
113 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX);
114
115 /* Select the IDE#1 device */
116 SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
117 /* enable it */
118 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
119 /* program with port addresses */
120 SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
121 SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
122 SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
123 SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
124 SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX);
125 SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX);
126 /* select the interrupt */
127 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX);
128
129 /* Select the IDE#2 device */
130 SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
131 /* enable it */
132 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
133 /* program with port addresses */
134 SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
135 SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
136 SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
137 SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
138 /* select the interrupt */
139 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX);
140
141 /* Select the configuration registers */
142 SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX);
143 /* enable the appropriate GPIO pins for IDE functionality:
144 * bit[0] In/Out 1==input; 0==output
145 * bit[1] Polarity 1==invert; 0==no invert
146 * bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable
147 * bit[3:4] Function Select 00==original; 01==Alternate Function #1
148 */
149 SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
150 SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
151 SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
152 SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
153 SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */
154
155 /* Exit the configuration state */
156 outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
157
158 return 0;
159}
160device_initcall(smsc_superio_setup);
diff --git a/arch/sh/boards/mach-microdev/setup.c b/arch/sh/boards/mach-microdev/setup.c
index 9f5a97812e75..d1df2a4fb9b8 100644
--- a/arch/sh/boards/mach-microdev/setup.c
+++ b/arch/sh/boards/mach-microdev/setup.c
@@ -17,64 +17,12 @@
17#include <mach/microdev.h> 17#include <mach/microdev.h>
18#include <asm/io.h> 18#include <asm/io.h>
19#include <asm/machvec.h> 19#include <asm/machvec.h>
20 20#include <asm/sizes.h>
21 /*
22 * Setup for the SMSC FDC37C93xAPM
23 */
24#define SMSC_CONFIG_PORT_ADDR (0x3F0)
25#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR
26#define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1)
27
28#define SMSC_ENTER_CONFIG_KEY 0x55
29#define SMSC_EXIT_CONFIG_KEY 0xaa
30
31#define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */
32#define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */
33#define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */
34#define SMSC_ACTIVATE_INDEX 0x30 /* Activate */
35#define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */
36#define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */
37#define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */
38#define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */
39#define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */
40#define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */
41
42#define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */
43#define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */
44#define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */
45#define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */
46#define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */
47#define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */
48#define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */
49
50#define SMSC_READ_INDEXED(index) ({ \
51 outb((index), SMSC_INDEX_PORT_ADDR); \
52 inb(SMSC_DATA_PORT_ADDR); })
53#define SMSC_WRITE_INDEXED(val, index) ({ \
54 outb((index), SMSC_INDEX_PORT_ADDR); \
55 outb((val), SMSC_DATA_PORT_ADDR); })
56
57#define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */
58#define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */
59#define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */
60#define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */
61
62#define SERIAL1_PRIMARY_BASE 0x03f8
63#define SERIAL2_PRIMARY_BASE 0x02f8
64
65#define MSB(x) ( (x) >> 8 )
66#define LSB(x) ( (x) & 0xff )
67
68 /* General-Purpose base address on CPU-board FPGA */
69#define MICRODEV_FPGA_GP_BASE 0xa6100000ul
70
71 /* assume a Keyboard Controller is present */
72int microdev_kbd_controller_present = 1;
73 21
74static struct resource smc91x_resources[] = { 22static struct resource smc91x_resources[] = {
75 [0] = { 23 [0] = {
76 .start = 0x300, 24 .start = 0x300,
77 .end = 0x300 + 0x0001000 - 1, 25 .end = 0x300 + SZ_4K - 1,
78 .flags = IORESOURCE_MEM, 26 .flags = IORESOURCE_MEM,
79 }, 27 },
80 [1] = { 28 [1] = {
@@ -91,7 +39,6 @@ static struct platform_device smc91x_device = {
91 .resource = smc91x_resources, 39 .resource = smc91x_resources,
92}; 40};
93 41
94#ifdef CONFIG_FB_S1D13XXX
95static struct s1d13xxxfb_regval s1d13806_initregs[] = { 42static struct s1d13xxxfb_regval s1d13806_initregs[] = {
96 { S1DREG_MISC, 0x00 }, 43 { S1DREG_MISC, 0x00 },
97 { S1DREG_COM_DISP_MODE, 0x00 }, 44 { S1DREG_COM_DISP_MODE, 0x00 },
@@ -210,12 +157,12 @@ static struct s1d13xxxfb_pdata s1d13806_platform_data = {
210static struct resource s1d13806_resources[] = { 157static struct resource s1d13806_resources[] = {
211 [0] = { 158 [0] = {
212 .start = 0x07200000, 159 .start = 0x07200000,
213 .end = 0x07200000 + 0x00200000 - 1, 160 .end = 0x07200000 + SZ_2M - 1,
214 .flags = IORESOURCE_MEM, 161 .flags = IORESOURCE_MEM,
215 }, 162 },
216 [1] = { 163 [1] = {
217 .start = 0x07000000, 164 .start = 0x07000000,
218 .end = 0x07000000 + 0x00200000 - 1, 165 .end = 0x07000000 + SZ_2M - 1,
219 .flags = IORESOURCE_MEM, 166 .flags = IORESOURCE_MEM,
220 }, 167 },
221}; 168};
@@ -230,145 +177,24 @@ static struct platform_device s1d13806_device = {
230 .platform_data = &s1d13806_platform_data, 177 .platform_data = &s1d13806_platform_data,
231 }, 178 },
232}; 179};
233#endif
234 180
235static struct platform_device *microdev_devices[] __initdata = { 181static struct platform_device *microdev_devices[] __initdata = {
236 &smc91x_device, 182 &smc91x_device,
237#ifdef CONFIG_FB_S1D13XXX
238 &s1d13806_device, 183 &s1d13806_device,
239#endif
240}; 184};
241 185
242static int __init microdev_devices_setup(void) 186static int __init microdev_devices_setup(void)
243{ 187{
244 return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices)); 188 return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices));
245} 189}
246 190device_initcall(microdev_devices_setup);
247/*
248 * Setup for the SMSC FDC37C93xAPM
249 */
250static int __init smsc_superio_setup(void)
251{
252
253 unsigned char devid, devrev;
254
255 /* Initially the chip is in run state */
256 /* Put it into configuration state */
257 outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
258
259 /* Read device ID info */
260 devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
261 devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
262 if ( (devid==0x30) && (devrev==0x01) )
263 {
264 printk("SMSC FDC37C93xAPM SuperIO device detected\n");
265 }
266 else
267 { /* not the device identity we expected */
268 printk("Not detected a SMSC FDC37C93xAPM SuperIO device (devid=0x%02x, rev=0x%02x)\n",
269 devid, devrev);
270 /* inform the keyboard driver that we have no keyboard controller */
271 microdev_kbd_controller_present = 0;
272 /* little point in doing anything else in this functon */
273 return 0;
274 }
275
276 /* Select the keyboard device */
277 SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
278 /* enable it */
279 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
280 /* enable the interrupts */
281 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX);
282 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX);
283
284 /* Select the Serial #1 device */
285 SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
286 /* enable it */
287 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
288 /* program with port addresses */
289 SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
290 SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
291 SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
292 /* enable the interrupts */
293 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX);
294
295 /* Select the Serial #2 device */
296 SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
297 /* enable it */
298 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
299 /* program with port addresses */
300 SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
301 SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
302 SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
303 /* enable the interrupts */
304 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX);
305
306 /* Select the IDE#1 device */
307 SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
308 /* enable it */
309 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
310 /* program with port addresses */
311 SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
312 SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
313 SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
314 SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
315 SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX);
316 SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX);
317 /* select the interrupt */
318 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX);
319
320 /* Select the IDE#2 device */
321 SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
322 /* enable it */
323 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
324 /* program with port addresses */
325 SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
326 SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
327 SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
328 SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
329 /* select the interrupt */
330 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX);
331
332 /* Select the configuration registers */
333 SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX);
334 /* enable the appropriate GPIO pins for IDE functionality:
335 * bit[0] In/Out 1==input; 0==output
336 * bit[1] Polarity 1==invert; 0==no invert
337 * bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable
338 * bit[3:4] Function Select 00==original; 01==Alternate Function #1
339 */
340 SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
341 SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
342 SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
343 SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
344 SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */
345
346 /* Exit the configuration state */
347 outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
348
349 return 0;
350}
351
352static void __init microdev_setup(char **cmdline_p)
353{
354 int * const fpgaRevisionRegister = (int*)(MICRODEV_FPGA_GP_BASE + 0x8ul);
355 const int fpgaRevision = *fpgaRevisionRegister;
356 int * const CacheControlRegister = (int*)CCR;
357
358 device_initcall(microdev_devices_setup);
359 device_initcall(smsc_superio_setup);
360
361 printk("SuperH %s board (FPGA rev: 0x%0x, CCR: 0x%0x)\n",
362 get_system_type(), fpgaRevision, *CacheControlRegister);
363}
364 191
365/* 192/*
366 * The Machine Vector 193 * The Machine Vector
367 */ 194 */
368static struct sh_machine_vector mv_sh4202_microdev __initmv = { 195static struct sh_machine_vector mv_sh4202_microdev __initmv = {
369 .mv_name = "SH4-202 MicroDev", 196 .mv_name = "SH4-202 MicroDev",
370 .mv_setup = microdev_setup, 197 .mv_nr_irqs = 72,
371 .mv_nr_irqs = 72, /* QQQ need to check this - use the MACRO */
372 198
373 .mv_inb = microdev_inb, 199 .mv_inb = microdev_inb,
374 .mv_inw = microdev_inw, 200 .mv_inw = microdev_inw,
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