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authorIngo Molnar <mingo@elte.hu>2008-07-28 17:32:00 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-28 17:32:00 -0400
commit9e3ee1c39c0cc71222f9980ccbf87fe072897eef (patch)
tree99462000e6f0d4f907cb2fc690f19d4d441ba0f3 /arch/sh/boards
parente56b3bc7942982ac2589c942fb345e38bc7a341a (diff)
parentf934fb19ef34730263e6afc01e8ec27a8a71470f (diff)
Merge branch 'linus' into cpus4096
Conflicts: kernel/stop_machine.c Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/sh/boards')
-rw-r--r--arch/sh/boards/dreamcast/rtc.c4
-rw-r--r--arch/sh/boards/renesas/ap325rxa/Makefile1
-rw-r--r--arch/sh/boards/renesas/ap325rxa/setup.c313
-rw-r--r--arch/sh/boards/renesas/migor/Kconfig15
-rw-r--r--arch/sh/boards/renesas/migor/Makefile1
-rw-r--r--arch/sh/boards/renesas/migor/lcd_qvga.c165
-rw-r--r--arch/sh/boards/renesas/migor/setup.c276
-rw-r--r--arch/sh/boards/renesas/rsk7203/Makefile1
-rw-r--r--arch/sh/boards/renesas/rsk7203/setup.c126
-rw-r--r--arch/sh/boards/renesas/sh7763rdp/Makefile1
-rw-r--r--arch/sh/boards/renesas/sh7763rdp/irq.c45
-rw-r--r--arch/sh/boards/renesas/sh7763rdp/setup.c128
-rw-r--r--arch/sh/boards/renesas/sh7785lcr/Makefile1
-rw-r--r--arch/sh/boards/renesas/sh7785lcr/setup.c302
-rw-r--r--arch/sh/boards/se/7343/irq.c232
-rw-r--r--arch/sh/boards/se/7343/setup.c70
-rw-r--r--arch/sh/boards/se/770x/io.c59
-rw-r--r--arch/sh/boards/se/770x/setup.c53
-rw-r--r--arch/sh/boards/se/7722/setup.c8
19 files changed, 1558 insertions, 243 deletions
diff --git a/arch/sh/boards/dreamcast/rtc.c b/arch/sh/boards/dreamcast/rtc.c
index b3a876a3b859..a7433685798d 100644
--- a/arch/sh/boards/dreamcast/rtc.c
+++ b/arch/sh/boards/dreamcast/rtc.c
@@ -30,7 +30,7 @@
30 * 30 *
31 * Grabs the current RTC seconds counter and adjusts it to the Unix Epoch. 31 * Grabs the current RTC seconds counter and adjusts it to the Unix Epoch.
32 */ 32 */
33void aica_rtc_gettimeofday(struct timespec *ts) 33static void aica_rtc_gettimeofday(struct timespec *ts)
34{ 34{
35 unsigned long val1, val2; 35 unsigned long val1, val2;
36 36
@@ -54,7 +54,7 @@ void aica_rtc_gettimeofday(struct timespec *ts)
54 * 54 *
55 * Adjusts the given @tv to the AICA Epoch and sets the RTC seconds counter. 55 * Adjusts the given @tv to the AICA Epoch and sets the RTC seconds counter.
56 */ 56 */
57int aica_rtc_settimeofday(const time_t secs) 57static int aica_rtc_settimeofday(const time_t secs)
58{ 58{
59 unsigned long val1, val2; 59 unsigned long val1, val2;
60 unsigned long adj = secs + TWENTY_YEARS; 60 unsigned long adj = secs + TWENTY_YEARS;
diff --git a/arch/sh/boards/renesas/ap325rxa/Makefile b/arch/sh/boards/renesas/ap325rxa/Makefile
new file mode 100644
index 000000000000..f663768429f0
--- /dev/null
+++ b/arch/sh/boards/renesas/ap325rxa/Makefile
@@ -0,0 +1 @@
obj-y := setup.o
diff --git a/arch/sh/boards/renesas/ap325rxa/setup.c b/arch/sh/boards/renesas/ap325rxa/setup.c
new file mode 100644
index 000000000000..7fa74462bd9f
--- /dev/null
+++ b/arch/sh/boards/renesas/ap325rxa/setup.c
@@ -0,0 +1,313 @@
1/*
2 * Renesas - AP-325RXA
3 * (Compatible with Algo System ., LTD. - AP-320A)
4 *
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 * Author : Yusuke Goda <goda.yuske@renesas.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/init.h>
14#include <linux/device.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/mtd/physmap.h>
18#include <linux/delay.h>
19#include <linux/i2c.h>
20#include <linux/delay.h>
21#include <linux/smc911x.h>
22#include <media/soc_camera_platform.h>
23#include <media/sh_mobile_ceu.h>
24#include <asm/sh_mobile_lcdc.h>
25#include <asm/io.h>
26#include <asm/clock.h>
27
28static struct smc911x_platdata smc911x_info = {
29 .flags = SMC911X_USE_32BIT,
30 .irq_flags = IRQF_TRIGGER_LOW,
31};
32
33static struct resource smc9118_resources[] = {
34 [0] = {
35 .start = 0xb6080000,
36 .end = 0xb60fffff,
37 .flags = IORESOURCE_MEM,
38 },
39 [1] = {
40 .start = 35,
41 .end = 35,
42 .flags = IORESOURCE_IRQ,
43 }
44};
45
46static struct platform_device smc9118_device = {
47 .name = "smc911x",
48 .id = -1,
49 .num_resources = ARRAY_SIZE(smc9118_resources),
50 .resource = smc9118_resources,
51 .dev = {
52 .platform_data = &smc911x_info,
53 },
54};
55
56static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
57 {
58 .name = "uboot",
59 .offset = 0,
60 .size = (1 * 1024 * 1024),
61 .mask_flags = MTD_WRITEABLE, /* Read-only */
62 }, {
63 .name = "kernel",
64 .offset = MTDPART_OFS_APPEND,
65 .size = (2 * 1024 * 1024),
66 }, {
67 .name = "other",
68 .offset = MTDPART_OFS_APPEND,
69 .size = MTDPART_SIZ_FULL,
70 },
71};
72
73static struct physmap_flash_data ap325rxa_nor_flash_data = {
74 .width = 2,
75 .parts = ap325rxa_nor_flash_partitions,
76 .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
77};
78
79static struct resource ap325rxa_nor_flash_resources[] = {
80 [0] = {
81 .name = "NOR Flash",
82 .start = 0x00000000,
83 .end = 0x00ffffff,
84 .flags = IORESOURCE_MEM,
85 }
86};
87
88static struct platform_device ap325rxa_nor_flash_device = {
89 .name = "physmap-flash",
90 .resource = ap325rxa_nor_flash_resources,
91 .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
92 .dev = {
93 .platform_data = &ap325rxa_nor_flash_data,
94 },
95};
96
97#define FPGA_LCDREG 0xB4100180
98#define FPGA_BKLREG 0xB4100212
99#define FPGA_LCDREG_VAL 0x0018
100#define PORT_PHCR 0xA405010E
101#define PORT_PLCR 0xA4050114
102#define PORT_PMCR 0xA4050116
103#define PORT_PRCR 0xA405011C
104#define PORT_PSCR 0xA405011E
105#define PORT_PZCR 0xA405014C
106#define PORT_HIZCRA 0xA4050158
107#define PORT_MSELCRB 0xA4050182
108#define PORT_PSDR 0xA405013E
109#define PORT_PZDR 0xA405016C
110#define PORT_PSELD 0xA4050154
111
112static void ap320_wvga_power_on(void *board_data)
113{
114 msleep(100);
115
116 /* ASD AP-320/325 LCD ON */
117 ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);
118
119 /* backlight */
120 ctrl_outw((ctrl_inw(PORT_PSCR) & ~0x00C0) | 0x40, PORT_PSCR);
121 ctrl_outb(ctrl_inb(PORT_PSDR) & ~0x08, PORT_PSDR);
122 ctrl_outw(0x100, FPGA_BKLREG);
123}
124
125static struct sh_mobile_lcdc_info lcdc_info = {
126 .clock_source = LCDC_CLK_EXTERNAL,
127 .ch[0] = {
128 .chan = LCDC_CHAN_MAINLCD,
129 .bpp = 16,
130 .interface_type = RGB18,
131 .clock_divider = 1,
132 .lcd_cfg = {
133 .name = "LB070WV1",
134 .xres = 800,
135 .yres = 480,
136 .left_margin = 40,
137 .right_margin = 160,
138 .hsync_len = 8,
139 .upper_margin = 63,
140 .lower_margin = 80,
141 .vsync_len = 1,
142 .sync = 0, /* hsync and vsync are active low */
143 },
144 .board_cfg = {
145 .display_on = ap320_wvga_power_on,
146 },
147 }
148};
149
150static struct resource lcdc_resources[] = {
151 [0] = {
152 .name = "LCDC",
153 .start = 0xfe940000, /* P4-only space */
154 .end = 0xfe941fff,
155 .flags = IORESOURCE_MEM,
156 },
157};
158
159static struct platform_device lcdc_device = {
160 .name = "sh_mobile_lcdc_fb",
161 .num_resources = ARRAY_SIZE(lcdc_resources),
162 .resource = lcdc_resources,
163 .dev = {
164 .platform_data = &lcdc_info,
165 },
166};
167
168static unsigned char camera_ncm03j_magic[] =
169{
170 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
171 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
172 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
173 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
174 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
175 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
176 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
177 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
178 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
179 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
180 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
181 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
182 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
183 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
184 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
185 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
186};
187
188static int camera_set_capture(struct soc_camera_platform_info *info,
189 int enable)
190{
191 struct i2c_adapter *a = i2c_get_adapter(0);
192 struct i2c_msg msg;
193 int ret = 0;
194 int i;
195
196 if (!enable)
197 return 0; /* no disable for now */
198
199 for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
200 u_int8_t buf[8];
201
202 msg.addr = 0x6e;
203 msg.buf = buf;
204 msg.len = 2;
205 msg.flags = 0;
206
207 buf[0] = camera_ncm03j_magic[i];
208 buf[1] = camera_ncm03j_magic[i + 1];
209
210 ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
211 }
212
213 return ret;
214}
215
216static struct soc_camera_platform_info camera_info = {
217 .iface = 0,
218 .format_name = "UYVY",
219 .format_depth = 16,
220 .format = {
221 .pixelformat = V4L2_PIX_FMT_UYVY,
222 .colorspace = V4L2_COLORSPACE_SMPTE170M,
223 .width = 640,
224 .height = 480,
225 },
226 .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
227 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
228 .set_capture = camera_set_capture,
229};
230
231static struct platform_device camera_device = {
232 .name = "soc_camera_platform",
233 .dev = {
234 .platform_data = &camera_info,
235 },
236};
237
238static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
239 .flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
240 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
241};
242
243static struct resource ceu_resources[] = {
244 [0] = {
245 .name = "CEU",
246 .start = 0xfe910000,
247 .end = 0xfe91009f,
248 .flags = IORESOURCE_MEM,
249 },
250 [1] = {
251 .start = 52,
252 .flags = IORESOURCE_IRQ,
253 },
254 [2] = {
255 /* place holder for contiguous memory */
256 },
257};
258
259static struct platform_device ceu_device = {
260 .name = "sh_mobile_ceu",
261 .num_resources = ARRAY_SIZE(ceu_resources),
262 .resource = ceu_resources,
263 .dev = {
264 .platform_data = &sh_mobile_ceu_info,
265 },
266};
267
268static struct platform_device *ap325rxa_devices[] __initdata = {
269 &smc9118_device,
270 &ap325rxa_nor_flash_device,
271 &lcdc_device,
272 &ceu_device,
273 &camera_device,
274};
275
276static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
277};
278
279static int __init ap325rxa_devices_setup(void)
280{
281 clk_always_enable("mstp200"); /* LCDC */
282 clk_always_enable("mstp203"); /* CEU */
283
284 platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
285
286 i2c_register_board_info(0, ap325rxa_i2c_devices,
287 ARRAY_SIZE(ap325rxa_i2c_devices));
288
289 return platform_add_devices(ap325rxa_devices,
290 ARRAY_SIZE(ap325rxa_devices));
291}
292device_initcall(ap325rxa_devices_setup);
293
294static void __init ap325rxa_setup(char **cmdline_p)
295{
296 /* LCDC configuration */
297 ctrl_outw(ctrl_inw(PORT_PHCR) & ~0xffff, PORT_PHCR);
298 ctrl_outw(ctrl_inw(PORT_PLCR) & ~0xffff, PORT_PLCR);
299 ctrl_outw(ctrl_inw(PORT_PMCR) & ~0xffff, PORT_PMCR);
300 ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x03ff, PORT_PRCR);
301 ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01C0, PORT_HIZCRA);
302
303 /* CEU */
304 ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
305 ctrl_outw(ctrl_inw(PORT_PSELD) & ~0x0003, PORT_PSELD);
306 ctrl_outw((ctrl_inw(PORT_PZCR) & ~0xff00) | 0x5500, PORT_PZCR);
307 ctrl_outb((ctrl_inb(PORT_PZDR) & ~0xf0) | 0x20, PORT_PZDR);
308}
309
310static struct sh_machine_vector mv_ap325rxa __initmv = {
311 .mv_name = "AP-325RXA",
312 .mv_setup = ap325rxa_setup,
313};
diff --git a/arch/sh/boards/renesas/migor/Kconfig b/arch/sh/boards/renesas/migor/Kconfig
new file mode 100644
index 000000000000..a7b3b728ec3c
--- /dev/null
+++ b/arch/sh/boards/renesas/migor/Kconfig
@@ -0,0 +1,15 @@
1if SH_MIGOR
2
3choice
4 prompt "Migo-R LCD Panel Board Selection"
5 default SH_MIGOR_QVGA
6
7config SH_MIGOR_QVGA
8 bool "QVGA (320x240)"
9
10config SH_MIGOR_RTA_WVGA
11 bool "RTA WVGA (800x480)"
12
13endchoice
14
15endif
diff --git a/arch/sh/boards/renesas/migor/Makefile b/arch/sh/boards/renesas/migor/Makefile
index 77037567633b..5f231dd25c0e 100644
--- a/arch/sh/boards/renesas/migor/Makefile
+++ b/arch/sh/boards/renesas/migor/Makefile
@@ -1 +1,2 @@
1obj-y := setup.o 1obj-y := setup.o
2obj-$(CONFIG_SH_MIGOR_QVGA) += lcd_qvga.o
diff --git a/arch/sh/boards/renesas/migor/lcd_qvga.c b/arch/sh/boards/renesas/migor/lcd_qvga.c
new file mode 100644
index 000000000000..6e9609596448
--- /dev/null
+++ b/arch/sh/boards/renesas/migor/lcd_qvga.c
@@ -0,0 +1,165 @@
1/*
2 * Support for SuperH MigoR Quarter VGA LCD Panel
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * Based on lcd_powertip.c from Kenati Technologies Pvt Ltd.
7 * Copyright (c) 2007 Ujjwal Pande <ujjwal@kenati.com>,
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/fb.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <asm/sh_mobile_lcdc.h>
21#include <asm/migor.h>
22
23/* LCD Module is a PH240320T according to board schematics. This module
24 * is made up of a 240x320 LCD hooked up to a R61505U (or HX8347-A01?)
25 * Driver IC. This IC is connected to the SH7722 built-in LCDC using a
26 * SYS-80 interface configured in 16 bit mode.
27 *
28 * Index 0: "Device Code Read" returns 0x1505.
29 */
30
31static void reset_lcd_module(void)
32{
33 ctrl_outb(ctrl_inb(PORT_PHDR) & ~0x04, PORT_PHDR);
34 mdelay(2);
35 ctrl_outb(ctrl_inb(PORT_PHDR) | 0x04, PORT_PHDR);
36 mdelay(1);
37}
38
39/* DB0-DB7 are connected to D1-D8, and DB8-DB15 to D10-D17 */
40
41static unsigned long adjust_reg18(unsigned short data)
42{
43 unsigned long tmp1, tmp2;
44
45 tmp1 = (data<<1 | 0x00000001) & 0x000001FF;
46 tmp2 = (data<<2 | 0x00000200) & 0x0003FE00;
47 return tmp1 | tmp2;
48}
49
50static void write_reg(void *sys_ops_handle,
51 struct sh_mobile_lcdc_sys_bus_ops *sys_ops,
52 unsigned short reg, unsigned short data)
53{
54 sys_ops->write_index(sys_ops_handle, adjust_reg18(reg << 8 | data));
55}
56
57static void write_reg16(void *sys_ops_handle,
58 struct sh_mobile_lcdc_sys_bus_ops *sys_ops,
59 unsigned short reg, unsigned short data)
60{
61 sys_ops->write_index(sys_ops_handle, adjust_reg18(reg));
62 sys_ops->write_data(sys_ops_handle, adjust_reg18(data));
63}
64
65static unsigned long read_reg16(void *sys_ops_handle,
66 struct sh_mobile_lcdc_sys_bus_ops *sys_ops,
67 unsigned short reg)
68{
69 unsigned long data;
70
71 sys_ops->write_index(sys_ops_handle, adjust_reg18(reg));
72 data = sys_ops->read_data(sys_ops_handle);
73 return ((data >> 1) & 0xff) | ((data >> 2) & 0xff00);
74}
75
76static void migor_lcd_qvga_seq(void *sys_ops_handle,
77 struct sh_mobile_lcdc_sys_bus_ops *sys_ops,
78 unsigned short const *data, int no_data)
79{
80 int i;
81
82 for (i = 0; i < no_data; i += 2)
83 write_reg16(sys_ops_handle, sys_ops, data[i], data[i + 1]);
84}
85
86static const unsigned short sync_data[] = {
87 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
88};
89
90static const unsigned short magic0_data[] = {
91 0x0060, 0x2700, 0x0008, 0x0808, 0x0090, 0x001A, 0x0007, 0x0001,
92 0x0017, 0x0001, 0x0019, 0x0000, 0x0010, 0x17B0, 0x0011, 0x0116,
93 0x0012, 0x0198, 0x0013, 0x1400, 0x0029, 0x000C, 0x0012, 0x01B8,
94};
95
96static const unsigned short magic1_data[] = {
97 0x0030, 0x0307, 0x0031, 0x0303, 0x0032, 0x0603, 0x0033, 0x0202,
98 0x0034, 0x0202, 0x0035, 0x0202, 0x0036, 0x1F1F, 0x0037, 0x0303,
99 0x0038, 0x0303, 0x0039, 0x0603, 0x003A, 0x0202, 0x003B, 0x0102,
100 0x003C, 0x0204, 0x003D, 0x0000, 0x0001, 0x0100, 0x0002, 0x0300,
101 0x0003, 0x5028, 0x0020, 0x00ef, 0x0021, 0x0000, 0x0004, 0x0000,
102 0x0009, 0x0000, 0x000A, 0x0008, 0x000C, 0x0000, 0x000D, 0x0000,
103 0x0015, 0x8000,
104};
105
106static const unsigned short magic2_data[] = {
107 0x0061, 0x0001, 0x0092, 0x0100, 0x0093, 0x0001, 0x0007, 0x0021,
108};
109
110static const unsigned short magic3_data[] = {
111 0x0010, 0x16B0, 0x0011, 0x0111, 0x0007, 0x0061,
112};
113
114int migor_lcd_qvga_setup(void *board_data, void *sohandle,
115 struct sh_mobile_lcdc_sys_bus_ops *so)
116{
117 unsigned long xres = 320;
118 unsigned long yres = 240;
119 int k;
120
121 reset_lcd_module();
122 migor_lcd_qvga_seq(sohandle, so, sync_data, ARRAY_SIZE(sync_data));
123
124 if (read_reg16(sohandle, so, 0) != 0x1505)
125 return -ENODEV;
126
127 pr_info("Migo-R QVGA LCD Module detected.\n");
128
129 migor_lcd_qvga_seq(sohandle, so, sync_data, ARRAY_SIZE(sync_data));
130 write_reg16(sohandle, so, 0x00A4, 0x0001);
131 mdelay(10);
132
133 migor_lcd_qvga_seq(sohandle, so, magic0_data, ARRAY_SIZE(magic0_data));
134 mdelay(100);
135
136 migor_lcd_qvga_seq(sohandle, so, magic1_data, ARRAY_SIZE(magic1_data));
137 write_reg16(sohandle, so, 0x0050, 0xef - (yres - 1));
138 write_reg16(sohandle, so, 0x0051, 0x00ef);
139 write_reg16(sohandle, so, 0x0052, 0x0000);
140 write_reg16(sohandle, so, 0x0053, xres - 1);
141
142 migor_lcd_qvga_seq(sohandle, so, magic2_data, ARRAY_SIZE(magic2_data));
143 mdelay(10);
144
145 migor_lcd_qvga_seq(sohandle, so, magic3_data, ARRAY_SIZE(magic3_data));
146 mdelay(40);
147
148 /* clear GRAM to avoid displaying garbage */
149
150 write_reg16(sohandle, so, 0x0020, 0x0000); /* horiz addr */
151 write_reg16(sohandle, so, 0x0021, 0x0000); /* vert addr */
152
153 for (k = 0; k < (xres * 256); k++) /* yes, 256 words per line */
154 write_reg16(sohandle, so, 0x0022, 0x0000);
155
156 write_reg16(sohandle, so, 0x0020, 0x0000); /* reset horiz addr */
157 write_reg16(sohandle, so, 0x0021, 0x0000); /* reset vert addr */
158 write_reg16(sohandle, so, 0x0007, 0x0173);
159 mdelay(40);
160
161 /* enable display */
162 write_reg(sohandle, so, 0x00, 0x22);
163 mdelay(100);
164 return 0;
165}
diff --git a/arch/sh/boards/renesas/migor/setup.c b/arch/sh/boards/renesas/migor/setup.c
index 963c99322095..7bd365ad2d06 100644
--- a/arch/sh/boards/renesas/migor/setup.c
+++ b/arch/sh/boards/renesas/migor/setup.c
@@ -15,9 +15,15 @@
15#include <linux/mtd/nand.h> 15#include <linux/mtd/nand.h>
16#include <linux/i2c.h> 16#include <linux/i2c.h>
17#include <linux/smc91x.h> 17#include <linux/smc91x.h>
18#include <linux/delay.h>
19#include <linux/clk.h>
20#include <media/soc_camera_platform.h>
21#include <media/sh_mobile_ceu.h>
22#include <asm/clock.h>
18#include <asm/machvec.h> 23#include <asm/machvec.h>
19#include <asm/io.h> 24#include <asm/io.h>
20#include <asm/sh_keysc.h> 25#include <asm/sh_keysc.h>
26#include <asm/sh_mobile_lcdc.h>
21#include <asm/migor.h> 27#include <asm/migor.h>
22 28
23/* Address IRQ Size Bus Description 29/* Address IRQ Size Bus Description
@@ -198,14 +204,237 @@ static struct platform_device migor_nand_flash_device = {
198 } 204 }
199}; 205};
200 206
207static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
208#ifdef CONFIG_SH_MIGOR_RTA_WVGA
209 .clock_source = LCDC_CLK_BUS,
210 .ch[0] = {
211 .chan = LCDC_CHAN_MAINLCD,
212 .bpp = 16,
213 .interface_type = RGB16,
214 .clock_divider = 2,
215 .lcd_cfg = {
216 .name = "LB070WV1",
217 .xres = 800,
218 .yres = 480,
219 .left_margin = 64,
220 .right_margin = 16,
221 .hsync_len = 120,
222 .upper_margin = 1,
223 .lower_margin = 17,
224 .vsync_len = 2,
225 .sync = 0,
226 },
227 }
228#endif
229#ifdef CONFIG_SH_MIGOR_QVGA
230 .clock_source = LCDC_CLK_PERIPHERAL,
231 .ch[0] = {
232 .chan = LCDC_CHAN_MAINLCD,
233 .bpp = 16,
234 .interface_type = SYS16A,
235 .clock_divider = 10,
236 .lcd_cfg = {
237 .name = "PH240320T",
238 .xres = 320,
239 .yres = 240,
240 .left_margin = 0,
241 .right_margin = 16,
242 .hsync_len = 8,
243 .upper_margin = 1,
244 .lower_margin = 17,
245 .vsync_len = 2,
246 .sync = FB_SYNC_HOR_HIGH_ACT,
247 },
248 .board_cfg = {
249 .setup_sys = migor_lcd_qvga_setup,
250 },
251 .sys_bus_cfg = {
252 .ldmt2r = 0x06000a09,
253 .ldmt3r = 0x180e3418,
254 },
255 }
256#endif
257};
258
259static struct resource migor_lcdc_resources[] = {
260 [0] = {
261 .name = "LCDC",
262 .start = 0xfe940000, /* P4-only space */
263 .end = 0xfe941fff,
264 .flags = IORESOURCE_MEM,
265 },
266};
267
268static struct platform_device migor_lcdc_device = {
269 .name = "sh_mobile_lcdc_fb",
270 .num_resources = ARRAY_SIZE(migor_lcdc_resources),
271 .resource = migor_lcdc_resources,
272 .dev = {
273 .platform_data = &sh_mobile_lcdc_info,
274 },
275};
276
277static struct clk *camera_clk;
278
279static void camera_power_on(void)
280{
281 unsigned char value;
282
283 camera_clk = clk_get(NULL, "video_clk");
284 clk_set_rate(camera_clk, 24000000);
285 clk_enable(camera_clk); /* start VIO_CKO */
286
287 mdelay(10);
288 value = ctrl_inb(PORT_PTDR);
289 value &= ~0x09;
290#ifndef CONFIG_SH_MIGOR_RTA_WVGA
291 value |= 0x01;
292#endif
293 ctrl_outb(value, PORT_PTDR);
294 mdelay(10);
295
296 ctrl_outb(value | 8, PORT_PTDR);
297}
298
299static void camera_power_off(void)
300{
301 clk_disable(camera_clk); /* stop VIO_CKO */
302 clk_put(camera_clk);
303
304 ctrl_outb(ctrl_inb(PORT_PTDR) & ~0x08, PORT_PTDR);
305}
306
307static unsigned char camera_ov772x_magic[] =
308{
309 0x09, 0x01, 0x0c, 0x10, 0x0d, 0x41, 0x0e, 0x01,
310 0x12, 0x00, 0x13, 0x8F, 0x14, 0x4A, 0x15, 0x00,
311 0x16, 0x00, 0x17, 0x23, 0x18, 0xa0, 0x19, 0x07,
312 0x1a, 0xf0, 0x1b, 0x40, 0x1f, 0x00, 0x20, 0x10,
313 0x22, 0xff, 0x23, 0x01, 0x28, 0x00, 0x29, 0xa0,
314 0x2a, 0x00, 0x2b, 0x00, 0x2c, 0xf0, 0x2d, 0x00,
315 0x2e, 0x00, 0x30, 0x80, 0x31, 0x60, 0x32, 0x00,
316 0x33, 0x00, 0x34, 0x00, 0x3d, 0x80, 0x3e, 0xe2,
317 0x3f, 0x1f, 0x42, 0x80, 0x43, 0x80, 0x44, 0x80,
318 0x45, 0x80, 0x46, 0x00, 0x47, 0x00, 0x48, 0x00,
319 0x49, 0x50, 0x4a, 0x30, 0x4b, 0x50, 0x4c, 0x50,
320 0x4d, 0x00, 0x4e, 0xef, 0x4f, 0x10, 0x50, 0x60,
321 0x51, 0x00, 0x52, 0x00, 0x53, 0x24, 0x54, 0x7a,
322 0x55, 0xfc, 0x62, 0xff, 0x63, 0xf0, 0x64, 0x1f,
323 0x65, 0x00, 0x66, 0x10, 0x67, 0x00, 0x68, 0x00,
324 0x69, 0x5c, 0x6a, 0x11, 0x6b, 0xa2, 0x6c, 0x01,
325 0x6d, 0x50, 0x6e, 0x80, 0x6f, 0x80, 0x70, 0x0f,
326 0x71, 0x00, 0x72, 0x00, 0x73, 0x0f, 0x74, 0x0f,
327 0x75, 0xff, 0x78, 0x10, 0x79, 0x70, 0x7a, 0x70,
328 0x7b, 0xf0, 0x7c, 0xf0, 0x7d, 0xf0, 0x7e, 0x0e,
329 0x7f, 0x1a, 0x80, 0x31, 0x81, 0x5a, 0x82, 0x69,
330 0x83, 0x75, 0x84, 0x7e, 0x85, 0x88, 0x86, 0x8f,
331 0x87, 0x96, 0x88, 0xa3, 0x89, 0xaf, 0x8a, 0xc4,
332 0x8b, 0xd7, 0x8c, 0xe8, 0x8d, 0x20, 0x8e, 0x00,
333 0x8f, 0x00, 0x90, 0x08, 0x91, 0x10, 0x92, 0x1f,
334 0x93, 0x01, 0x94, 0x2c, 0x95, 0x24, 0x96, 0x08,
335 0x97, 0x14, 0x98, 0x24, 0x99, 0x38, 0x9a, 0x9e,
336 0x9b, 0x00, 0x9c, 0x40, 0x9e, 0x11, 0x9f, 0x02,
337 0xa0, 0x00, 0xa1, 0x40, 0xa2, 0x40, 0xa3, 0x06,
338 0xa4, 0x00, 0xa6, 0x00, 0xa7, 0x40, 0xa8, 0x40,
339 0xa9, 0x80, 0xaa, 0x80, 0xab, 0x06, 0xac, 0xff,
340 0x12, 0x06, 0x64, 0x3f, 0x12, 0x46, 0x17, 0x3f,
341 0x18, 0x50, 0x19, 0x03, 0x1a, 0x78, 0x29, 0x50,
342 0x2c, 0x78,
343};
344
345static int ov772x_set_capture(struct soc_camera_platform_info *info,
346 int enable)
347{
348 struct i2c_adapter *a = i2c_get_adapter(0);
349 struct i2c_msg msg;
350 int ret = 0;
351 int i;
352
353 if (!enable)
354 return 0; /* camera_power_off() is enough */
355
356 for (i = 0; i < ARRAY_SIZE(camera_ov772x_magic); i += 2) {
357 u_int8_t buf[8];
358
359 msg.addr = 0x21;
360 msg.buf = buf;
361 msg.len = 2;
362 msg.flags = 0;
363
364 buf[0] = camera_ov772x_magic[i];
365 buf[1] = camera_ov772x_magic[i + 1];
366
367 ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
368 }
369
370 return ret;
371}
372
373static struct soc_camera_platform_info ov772x_info = {
374 .iface = 0,
375 .format_name = "RGB565",
376 .format_depth = 16,
377 .format = {
378 .pixelformat = V4L2_PIX_FMT_RGB565,
379 .colorspace = V4L2_COLORSPACE_SRGB,
380 .width = 320,
381 .height = 240,
382 },
383 .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
384 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
385 .set_capture = ov772x_set_capture,
386};
387
388static struct platform_device migor_camera_device = {
389 .name = "soc_camera_platform",
390 .dev = {
391 .platform_data = &ov772x_info,
392 },
393};
394
395static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
396 .flags = SOCAM_MASTER | SOCAM_DATAWIDTH_8 | SOCAM_PCLK_SAMPLE_RISING \
397 | SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_VSYNC_ACTIVE_HIGH,
398 .enable_camera = camera_power_on,
399 .disable_camera = camera_power_off,
400};
401
402static struct resource migor_ceu_resources[] = {
403 [0] = {
404 .name = "CEU",
405 .start = 0xfe910000,
406 .end = 0xfe91009f,
407 .flags = IORESOURCE_MEM,
408 },
409 [1] = {
410 .start = 52,
411 .flags = IORESOURCE_IRQ,
412 },
413 [2] = {
414 /* place holder for contiguous memory */
415 },
416};
417
418static struct platform_device migor_ceu_device = {
419 .name = "sh_mobile_ceu",
420 .num_resources = ARRAY_SIZE(migor_ceu_resources),
421 .resource = migor_ceu_resources,
422 .dev = {
423 .platform_data = &sh_mobile_ceu_info,
424 },
425};
426
201static struct platform_device *migor_devices[] __initdata = { 427static struct platform_device *migor_devices[] __initdata = {
202 &smc91x_eth_device, 428 &smc91x_eth_device,
203 &sh_keysc_device, 429 &sh_keysc_device,
430 &migor_lcdc_device,
431 &migor_ceu_device,
432 &migor_camera_device,
204 &migor_nor_flash_device, 433 &migor_nor_flash_device,
205 &migor_nand_flash_device, 434 &migor_nand_flash_device,
206}; 435};
207 436
208static struct i2c_board_info __initdata migor_i2c_devices[] = { 437static struct i2c_board_info migor_i2c_devices[] = {
209 { 438 {
210 I2C_BOARD_INFO("rs5c372b", 0x32), 439 I2C_BOARD_INFO("rs5c372b", 0x32),
211 }, 440 },
@@ -217,6 +446,12 @@ static struct i2c_board_info __initdata migor_i2c_devices[] = {
217 446
218static int __init migor_devices_setup(void) 447static int __init migor_devices_setup(void)
219{ 448{
449 clk_always_enable("mstp214"); /* KEYSC */
450 clk_always_enable("mstp200"); /* LCDC */
451 clk_always_enable("mstp203"); /* CEU */
452
453 platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
454
220 i2c_register_board_info(0, migor_i2c_devices, 455 i2c_register_board_info(0, migor_i2c_devices,
221 ARRAY_SIZE(migor_i2c_devices)); 456 ARRAY_SIZE(migor_i2c_devices));
222 457
@@ -235,20 +470,51 @@ static void __init migor_setup(char **cmdline_p)
235 ctrl_outw(ctrl_inw(PORT_PSELA) & ~0x4100, PORT_PSELA); 470 ctrl_outw(ctrl_inw(PORT_PSELA) & ~0x4100, PORT_PSELA);
236 ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA); 471 ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
237 ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC); 472 ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
238 ctrl_outl(ctrl_inl(MSTPCR2) & ~0x00004000, MSTPCR2);
239 473
240 /* NAND Flash */ 474 /* NAND Flash */
241 ctrl_outw(ctrl_inw(PORT_PXCR) & 0x0fff, PORT_PXCR); 475 ctrl_outw(ctrl_inw(PORT_PXCR) & 0x0fff, PORT_PXCR);
242 ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x00000600) | 0x00000200, 476 ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x00000600) | 0x00000200,
243 BSC_CS6ABCR); 477 BSC_CS6ABCR);
244 478
245 /* I2C */
246 ctrl_outl(ctrl_inl(MSTPCR1) & ~0x00000200, MSTPCR1);
247
248 /* Touch Panel - Enable IRQ6 */ 479 /* Touch Panel - Enable IRQ6 */
249 ctrl_outw(ctrl_inw(PORT_PZCR) & ~0xc, PORT_PZCR); 480 ctrl_outw(ctrl_inw(PORT_PZCR) & ~0xc, PORT_PZCR);
250 ctrl_outw((ctrl_inw(PORT_PSELA) | 0x8000), PORT_PSELA); 481 ctrl_outw((ctrl_inw(PORT_PSELA) | 0x8000), PORT_PSELA);
251 ctrl_outw((ctrl_inw(PORT_HIZCRC) & ~0x4000), PORT_HIZCRC); 482 ctrl_outw((ctrl_inw(PORT_HIZCRC) & ~0x4000), PORT_HIZCRC);
483
484#ifdef CONFIG_SH_MIGOR_RTA_WVGA
485 /* LCDC - WVGA - Enable RGB Interface signals */
486 ctrl_outw(ctrl_inw(PORT_PACR) & ~0x0003, PORT_PACR);
487 ctrl_outw(0x0000, PORT_PHCR);
488 ctrl_outw(0x0000, PORT_PLCR);
489 ctrl_outw(0x0000, PORT_PMCR);
490 ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x000f, PORT_PRCR);
491 ctrl_outw((ctrl_inw(PORT_PSELD) & ~0x000d) | 0x0400, PORT_PSELD);
492 ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0100, PORT_MSELCRB);
493 ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01e0, PORT_HIZCRA);
494#endif
495#ifdef CONFIG_SH_MIGOR_QVGA
496 /* LCDC - QVGA - Enable SYS Interface signals */
497 ctrl_outw(ctrl_inw(PORT_PACR) & ~0x0003, PORT_PACR);
498 ctrl_outw((ctrl_inw(PORT_PHCR) & ~0xcfff) | 0x0010, PORT_PHCR);
499 ctrl_outw(0x0000, PORT_PLCR);
500 ctrl_outw(0x0000, PORT_PMCR);
501 ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x030f, PORT_PRCR);
502 ctrl_outw((ctrl_inw(PORT_PSELD) & ~0x0001) | 0x0420, PORT_PSELD);
503 ctrl_outw(ctrl_inw(PORT_MSELCRB) | 0x0100, PORT_MSELCRB);
504 ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01e0, PORT_HIZCRA);
505#endif
506
507 /* CEU */
508 ctrl_outw((ctrl_inw(PORT_PTCR) & ~0x03c3) | 0x0051, PORT_PTCR);
509 ctrl_outw(ctrl_inw(PORT_PUCR) & ~0x03ff, PORT_PUCR);
510 ctrl_outw(ctrl_inw(PORT_PVCR) & ~0x03ff, PORT_PVCR);
511 ctrl_outw(ctrl_inw(PORT_PWCR) & ~0x3c00, PORT_PWCR);
512 ctrl_outw(ctrl_inw(PORT_PSELC) | 0x0001, PORT_PSELC);
513 ctrl_outw(ctrl_inw(PORT_PSELD) & ~0x2000, PORT_PSELD);
514 ctrl_outw(ctrl_inw(PORT_PSELE) | 0x000f, PORT_PSELE);
515 ctrl_outw(ctrl_inw(PORT_MSELCRB) | 0x2200, PORT_MSELCRB);
516 ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x0a00, PORT_HIZCRA);
517 ctrl_outw(ctrl_inw(PORT_HIZCRB) & ~0x0003, PORT_HIZCRB);
252} 518}
253 519
254static struct sh_machine_vector mv_migor __initmv = { 520static struct sh_machine_vector mv_migor __initmv = {
diff --git a/arch/sh/boards/renesas/rsk7203/Makefile b/arch/sh/boards/renesas/rsk7203/Makefile
new file mode 100644
index 000000000000..f663768429f0
--- /dev/null
+++ b/arch/sh/boards/renesas/rsk7203/Makefile
@@ -0,0 +1 @@
obj-y := setup.o
diff --git a/arch/sh/boards/renesas/rsk7203/setup.c b/arch/sh/boards/renesas/rsk7203/setup.c
new file mode 100644
index 000000000000..0bbda04b03b9
--- /dev/null
+++ b/arch/sh/boards/renesas/rsk7203/setup.c
@@ -0,0 +1,126 @@
1/*
2 * Renesas Technology Europe RSK+ 7203 Support.
3 *
4 * Copyright (C) 2008 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/types.h>
12#include <linux/platform_device.h>
13#include <linux/mtd/mtd.h>
14#include <linux/mtd/partitions.h>
15#include <linux/mtd/physmap.h>
16#include <linux/mtd/map.h>
17#include <asm/machvec.h>
18#include <asm/io.h>
19
20static struct resource smc911x_resources[] = {
21 [0] = {
22 .start = 0x24000000,
23 .end = 0x24000000 + 0x100,
24 .flags = IORESOURCE_MEM,
25 },
26 [1] = {
27 .start = 64,
28 .end = 64,
29 .flags = IORESOURCE_IRQ,
30 },
31};
32
33static struct platform_device smc911x_device = {
34 .name = "smc911x",
35 .id = -1,
36 .num_resources = ARRAY_SIZE(smc911x_resources),
37 .resource = smc911x_resources,
38};
39
40static const char *probes[] = { "cmdlinepart", NULL };
41
42static struct mtd_partition *parsed_partitions;
43
44static struct mtd_partition rsk7203_partitions[] = {
45 {
46 .name = "Bootloader",
47 .offset = 0x00000000,
48 .size = 0x00040000,
49 .mask_flags = MTD_WRITEABLE,
50 }, {
51 .name = "Kernel",
52 .offset = MTDPART_OFS_NXTBLK,
53 .size = 0x001c0000,
54 }, {
55 .name = "Flash_FS",
56 .offset = MTDPART_OFS_NXTBLK,
57 .size = MTDPART_SIZ_FULL,
58 }
59};
60
61static struct physmap_flash_data flash_data = {
62 .width = 2,
63};
64
65static struct resource flash_resource = {
66 .start = 0x20000000,
67 .end = 0x20400000,
68 .flags = IORESOURCE_MEM,
69};
70
71static struct platform_device flash_device = {
72 .name = "physmap-flash",
73 .id = -1,
74 .resource = &flash_resource,
75 .num_resources = 1,
76 .dev = {
77 .platform_data = &flash_data,
78 },
79};
80
81static struct mtd_info *flash_mtd;
82
83static struct map_info rsk7203_flash_map = {
84 .name = "RSK+ Flash",
85 .size = 0x400000,
86 .bankwidth = 2,
87};
88
89static void __init set_mtd_partitions(void)
90{
91 int nr_parts = 0;
92
93 simple_map_init(&rsk7203_flash_map);
94 flash_mtd = do_map_probe("cfi_probe", &rsk7203_flash_map);
95 nr_parts = parse_mtd_partitions(flash_mtd, probes,
96 &parsed_partitions, 0);
97 /* If there is no partition table, used the hard coded table */
98 if (nr_parts <= 0) {
99 flash_data.parts = rsk7203_partitions;
100 flash_data.nr_parts = ARRAY_SIZE(rsk7203_partitions);
101 } else {
102 flash_data.nr_parts = nr_parts;
103 flash_data.parts = parsed_partitions;
104 }
105}
106
107
108static struct platform_device *rsk7203_devices[] __initdata = {
109 &smc911x_device,
110 &flash_device,
111};
112
113static int __init rsk7203_devices_setup(void)
114{
115 set_mtd_partitions();
116 return platform_add_devices(rsk7203_devices,
117 ARRAY_SIZE(rsk7203_devices));
118}
119device_initcall(rsk7203_devices_setup);
120
121/*
122 * The Machine Vector
123 */
124static struct sh_machine_vector mv_rsk7203 __initmv = {
125 .mv_name = "RSK+7203",
126};
diff --git a/arch/sh/boards/renesas/sh7763rdp/Makefile b/arch/sh/boards/renesas/sh7763rdp/Makefile
new file mode 100644
index 000000000000..f6c0b55516d2
--- /dev/null
+++ b/arch/sh/boards/renesas/sh7763rdp/Makefile
@@ -0,0 +1 @@
obj-y := setup.o irq.o
diff --git a/arch/sh/boards/renesas/sh7763rdp/irq.c b/arch/sh/boards/renesas/sh7763rdp/irq.c
new file mode 100644
index 000000000000..fd850bad2dec
--- /dev/null
+++ b/arch/sh/boards/renesas/sh7763rdp/irq.c
@@ -0,0 +1,45 @@
1/*
2 * linux/arch/sh/boards/renesas/sh7763rdp/irq.c
3 *
4 * Renesas Solutions SH7763RDP Support.
5 *
6 * Copyright (C) 2008 Renesas Solutions Corp.
7 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14#include <linux/init.h>
15#include <linux/irq.h>
16#include <asm/io.h>
17#include <asm/irq.h>
18#include <asm/sh7763rdp.h>
19
20#define INTC_BASE (0xFFD00000)
21#define INTC_INT2PRI7 (INTC_BASE+0x4001C)
22#define INTC_INT2MSKCR (INTC_BASE+0x4003C)
23#define INTC_INT2MSKCR1 (INTC_BASE+0x400D4)
24
25/*
26 * Initialize IRQ setting
27 */
28void __init init_sh7763rdp_IRQ(void)
29{
30 /* GPIO enabled */
31 ctrl_outl(1 << 25, INTC_INT2MSKCR);
32
33 /* enable GPIO interrupts */
34 ctrl_outl((ctrl_inl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000,
35 INTC_INT2PRI7);
36
37 /* USBH enabled */
38 ctrl_outl(1 << 17, INTC_INT2MSKCR1);
39
40 /* GETHER enabled */
41 ctrl_outl(1 << 16, INTC_INT2MSKCR1);
42
43 /* DMAC enabled */
44 ctrl_outl(1 << 8, INTC_INT2MSKCR);
45}
diff --git a/arch/sh/boards/renesas/sh7763rdp/setup.c b/arch/sh/boards/renesas/sh7763rdp/setup.c
new file mode 100644
index 000000000000..925f16af7121
--- /dev/null
+++ b/arch/sh/boards/renesas/sh7763rdp/setup.c
@@ -0,0 +1,128 @@
1/*
2 * linux/arch/sh/boards/renesas/sh7763rdp/setup.c
3 *
4 * Renesas Solutions sh7763rdp board
5 *
6 * Copyright (C) 2008 Renesas Solutions Corp.
7 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/interrupt.h>
16#include <linux/input.h>
17#include <linux/mtd/physmap.h>
18#include <asm/io.h>
19#include <asm/sh7763rdp.h>
20
21/* NOR Flash */
22static struct mtd_partition sh7763rdp_nor_flash_partitions[] = {
23 {
24 .name = "U-Boot",
25 .offset = 0,
26 .size = (2 * 128 * 1024),
27 .mask_flags = MTD_WRITEABLE, /* Read-only */
28 }, {
29 .name = "Linux-Kernel",
30 .offset = MTDPART_OFS_APPEND,
31 .size = (20 * 128 * 1024),
32 }, {
33 .name = "Root Filesystem",
34 .offset = MTDPART_OFS_APPEND,
35 .size = MTDPART_SIZ_FULL,
36 },
37};
38
39static struct physmap_flash_data sh7763rdp_nor_flash_data = {
40 .width = 2,
41 .parts = sh7763rdp_nor_flash_partitions,
42 .nr_parts = ARRAY_SIZE(sh7763rdp_nor_flash_partitions),
43};
44
45static struct resource sh7763rdp_nor_flash_resources[] = {
46 [0] = {
47 .name = "NOR Flash",
48 .start = 0,
49 .end = (64 * 1024 * 1024),
50 .flags = IORESOURCE_MEM,
51 },
52};
53
54static struct platform_device sh7763rdp_nor_flash_device = {
55 .name = "physmap-flash",
56 .resource = sh7763rdp_nor_flash_resources,
57 .num_resources = ARRAY_SIZE(sh7763rdp_nor_flash_resources),
58 .dev = {
59 .platform_data = &sh7763rdp_nor_flash_data,
60 },
61};
62
63static struct platform_device *sh7763rdp_devices[] __initdata = {
64 &sh7763rdp_nor_flash_device,
65};
66
67static int __init sh7763rdp_devices_setup(void)
68{
69 return platform_add_devices(sh7763rdp_devices,
70 ARRAY_SIZE(sh7763rdp_devices));
71}
72__initcall(sh7763rdp_devices_setup);
73
74static void __init sh7763rdp_setup(char **cmdline_p)
75{
76 /* Board version check */
77 if (ctrl_inw(CPLD_BOARD_ID_ERV_REG) == 0xECB1)
78 printk(KERN_INFO "RTE Standard Configuration\n");
79 else
80 printk(KERN_INFO "RTA Standard Configuration\n");
81
82 /* USB pin select bits (clear bit 5-2 to 0) */
83 ctrl_outw((ctrl_inw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2);
84 /* USBH setup port I controls to other (clear bits 4-9 to 0) */
85 ctrl_outw(ctrl_inw(PORT_PICR) & 0xFC0F, PORT_PICR);
86
87 /* Select USB Host controller */
88 ctrl_outw(0x00, USB_USBHSC);
89
90 /* For LCD */
91 /* set PTJ7-1, bits 15-2 of PJCR to 0 */
92 ctrl_outw(ctrl_inw(PORT_PJCR) & 0x0003, PORT_PJCR);
93 /* set PTI5, bits 11-10 of PICR to 0 */
94 ctrl_outw(ctrl_inw(PORT_PICR) & 0xF3FF, PORT_PICR);
95 ctrl_outw(0, PORT_PKCR);
96 ctrl_outw(0, PORT_PLCR);
97 /* set PSEL2 bits 14-8, 5-4, of PSEL2 to 0 */
98 ctrl_outw((ctrl_inw(PORT_PSEL2) & 0x00C0), PORT_PSEL2);
99 /* set PSEL3 bits 14-12, 6-4, 2-0 of PSEL3 to 0 */
100 ctrl_outw((ctrl_inw(PORT_PSEL3) & 0x0700), PORT_PSEL3);
101
102 /* For HAC */
103 /* bit3-0 0100:HAC & SSI1 enable */
104 ctrl_outw((ctrl_inw(PORT_PSEL1) & 0xFFF0) | 0x0004, PORT_PSEL1);
105 /* bit14 1:SSI_HAC_CLK enable */
106 ctrl_outw(ctrl_inw(PORT_PSEL4) | 0x4000, PORT_PSEL4);
107
108 /* SH-Ether */
109 ctrl_outw((ctrl_inw(PORT_PSEL1) & ~0xff00) | 0x2400, PORT_PSEL1);
110 ctrl_outw(0x0, PORT_PFCR);
111 ctrl_outw(0x0, PORT_PFCR);
112 ctrl_outw(0x0, PORT_PFCR);
113
114 /* MMC */
115 /*selects SCIF and MMC other functions */
116 ctrl_outw(0x0001, PORT_PSEL0);
117 /* MMC clock operates */
118 ctrl_outl(ctrl_inl(MSTPCR1) & ~0x8, MSTPCR1);
119 ctrl_outw(ctrl_inw(PORT_PACR) & ~0x3000, PORT_PACR);
120 ctrl_outw(ctrl_inw(PORT_PCCR) & ~0xCFC3, PORT_PCCR);
121}
122
123static struct sh_machine_vector mv_sh7763rdp __initmv = {
124 .mv_name = "sh7763drp",
125 .mv_setup = sh7763rdp_setup,
126 .mv_nr_irqs = 112,
127 .mv_init_irq = init_sh7763rdp_IRQ,
128};
diff --git a/arch/sh/boards/renesas/sh7785lcr/Makefile b/arch/sh/boards/renesas/sh7785lcr/Makefile
new file mode 100644
index 000000000000..77037567633b
--- /dev/null
+++ b/arch/sh/boards/renesas/sh7785lcr/Makefile
@@ -0,0 +1 @@
obj-y := setup.o
diff --git a/arch/sh/boards/renesas/sh7785lcr/setup.c b/arch/sh/boards/renesas/sh7785lcr/setup.c
new file mode 100644
index 000000000000..b95d674ee704
--- /dev/null
+++ b/arch/sh/boards/renesas/sh7785lcr/setup.c
@@ -0,0 +1,302 @@
1/*
2 * Renesas Technology Corp. R0P7785LC0011RL Support.
3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/init.h>
12#include <linux/platform_device.h>
13#include <linux/sm501.h>
14#include <linux/sm501-regs.h>
15#include <linux/fb.h>
16#include <linux/mtd/physmap.h>
17#include <linux/delay.h>
18#include <linux/i2c.h>
19#include <linux/i2c-pca-platform.h>
20#include <linux/i2c-algo-pca.h>
21#include <asm/heartbeat.h>
22#include <asm/sh7785lcr.h>
23
24/*
25 * NOTE: This board has 2 physical memory maps.
26 * Please look at include/asm-sh/sh7785lcr.h or hardware manual.
27 */
28static struct resource heartbeat_resources[] = {
29 [0] = {
30 .start = PLD_LEDCR,
31 .end = PLD_LEDCR,
32 .flags = IORESOURCE_MEM,
33 },
34};
35
36static struct heartbeat_data heartbeat_data = {
37 .regsize = 8,
38};
39
40static struct platform_device heartbeat_device = {
41 .name = "heartbeat",
42 .id = -1,
43 .dev = {
44 .platform_data = &heartbeat_data,
45 },
46 .num_resources = ARRAY_SIZE(heartbeat_resources),
47 .resource = heartbeat_resources,
48};
49
50static struct mtd_partition nor_flash_partitions[] = {
51 {
52 .name = "loader",
53 .offset = 0x00000000,
54 .size = 512 * 1024,
55 },
56 {
57 .name = "bootenv",
58 .offset = MTDPART_OFS_APPEND,
59 .size = 512 * 1024,
60 },
61 {
62 .name = "kernel",
63 .offset = MTDPART_OFS_APPEND,
64 .size = 4 * 1024 * 1024,
65 },
66 {
67 .name = "data",
68 .offset = MTDPART_OFS_APPEND,
69 .size = MTDPART_SIZ_FULL,
70 },
71};
72
73static struct physmap_flash_data nor_flash_data = {
74 .width = 4,
75 .parts = nor_flash_partitions,
76 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
77};
78
79static struct resource nor_flash_resources[] = {
80 [0] = {
81 .start = NOR_FLASH_ADDR,
82 .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
83 .flags = IORESOURCE_MEM,
84 }
85};
86
87static struct platform_device nor_flash_device = {
88 .name = "physmap-flash",
89 .dev = {
90 .platform_data = &nor_flash_data,
91 },
92 .num_resources = ARRAY_SIZE(nor_flash_resources),
93 .resource = nor_flash_resources,
94};
95
96static struct resource r8a66597_usb_host_resources[] = {
97 [0] = {
98 .name = "r8a66597_hcd",
99 .start = R8A66597_ADDR,
100 .end = R8A66597_ADDR + R8A66597_SIZE - 1,
101 .flags = IORESOURCE_MEM,
102 },
103 [1] = {
104 .name = "r8a66597_hcd",
105 .start = 2,
106 .end = 2,
107 .flags = IORESOURCE_IRQ,
108 },
109};
110
111static struct platform_device r8a66597_usb_host_device = {
112 .name = "r8a66597_hcd",
113 .id = -1,
114 .dev = {
115 .dma_mask = NULL,
116 .coherent_dma_mask = 0xffffffff,
117 },
118 .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
119 .resource = r8a66597_usb_host_resources,
120};
121
122static struct resource sm501_resources[] = {
123 [0] = {
124 .start = SM107_MEM_ADDR,
125 .end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1,
126 .flags = IORESOURCE_MEM,
127 },
128 [1] = {
129 .start = SM107_REG_ADDR,
130 .end = SM107_REG_ADDR + SM107_REG_SIZE - 1,
131 .flags = IORESOURCE_MEM,
132 },
133 [2] = {
134 .start = 10,
135 .flags = IORESOURCE_IRQ,
136 },
137};
138
139static struct fb_videomode sm501_default_mode_crt = {
140 .pixclock = 35714, /* 28MHz */
141 .xres = 640,
142 .yres = 480,
143 .left_margin = 105,
144 .right_margin = 16,
145 .upper_margin = 33,
146 .lower_margin = 10,
147 .hsync_len = 39,
148 .vsync_len = 2,
149 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
150};
151
152static struct fb_videomode sm501_default_mode_pnl = {
153 .pixclock = 40000, /* 25MHz */
154 .xres = 640,
155 .yres = 480,
156 .left_margin = 2,
157 .right_margin = 16,
158 .upper_margin = 33,
159 .lower_margin = 10,
160 .hsync_len = 39,
161 .vsync_len = 2,
162 .sync = 0,
163};
164
165static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = {
166 .def_bpp = 16,
167 .def_mode = &sm501_default_mode_pnl,
168 .flags = SM501FB_FLAG_USE_INIT_MODE |
169 SM501FB_FLAG_USE_HWCURSOR |
170 SM501FB_FLAG_USE_HWACCEL |
171 SM501FB_FLAG_DISABLE_AT_EXIT |
172 SM501FB_FLAG_PANEL_NO_VBIASEN,
173};
174
175static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = {
176 .def_bpp = 16,
177 .def_mode = &sm501_default_mode_crt,
178 .flags = SM501FB_FLAG_USE_INIT_MODE |
179 SM501FB_FLAG_USE_HWCURSOR |
180 SM501FB_FLAG_USE_HWACCEL |
181 SM501FB_FLAG_DISABLE_AT_EXIT,
182};
183
184static struct sm501_platdata_fb sm501_fb_pdata = {
185 .fb_route = SM501_FB_OWN,
186 .fb_crt = &sm501_pdata_fbsub_crt,
187 .fb_pnl = &sm501_pdata_fbsub_pnl,
188};
189
190static struct sm501_initdata sm501_initdata = {
191 .gpio_high = {
192 .set = 0x00001fe0,
193 .mask = 0x0,
194 },
195 .devices = 0,
196 .mclk = 84 * 1000000,
197 .m1xclk = 112 * 1000000,
198};
199
200static struct sm501_platdata sm501_platform_data = {
201 .init = &sm501_initdata,
202 .fb = &sm501_fb_pdata,
203};
204
205static struct platform_device sm501_device = {
206 .name = "sm501",
207 .id = -1,
208 .dev = {
209 .platform_data = &sm501_platform_data,
210 },
211 .num_resources = ARRAY_SIZE(sm501_resources),
212 .resource = sm501_resources,
213};
214
215static struct resource i2c_resources[] = {
216 [0] = {
217 .start = PCA9564_ADDR,
218 .end = PCA9564_ADDR + PCA9564_SIZE - 1,
219 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
220 },
221 [1] = {
222 .start = 12,
223 .end = 12,
224 .flags = IORESOURCE_IRQ,
225 },
226};
227
228static struct i2c_pca9564_pf_platform_data i2c_platform_data = {
229 .gpio = 0,
230 .i2c_clock_speed = I2C_PCA_CON_330kHz,
231 .timeout = 100,
232};
233
234static struct platform_device i2c_device = {
235 .name = "i2c-pca-platform",
236 .id = -1,
237 .dev = {
238 .platform_data = &i2c_platform_data,
239 },
240 .num_resources = ARRAY_SIZE(i2c_resources),
241 .resource = i2c_resources,
242};
243
244static struct platform_device *sh7785lcr_devices[] __initdata = {
245 &heartbeat_device,
246 &nor_flash_device,
247 &r8a66597_usb_host_device,
248 &sm501_device,
249 &i2c_device,
250};
251
252static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = {
253 {
254 I2C_BOARD_INFO("r2025sd", 0x32),
255 },
256};
257
258static int __init sh7785lcr_devices_setup(void)
259{
260 i2c_register_board_info(0, sh7785lcr_i2c_devices,
261 ARRAY_SIZE(sh7785lcr_i2c_devices));
262
263 return platform_add_devices(sh7785lcr_devices,
264 ARRAY_SIZE(sh7785lcr_devices));
265}
266__initcall(sh7785lcr_devices_setup);
267
268/* Initialize IRQ setting */
269void __init init_sh7785lcr_IRQ(void)
270{
271 plat_irq_setup_pins(IRQ_MODE_IRQ7654);
272 plat_irq_setup_pins(IRQ_MODE_IRQ3210);
273}
274
275static void sh7785lcr_power_off(void)
276{
277 ctrl_outb(0x01, P2SEGADDR(PLD_POFCR));
278}
279
280/* Initialize the board */
281static void __init sh7785lcr_setup(char **cmdline_p)
282{
283 void __iomem *sm501_reg;
284
285 printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n");
286
287 pm_power_off = sh7785lcr_power_off;
288
289 /* sm501 DRAM configuration */
290 sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL;
291 writel(0x000307c2, sm501_reg);
292}
293
294/*
295 * The Machine Vector
296 */
297static struct sh_machine_vector mv_sh7785lcr __initmv = {
298 .mv_name = "SH7785LCR",
299 .mv_setup = sh7785lcr_setup,
300 .mv_init_irq = init_sh7785lcr_IRQ,
301};
302
diff --git a/arch/sh/boards/se/7343/irq.c b/arch/sh/boards/se/7343/irq.c
index 763f6deba814..1112e86aa93a 100644
--- a/arch/sh/boards/se/7343/irq.c
+++ b/arch/sh/boards/se/7343/irq.c
@@ -1,202 +1,80 @@
1/* 1/*
2 * arch/sh/boards/se/7343/irq.c 2 * linux/arch/sh/boards/se/7343/irq.c
3 * 3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda
5 *
6 * Based on linux/arch/sh/boards/se/7722/irq.c
7 * Copyright (C) 2007 Nobuhiro Iwamatsu
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
4 */ 12 */
5#include <linux/init.h> 13#include <linux/init.h>
6#include <linux/interrupt.h>
7#include <linux/irq.h> 14#include <linux/irq.h>
15#include <linux/interrupt.h>
8#include <asm/irq.h> 16#include <asm/irq.h>
9#include <asm/io.h> 17#include <asm/io.h>
10#include <asm/mach/se7343.h> 18#include <asm/se7343.h>
11 19
12static void 20static void disable_se7343_irq(unsigned int irq)
13disable_intreq_irq(unsigned int irq)
14{ 21{
15 int bit = irq - OFFCHIP_IRQ_BASE; 22 unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
16 u16 val; 23 ctrl_outw(ctrl_inw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
17
18 val = ctrl_inw(PA_CPLD_IMSK);
19 val |= 1 << bit;
20 ctrl_outw(val, PA_CPLD_IMSK);
21} 24}
22 25
23static void 26static void enable_se7343_irq(unsigned int irq)
24enable_intreq_irq(unsigned int irq)
25{ 27{
26 int bit = irq - OFFCHIP_IRQ_BASE; 28 unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
27 u16 val; 29 ctrl_outw(ctrl_inw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
28
29 val = ctrl_inw(PA_CPLD_IMSK);
30 val &= ~(1 << bit);
31 ctrl_outw(val, PA_CPLD_IMSK);
32} 30}
33 31
34static void 32static struct irq_chip se7343_irq_chip __read_mostly = {
35mask_and_ack_intreq_irq(unsigned int irq) 33 .name = "SE7343-FPGA",
36{ 34 .mask = disable_se7343_irq,
37 disable_intreq_irq(irq); 35 .unmask = enable_se7343_irq,
38} 36 .mask_ack = disable_se7343_irq,
39
40static unsigned int
41startup_intreq_irq(unsigned int irq)
42{
43 enable_intreq_irq(irq);
44 return 0;
45}
46
47static void
48shutdown_intreq_irq(unsigned int irq)
49{
50 disable_intreq_irq(irq);
51}
52
53static void
54end_intreq_irq(unsigned int irq)
55{
56 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
57 enable_intreq_irq(irq);
58}
59
60static struct hw_interrupt_type intreq_irq_type = {
61 .typename = "FPGA-IRQ",
62 .startup = startup_intreq_irq,
63 .shutdown = shutdown_intreq_irq,
64 .enable = enable_intreq_irq,
65 .disable = disable_intreq_irq,
66 .ack = mask_and_ack_intreq_irq,
67 .end = end_intreq_irq
68}; 37};
69 38
70static void 39static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
71make_intreq_irq(unsigned int irq)
72{
73 disable_irq_nosync(irq);
74 irq_desc[irq].chip = &intreq_irq_type;
75 disable_intreq_irq(irq);
76}
77
78int
79shmse_irq_demux(int irq)
80{ 40{
81 int bit; 41 unsigned short intv = ctrl_inw(PA_CPLD_ST);
82 volatile u16 val; 42 struct irq_desc *ext_desc;
83 43 unsigned int ext_irq = SE7343_FPGA_IRQ_BASE;
84 if (irq == IRQ5_IRQ) { 44
85 /* Read status Register */ 45 intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
86 val = ctrl_inw(PA_CPLD_ST); 46
87 bit = ffs(val); 47 while (intv) {
88 if (bit != 0) 48 if (intv & 1) {
89 return OFFCHIP_IRQ_BASE + bit - 1; 49 ext_desc = irq_desc + ext_irq;
50 handle_level_irq(ext_irq, ext_desc);
51 }
52 intv >>= 1;
53 ext_irq++;
90 } 54 }
91 return irq;
92} 55}
93 56
94/* IRQ5 is multiplexed between the following sources:
95 * 1. PC Card socket
96 * 2. Extension slot
97 * 3. USB Controller
98 * 4. Serial Controller
99 *
100 * We configure IRQ5 as a cascade IRQ.
101 */
102static struct irqaction irq5 = {
103 .handler = no_action,
104 .mask = CPU_MASK_NONE,
105 .name = "IRQ5-cascade",
106};
107
108static struct ipr_data se7343_irq5_ipr_map[] = {
109 { IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY },
110};
111static struct ipr_data se7343_siof0_vpu_ipr_map[] = {
112 { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
113 { VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 },
114};
115static struct ipr_data se7343_other_ipr_map[] = {
116 { DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
117 { DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
118 { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
119 { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
120 { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
121 { DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
122
123 /* I2C block */
124 { IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
125 { IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
126 { IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
127 { IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
128
129 { IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
130 { IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
131 { IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
132 { IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
133
134 /* SIOF */
135 { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
136
137 /* SIU */
138 { SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY },
139
140 /* VIO interrupt */
141 { CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
142 { BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
143 { VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
144
145 /*MFI interrupt*/
146
147 { MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY },
148
149 /* LCD controller */
150 { LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY },
151};
152
153/* 57/*
154 * Initialize IRQ setting 58 * Initialize IRQ setting
155 */ 59 */
156void __init 60void __init init_7343se_IRQ(void)
157init_7343se_IRQ(void)
158{ 61{
159 /* Setup Multiplexed interrupts */ 62 int i;
160 ctrl_outw(8, PA_CPLD_MODESET); /* Set all CPLD interrupts to active 63
161 * low. 64 ctrl_outw(0, PA_CPLD_IMSK); /* disable all irqs */
162 */ 65 ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */
163 /* Mask all CPLD controller interrupts */ 66
164 ctrl_outw(0x0fff, PA_CPLD_IMSK); 67 for (i = 0; i < SE7343_FPGA_IRQ_NR; i++)
165 68 set_irq_chip_and_handler_name(SE7343_FPGA_IRQ_BASE + i,
166 /* PC Card interrupts */ 69 &se7343_irq_chip,
167 make_intreq_irq(PC_IRQ0); 70 handle_level_irq, "level");
168 make_intreq_irq(PC_IRQ1); 71
169 make_intreq_irq(PC_IRQ2); 72 set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
170 make_intreq_irq(PC_IRQ3); 73 set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
171 74 set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);
172 /* Extension Slot Interrupts */ 75 set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
173 make_intreq_irq(EXT_IRQ0); 76 set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux);
174 make_intreq_irq(EXT_IRQ1); 77 set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
175 make_intreq_irq(EXT_IRQ2); 78 set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux);
176 make_intreq_irq(EXT_IRQ3); 79 set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
177
178 /* USB Controller interrupts */
179 make_intreq_irq(USB_IRQ0);
180 make_intreq_irq(USB_IRQ1);
181
182 /* Serial Controller interrupts */
183 make_intreq_irq(UART_IRQ0);
184 make_intreq_irq(UART_IRQ1);
185
186 /* Setup all external interrupts to be active low */
187 ctrl_outw(0xaaaa, INTC_ICR1);
188
189 make_ipr_irq(se7343_irq5_ipr_map, ARRAY_SIZE(se7343_irq5_ipr_map));
190
191 setup_irq(IRQ5_IRQ, &irq5);
192 /* Set port control to use IRQ5 */
193 *(u16 *)0xA4050108 &= ~0xc;
194
195 make_ipr_irq(se7343_siof0_vpu_ipr_map, ARRAY_SIZE(se7343_siof0_vpu_ipr_map));
196
197 ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */
198
199 make_ipr_irq(se7343_other_ipr_map, ARRAY_SIZE(se7343_other_ipr_map));
200
201 ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */
202} 80}
diff --git a/arch/sh/boards/se/7343/setup.c b/arch/sh/boards/se/7343/setup.c
index c9431b3a051b..8ae718d6c710 100644
--- a/arch/sh/boards/se/7343/setup.c
+++ b/arch/sh/boards/se/7343/setup.c
@@ -1,10 +1,11 @@
1#include <linux/init.h> 1#include <linux/init.h>
2#include <linux/platform_device.h> 2#include <linux/platform_device.h>
3#include <linux/mtd/physmap.h>
3#include <asm/machvec.h> 4#include <asm/machvec.h>
4#include <asm/mach/se7343.h> 5#include <asm/mach/se7343.h>
6#include <asm/heartbeat.h>
5#include <asm/irq.h> 7#include <asm/irq.h>
6 8#include <asm/io.h>
7void init_7343se_IRQ(void);
8 9
9static struct resource smc91x_resources[] = { 10static struct resource smc91x_resources[] = {
10 [0] = { 11 [0] = {
@@ -17,8 +18,8 @@ static struct resource smc91x_resources[] = {
17 * shared with other devices via externel 18 * shared with other devices via externel
18 * interrupt controller in FPGA... 19 * interrupt controller in FPGA...
19 */ 20 */
20 .start = EXT_IRQ2, 21 .start = SMC_IRQ,
21 .end = EXT_IRQ2, 22 .end = SMC_IRQ,
22 .flags = IORESOURCE_IRQ, 23 .flags = IORESOURCE_IRQ,
23 }, 24 },
24}; 25};
@@ -38,16 +39,65 @@ static struct resource heartbeat_resources[] = {
38 }, 39 },
39}; 40};
40 41
42static struct heartbeat_data heartbeat_data = {
43 .regsize = 16,
44};
45
41static struct platform_device heartbeat_device = { 46static struct platform_device heartbeat_device = {
42 .name = "heartbeat", 47 .name = "heartbeat",
43 .id = -1, 48 .id = -1,
49 .dev = {
50 .platform_data = &heartbeat_data,
51 },
44 .num_resources = ARRAY_SIZE(heartbeat_resources), 52 .num_resources = ARRAY_SIZE(heartbeat_resources),
45 .resource = heartbeat_resources, 53 .resource = heartbeat_resources,
46}; 54};
47 55
56static struct mtd_partition nor_flash_partitions[] = {
57 {
58 .name = "loader",
59 .offset = 0x00000000,
60 .size = 128 * 1024,
61 },
62 {
63 .name = "rootfs",
64 .offset = MTDPART_OFS_APPEND,
65 .size = 31 * 1024 * 1024,
66 },
67 {
68 .name = "data",
69 .offset = MTDPART_OFS_APPEND,
70 .size = MTDPART_SIZ_FULL,
71 },
72};
73
74static struct physmap_flash_data nor_flash_data = {
75 .width = 2,
76 .parts = nor_flash_partitions,
77 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
78};
79
80static struct resource nor_flash_resources[] = {
81 [0] = {
82 .start = 0x00000000,
83 .end = 0x01ffffff,
84 .flags = IORESOURCE_MEM,
85 }
86};
87
88static struct platform_device nor_flash_device = {
89 .name = "physmap-flash",
90 .dev = {
91 .platform_data = &nor_flash_data,
92 },
93 .num_resources = ARRAY_SIZE(nor_flash_resources),
94 .resource = nor_flash_resources,
95};
96
48static struct platform_device *sh7343se_platform_devices[] __initdata = { 97static struct platform_device *sh7343se_platform_devices[] __initdata = {
49 &smc91x_device, 98 &smc91x_device,
50 &heartbeat_device, 99 &heartbeat_device,
100 &nor_flash_device,
51}; 101};
52 102
53static int __init sh7343se_devices_setup(void) 103static int __init sh7343se_devices_setup(void)
@@ -55,10 +105,19 @@ static int __init sh7343se_devices_setup(void)
55 return platform_add_devices(sh7343se_platform_devices, 105 return platform_add_devices(sh7343se_platform_devices,
56 ARRAY_SIZE(sh7343se_platform_devices)); 106 ARRAY_SIZE(sh7343se_platform_devices));
57} 107}
108device_initcall(sh7343se_devices_setup);
58 109
110/*
111 * Initialize the board
112 */
59static void __init sh7343se_setup(char **cmdline_p) 113static void __init sh7343se_setup(char **cmdline_p)
60{ 114{
61 device_initcall(sh7343se_devices_setup); 115 ctrl_outw(0xf900, FPGA_OUT); /* FPGA */
116
117 ctrl_outw(0x0002, PORT_PECR); /* PORT E 1 = IRQ5 */
118 ctrl_outw(0x0020, PORT_PSELD);
119
120 printk(KERN_INFO "MS7343CP01 Setup...done\n");
62} 121}
63 122
64/* 123/*
@@ -90,5 +149,4 @@ static struct sh_machine_vector mv_7343se __initmv = {
90 .mv_outsl = sh7343se_outsl, 149 .mv_outsl = sh7343se_outsl,
91 150
92 .mv_init_irq = init_7343se_IRQ, 151 .mv_init_irq = init_7343se_IRQ,
93 .mv_irq_demux = shmse_irq_demux,
94}; 152};
diff --git a/arch/sh/boards/se/770x/io.c b/arch/sh/boards/se/770x/io.c
index c4550473d4c3..b1ec085b8673 100644
--- a/arch/sh/boards/se/770x/io.c
+++ b/arch/sh/boards/se/770x/io.c
@@ -1,25 +1,13 @@
1/* $Id: io.c,v 1.7 2006/02/05 21:55:29 lethal Exp $ 1/*
2 *
3 * linux/arch/sh/kernel/io_se.c
4 *
5 * Copyright (C) 2000 Kazumoto Kojima 2 * Copyright (C) 2000 Kazumoto Kojima
6 * 3 *
7 * I/O routine for Hitachi SolutionEngine. 4 * I/O routine for Hitachi SolutionEngine.
8 *
9 */ 5 */
10
11#include <linux/kernel.h> 6#include <linux/kernel.h>
12#include <linux/types.h> 7#include <linux/types.h>
13#include <asm/io.h> 8#include <asm/io.h>
14#include <asm/se.h> 9#include <asm/se.h>
15 10
16/* SH pcmcia io window base, start and end. */
17int sh_pcic_io_wbase = 0xb8400000;
18int sh_pcic_io_start;
19int sh_pcic_io_stop;
20int sh_pcic_io_type;
21int sh_pcic_io_dummy;
22
23/* MS7750 requires special versions of in*, out* routines, since 11/* MS7750 requires special versions of in*, out* routines, since
24 PC-like io ports are located at upper half byte of 16-bit word which 12 PC-like io ports are located at upper half byte of 16-bit word which
25 can be accessed only with 16-bit wide. */ 13 can be accessed only with 16-bit wide. */
@@ -33,8 +21,6 @@ port2adr(unsigned int port)
33 return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000)); 21 return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
34 else if (port >= 0x1000) 22 else if (port >= 0x1000)
35 return (volatile __u16 *) (PA_83902 + (port << 1)); 23 return (volatile __u16 *) (PA_83902 + (port << 1));
36 else if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
37 return (volatile __u16 *) (sh_pcic_io_wbase + (port &~ 1));
38 else 24 else
39 return (volatile __u16 *) (PA_SUPERIO + (port << 1)); 25 return (volatile __u16 *) (PA_SUPERIO + (port << 1));
40} 26}
@@ -51,32 +37,27 @@ shifted_port(unsigned long port)
51 37
52unsigned char se_inb(unsigned long port) 38unsigned char se_inb(unsigned long port)
53{ 39{
54 if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) 40 if (shifted_port(port))
55 return *(__u8 *) (sh_pcic_io_wbase + 0x40000 + port); 41 return (*port2adr(port) >> 8);
56 else if (shifted_port(port))
57 return (*port2adr(port) >> 8);
58 else 42 else
59 return (*port2adr(port))&0xff; 43 return (*port2adr(port))&0xff;
60} 44}
61 45
62unsigned char se_inb_p(unsigned long port) 46unsigned char se_inb_p(unsigned long port)
63{ 47{
64 unsigned long v; 48 unsigned long v;
65 49
66 if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) 50 if (shifted_port(port))
67 v = *(__u8 *) (sh_pcic_io_wbase + 0x40000 + port); 51 v = (*port2adr(port) >> 8);
68 else if (shifted_port(port))
69 v = (*port2adr(port) >> 8);
70 else 52 else
71 v = (*port2adr(port))&0xff; 53 v = (*port2adr(port))&0xff;
72 ctrl_delay(); 54 ctrl_delay();
73 return v; 55 return v;
74} 56}
75 57
76unsigned short se_inw(unsigned long port) 58unsigned short se_inw(unsigned long port)
77{ 59{
78 if (port >= 0x2000 || 60 if (port >= 0x2000)
79 (sh_pcic_io_start <= port && port <= sh_pcic_io_stop))
80 return *port2adr(port); 61 return *port2adr(port);
81 else 62 else
82 maybebadio(port); 63 maybebadio(port);
@@ -91,9 +72,7 @@ unsigned int se_inl(unsigned long port)
91 72
92void se_outb(unsigned char value, unsigned long port) 73void se_outb(unsigned char value, unsigned long port)
93{ 74{
94 if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) 75 if (shifted_port(port))
95 *(__u8 *)(sh_pcic_io_wbase + port) = value;
96 else if (shifted_port(port))
97 *(port2adr(port)) = value << 8; 76 *(port2adr(port)) = value << 8;
98 else 77 else
99 *(port2adr(port)) = value; 78 *(port2adr(port)) = value;
@@ -101,9 +80,7 @@ void se_outb(unsigned char value, unsigned long port)
101 80
102void se_outb_p(unsigned char value, unsigned long port) 81void se_outb_p(unsigned char value, unsigned long port)
103{ 82{
104 if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) 83 if (shifted_port(port))
105 *(__u8 *)(sh_pcic_io_wbase + port) = value;
106 else if (shifted_port(port))
107 *(port2adr(port)) = value << 8; 84 *(port2adr(port)) = value << 8;
108 else 85 else
109 *(port2adr(port)) = value; 86 *(port2adr(port)) = value;
@@ -112,8 +89,7 @@ void se_outb_p(unsigned char value, unsigned long port)
112 89
113void se_outw(unsigned short value, unsigned long port) 90void se_outw(unsigned short value, unsigned long port)
114{ 91{
115 if (port >= 0x2000 || 92 if (port >= 0x2000)
116 (sh_pcic_io_start <= port && port <= sh_pcic_io_stop))
117 *port2adr(port) = value; 93 *port2adr(port) = value;
118 else 94 else
119 maybebadio(port); 95 maybebadio(port);
@@ -129,11 +105,7 @@ void se_insb(unsigned long port, void *addr, unsigned long count)
129 volatile __u16 *p = port2adr(port); 105 volatile __u16 *p = port2adr(port);
130 __u8 *ap = addr; 106 __u8 *ap = addr;
131 107
132 if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) { 108 if (shifted_port(port)) {
133 volatile __u8 *bp = (__u8 *) (sh_pcic_io_wbase + 0x40000 + port);
134 while (count--)
135 *ap++ = *bp;
136 } else if (shifted_port(port)) {
137 while (count--) 109 while (count--)
138 *ap++ = *p >> 8; 110 *ap++ = *p >> 8;
139 } else { 111 } else {
@@ -160,11 +132,7 @@ void se_outsb(unsigned long port, const void *addr, unsigned long count)
160 volatile __u16 *p = port2adr(port); 132 volatile __u16 *p = port2adr(port);
161 const __u8 *ap = addr; 133 const __u8 *ap = addr;
162 134
163 if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) { 135 if (shifted_port(port)) {
164 volatile __u8 *bp = (__u8 *) (sh_pcic_io_wbase + port);
165 while (count--)
166 *bp = *ap++;
167 } else if (shifted_port(port)) {
168 while (count--) 136 while (count--)
169 *p = *ap++ << 8; 137 *p = *ap++ << 8;
170 } else { 138 } else {
@@ -177,6 +145,7 @@ void se_outsw(unsigned long port, const void *addr, unsigned long count)
177{ 145{
178 volatile __u16 *p = port2adr(port); 146 volatile __u16 *p = port2adr(port);
179 const __u16 *ap = addr; 147 const __u16 *ap = addr;
148
180 while (count--) 149 while (count--)
181 *p = *ap++; 150 *p = *ap++;
182} 151}
diff --git a/arch/sh/boards/se/770x/setup.c b/arch/sh/boards/se/770x/setup.c
index 318bc8a3969c..cf4a5ba12df4 100644
--- a/arch/sh/boards/se/770x/setup.c
+++ b/arch/sh/boards/se/770x/setup.c
@@ -14,8 +14,6 @@
14#include <asm/smc37c93x.h> 14#include <asm/smc37c93x.h>
15#include <asm/heartbeat.h> 15#include <asm/heartbeat.h>
16 16
17void init_se_IRQ(void);
18
19/* 17/*
20 * Configure the Super I/O chip 18 * Configure the Super I/O chip
21 */ 19 */
@@ -73,7 +71,7 @@ static struct resource cf_ide_resources[] = {
73 }, 71 },
74 [1] = { 72 [1] = {
75 .start = PA_MRSHPC_IO + 0x1f0 + 0x206, 73 .start = PA_MRSHPC_IO + 0x1f0 + 0x206,
76 .end = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8, 74 .end = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8,
77 .flags = IORESOURCE_MEM, 75 .flags = IORESOURCE_MEM,
78 }, 76 },
79 [2] = { 77 [2] = {
@@ -115,9 +113,58 @@ static struct platform_device heartbeat_device = {
115 .resource = heartbeat_resources, 113 .resource = heartbeat_resources,
116}; 114};
117 115
116/* SH771X Ethernet driver */
117static struct resource sh_eth0_resources[] = {
118 [0] = {
119 .start = SH_ETH0_BASE,
120 .end = SH_ETH0_BASE + 0x1B8,
121 .flags = IORESOURCE_MEM,
122 },
123 [1] = {
124 .start = SH_ETH0_IRQ,
125 .end = SH_ETH0_IRQ,
126 .flags = IORESOURCE_IRQ,
127 },
128};
129
130static struct platform_device sh_eth0_device = {
131 .name = "sh-eth",
132 .id = 0,
133 .dev = {
134 .platform_data = PHY_ID,
135 },
136 .num_resources = ARRAY_SIZE(sh_eth0_resources),
137 .resource = sh_eth0_resources,
138};
139
140static struct resource sh_eth1_resources[] = {
141 [0] = {
142 .start = SH_ETH1_BASE,
143 .end = SH_ETH1_BASE + 0x1B8,
144 .flags = IORESOURCE_MEM,
145 },
146 [1] = {
147 .start = SH_ETH1_IRQ,
148 .end = SH_ETH1_IRQ,
149 .flags = IORESOURCE_IRQ,
150 },
151};
152
153static struct platform_device sh_eth1_device = {
154 .name = "sh-eth",
155 .id = 1,
156 .dev = {
157 .platform_data = PHY_ID,
158 },
159 .num_resources = ARRAY_SIZE(sh_eth1_resources),
160 .resource = sh_eth1_resources,
161};
162
118static struct platform_device *se_devices[] __initdata = { 163static struct platform_device *se_devices[] __initdata = {
119 &heartbeat_device, 164 &heartbeat_device,
120 &cf_ide_device, 165 &cf_ide_device,
166 &sh_eth0_device,
167 &sh_eth1_device,
121}; 168};
122 169
123static int __init se_devices_setup(void) 170static int __init se_devices_setup(void)
diff --git a/arch/sh/boards/se/7722/setup.c b/arch/sh/boards/se/7722/setup.c
index ede3957fc14a..6e228ea59788 100644
--- a/arch/sh/boards/se/7722/setup.c
+++ b/arch/sh/boards/se/7722/setup.c
@@ -16,6 +16,7 @@
16#include <linux/input.h> 16#include <linux/input.h>
17#include <linux/smc91x.h> 17#include <linux/smc91x.h>
18#include <asm/machvec.h> 18#include <asm/machvec.h>
19#include <asm/clock.h>
19#include <asm/se7722.h> 20#include <asm/se7722.h>
20#include <asm/io.h> 21#include <asm/io.h>
21#include <asm/heartbeat.h> 22#include <asm/heartbeat.h>
@@ -145,6 +146,8 @@ static struct platform_device *se7722_devices[] __initdata = {
145 146
146static int __init se7722_devices_setup(void) 147static int __init se7722_devices_setup(void)
147{ 148{
149 clk_always_enable("mstp214"); /* KEYSC */
150
148 return platform_add_devices(se7722_devices, 151 return platform_add_devices(se7722_devices,
149 ARRAY_SIZE(se7722_devices)); 152 ARRAY_SIZE(se7722_devices));
150} 153}
@@ -154,11 +157,6 @@ static void __init se7722_setup(char **cmdline_p)
154{ 157{
155 ctrl_outw(0x010D, FPGA_OUT); /* FPGA */ 158 ctrl_outw(0x010D, FPGA_OUT); /* FPGA */
156 159
157 ctrl_outl(0x00051001, MSTPCR0);
158 ctrl_outl(0x00000000, MSTPCR1);
159 /* KEYSC, VOU, BEU, CEU, VEU, VPU, LCDC, USB */
160 ctrl_outl(0xffffb7c0, MSTPCR2);
161
162 ctrl_outw(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */ 160 ctrl_outw(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */
163 ctrl_outw(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */ 161 ctrl_outw(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */
164 162
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 16:43:58 -0500