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authorSimon Arlott <simon@fire.lp0.eu>2007-05-13 19:15:10 -0400
committerPaul Mundt <lethal@linux-sh.org>2007-05-21 01:31:39 -0400
commite868d61272caa648214046a096e5a6bfc068dc8c (patch)
tree087153c10725af12129ac8c55bda489f255bdd2c /arch/sh/boards/superh
parent049fa57ce3b22d9f5acb251070941b630ee71d6e (diff)
spelling fixes: arch/sh/
Spelling fixes in arch/sh/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/boards/superh')
-rw-r--r--arch/sh/boards/superh/microdev/io.c6
-rw-r--r--arch/sh/boards/superh/microdev/irq.c6
-rw-r--r--arch/sh/boards/superh/microdev/setup.c2
3 files changed, 7 insertions, 7 deletions
diff --git a/arch/sh/boards/superh/microdev/io.c b/arch/sh/boards/superh/microdev/io.c
index 83419bf4c834..b704e20d7e4d 100644
--- a/arch/sh/boards/superh/microdev/io.c
+++ b/arch/sh/boards/superh/microdev/io.c
@@ -198,12 +198,12 @@ void microdev_outb(unsigned char b, unsigned long port)
198 /* 198 /*
199 * There is a board feature with the current SH4-202 MicroDev in 199 * There is a board feature with the current SH4-202 MicroDev in
200 * that the 2 byte enables (nBE0 and nBE1) are tied together (and 200 * that the 2 byte enables (nBE0 and nBE1) are tied together (and
201 * to the Chip Select Line (Ethernet_CS)). Due to this conectivity, 201 * to the Chip Select Line (Ethernet_CS)). Due to this connectivity,
202 * it is not possible to safely perform 8-bit writes to the 202 * it is not possible to safely perform 8-bit writes to the
203 * Ethernet registers, as 16-bits will be consumed from the Data 203 * Ethernet registers, as 16-bits will be consumed from the Data
204 * lines (corrupting the other byte). Hence, this function is 204 * lines (corrupting the other byte). Hence, this function is
205 * written to impliment 16-bit read/modify/write for all byte-wide 205 * written to implement 16-bit read/modify/write for all byte-wide
206 * acceses. 206 * accesses.
207 * 207 *
208 * Note: there is no problem with byte READS (even or odd). 208 * Note: there is no problem with byte READS (even or odd).
209 * 209 *
diff --git a/arch/sh/boards/superh/microdev/irq.c b/arch/sh/boards/superh/microdev/irq.c
index 8c64baa30364..cc1cb04fa618 100644
--- a/arch/sh/boards/superh/microdev/irq.c
+++ b/arch/sh/boards/superh/microdev/irq.c
@@ -100,7 +100,7 @@ static void disable_microdev_irq(unsigned int irq)
100 100
101 fpgaIrq = fpgaIrqTable[irq].fpgaIrq; 101 fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
102 102
103 /* disable interupts on the FPGA INTC register */ 103 /* disable interrupts on the FPGA INTC register */
104 ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG); 104 ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG);
105} 105}
106 106
@@ -125,7 +125,7 @@ static void enable_microdev_irq(unsigned int irq)
125 priorities |= MICRODEV_FPGA_INTPRI_LEVEL(fpgaIrq, pri); 125 priorities |= MICRODEV_FPGA_INTPRI_LEVEL(fpgaIrq, pri);
126 ctrl_outl(priorities, priorityReg); 126 ctrl_outl(priorities, priorityReg);
127 127
128 /* enable interupts on the FPGA INTC register */ 128 /* enable interrupts on the FPGA INTC register */
129 ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG); 129 ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
130} 130}
131 131
@@ -152,7 +152,7 @@ extern void __init init_microdev_irq(void)
152{ 152{
153 int i; 153 int i;
154 154
155 /* disable interupts on the FPGA INTC register */ 155 /* disable interrupts on the FPGA INTC register */
156 ctrl_outl(~0ul, MICRODEV_FPGA_INTDSB_REG); 156 ctrl_outl(~0ul, MICRODEV_FPGA_INTDSB_REG);
157 157
158 for (i = 0; i < NUM_EXTERNAL_IRQS; i++) 158 for (i = 0; i < NUM_EXTERNAL_IRQS; i++)
diff --git a/arch/sh/boards/superh/microdev/setup.c b/arch/sh/boards/superh/microdev/setup.c
index 031c814e6e76..6396cea1c896 100644
--- a/arch/sh/boards/superh/microdev/setup.c
+++ b/arch/sh/boards/superh/microdev/setup.c
@@ -349,7 +349,7 @@ static int __init smsc_superio_setup(void)
349 SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */ 349 SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
350 SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */ 350 SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */
351 351
352 /* Exit the configuraton state */ 352 /* Exit the configuration state */
353 outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); 353 outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
354 354
355 return 0; 355 return 0;