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authorPaul Mackerras <paulus@samba.org>2006-12-03 23:59:07 -0500
committerPaul Mackerras <paulus@samba.org>2006-12-03 23:59:07 -0500
commit79acbb3ff2d8095b692e1502b9eb2ccec348de26 (patch)
tree6ab773e5a8f9de2cd6443362b21d0d6fffe3b35e /arch/sh/boards/se
parent19a79859e168640f8e16d7b216d211c1c52b687a (diff)
parent2b5f6dcce5bf94b9b119e9ed8d537098ec61c3d2 (diff)
Merge branch 'linux-2.6' into for-linus
Diffstat (limited to 'arch/sh/boards/se')
-rw-r--r--arch/sh/boards/se/7300/irq.c20
-rw-r--r--arch/sh/boards/se/73180/irq.c47
-rw-r--r--arch/sh/boards/se/7343/irq.c90
-rw-r--r--arch/sh/boards/se/770x/irq.c80
-rw-r--r--arch/sh/boards/se/7751/irq.c85
5 files changed, 173 insertions, 149 deletions
diff --git a/arch/sh/boards/se/7300/irq.c b/arch/sh/boards/se/7300/irq.c
index ad1034f98a29..1279d776d60f 100644
--- a/arch/sh/boards/se/7300/irq.c
+++ b/arch/sh/boards/se/7300/irq.c
@@ -13,6 +13,17 @@
13#include <asm/io.h> 13#include <asm/io.h>
14#include <asm/se7300.h> 14#include <asm/se7300.h>
15 15
16static struct ipr_data se7300_ipr_map[] = {
17 /* PC_IRQ[0-3] -> IRQ0 (32) */
18 { IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, 0x0f - IRQ0_IRQ },
19 /* A_IRQ[0-3] -> IRQ1 (33) */
20 { IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, 0x0f - IRQ1_IRQ },
21 { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
22 { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
23 { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
24 { VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
25};
26
16/* 27/*
17 * Initialize IRQ setting 28 * Initialize IRQ setting
18 */ 29 */
@@ -23,14 +34,7 @@ init_7300se_IRQ(void)
23 ctrl_outw(0xa000, INTC_ICR1); /* IRQ mode; IRQ0,1 enable. */ 34 ctrl_outw(0xa000, INTC_ICR1); /* IRQ mode; IRQ0,1 enable. */
24 ctrl_outw(0x0000, PORT_PFCR); /* use F for IRQ[3:0] and SIU. */ 35 ctrl_outw(0x0000, PORT_PFCR); /* use F for IRQ[3:0] and SIU. */
25 36
26 /* PC_IRQ[0-3] -> IRQ0 (32) */ 37 make_ipr_irq(se7300_ipr_map, ARRAY_SIZE(se7300_ipr_map));
27 make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, 0x0f - IRQ0_IRQ);
28 /* A_IRQ[0-3] -> IRQ1 (33) */
29 make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, 0x0f - IRQ1_IRQ);
30 make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY);
31 make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
32 make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
33 make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
34 38
35 ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */ 39 ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */
36} 40}
diff --git a/arch/sh/boards/se/73180/irq.c b/arch/sh/boards/se/73180/irq.c
index 2c62b8ea350e..e7200c56bb45 100644
--- a/arch/sh/boards/se/73180/irq.c
+++ b/arch/sh/boards/se/73180/irq.c
@@ -87,13 +87,38 @@ shmse_irq_demux(int irq)
87 return irq; 87 return irq;
88} 88}
89 89
90static struct ipr_data se73180_siof0_ipr_map[] = {
91 { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
92};
93static struct ipr_data se73180_vpu_ipr_map[] = {
94 { VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 },
95};
96static struct ipr_data se73180_other_ipr_map[] = {
97 { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
98 { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
99 { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
100 { IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
101 { IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
102 { IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
103 { IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
104 { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
105 { SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY },
106
107 /* VIO interrupt */
108 { CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
109 { BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
110 { VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
111
112 { LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY },
113};
114
90/* 115/*
91 * Initialize IRQ setting 116 * Initialize IRQ setting
92 */ 117 */
93void __init 118void __init
94init_73180se_IRQ(void) 119init_73180se_IRQ(void)
95{ 120{
96 make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY); 121 make_ipr_irq(se73180_siof0_ipr_map, ARRAY_SIZE(se73180_siof0_ipr_map));
97 122
98 ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */ 123 ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */
99 ctrl_outw(0x2000, 0xb07fffec); /* mrshpc irq enable */ 124 ctrl_outw(0x2000, 0xb07fffec); /* mrshpc irq enable */
@@ -101,27 +126,11 @@ init_73180se_IRQ(void)
101 ctrl_outw(2 << ((7 - 5) * 2), INTC_ICR1); /* low-level irq */ 126 ctrl_outw(2 << ((7 - 5) * 2), INTC_ICR1); /* low-level irq */
102 make_intreq_irq(10); 127 make_intreq_irq(10);
103 128
104 make_ipr_irq(VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8); 129 make_ipr_irq(se73180_vpu_ipr_map, ARRAY_SIZE(se73180_vpu_ipr_map));
105 130
106 ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */ 131 ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */
107 132
108 make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 133 make_ipr_irq(se73180_other_ipr_map, ARRAY_SIZE(se73180_other_ipr_map));
109 make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
110 make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY);
111 make_ipr_irq(IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY);
112 make_ipr_irq(IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS,
113 IIC0_PRIORITY);
114 make_ipr_irq(IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS,
115 IIC0_PRIORITY);
116 make_ipr_irq(IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY);
117 make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY);
118 make_ipr_irq(SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY);
119
120 /* VIO interrupt */
121 make_ipr_irq(CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
122 make_ipr_irq(BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
123 make_ipr_irq(VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
124 134
125 make_ipr_irq(LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY);
126 ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */ 135 ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */
127} 136}
diff --git a/arch/sh/boards/se/7343/irq.c b/arch/sh/boards/se/7343/irq.c
index 288b62f59419..360153ecc55b 100644
--- a/arch/sh/boards/se/7343/irq.c
+++ b/arch/sh/boards/se/7343/irq.c
@@ -102,6 +102,51 @@ shmse_irq_demux(int irq)
102static struct irqaction irq5 = { no_action, 0, CPU_MASK_NONE, "IRQ5-cascade", 102static struct irqaction irq5 = { no_action, 0, CPU_MASK_NONE, "IRQ5-cascade",
103 NULL, NULL}; 103 NULL, NULL};
104 104
105static struct ipr_data se7343_irq5_ipr_map[] = {
106 { IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY },
107};
108static struct ipr_data se7343_siof0_vpu_ipr_map[] = {
109 { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
110 { VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 },
111};
112static struct ipr_data se7343_other_ipr_map[] = {
113 { DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
114 { DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
115 { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
116 { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
117 { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
118 { DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
119
120 /* I2C block */
121 { IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
122 { IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
123 { IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
124 { IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
125
126 { IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
127 { IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
128 { IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
129 { IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
130
131 /* SIOF */
132 { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
133
134 /* SIU */
135 { SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY },
136
137 /* VIO interrupt */
138 { CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
139 { BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
140 { VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
141
142 /*MFI interrupt*/
143
144 { MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY },
145
146 /* LCD controller */
147 { LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY },
148};
149
105/* 150/*
106 * Initialize IRQ setting 151 * Initialize IRQ setting
107 */ 152 */
@@ -138,54 +183,17 @@ init_7343se_IRQ(void)
138 /* Setup all external interrupts to be active low */ 183 /* Setup all external interrupts to be active low */
139 ctrl_outw(0xaaaa, INTC_ICR1); 184 ctrl_outw(0xaaaa, INTC_ICR1);
140 185
141 make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY); 186 make_ipr_irq(se7343_irq5_ipr_map, ARRAY_SIZE(se7343_irq5_ipr_map));
187
142 setup_irq(IRQ5_IRQ, &irq5); 188 setup_irq(IRQ5_IRQ, &irq5);
143 /* Set port control to use IRQ5 */ 189 /* Set port control to use IRQ5 */
144 *(u16 *)0xA4050108 &= ~0xc; 190 *(u16 *)0xA4050108 &= ~0xc;
145 191
146 make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY); 192 make_ipr_irq(se7343_siof0_vpu_ipr_map, ARRAY_SIZE(se7343_siof0_vpu_ipr_map));
147 make_ipr_irq(VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8);
148 193
149 ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */ 194 ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */
150 195
151 make_ipr_irq(DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 196 make_ipr_irq(se7343_other_ipr_map, ARRAY_SIZE(se7343_other_ipr_map));
152 make_ipr_irq(DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
153 make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
154 make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
155 make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY);
156 make_ipr_irq(DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY);
157
158 /* I2C block */
159 make_ipr_irq(IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY);
160 make_ipr_irq(IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS,
161 IIC0_PRIORITY);
162 make_ipr_irq(IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS,
163 IIC0_PRIORITY);
164 make_ipr_irq(IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY);
165
166 make_ipr_irq(IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY);
167 make_ipr_irq(IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS,
168 IIC1_PRIORITY);
169 make_ipr_irq(IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS,
170 IIC1_PRIORITY);
171 make_ipr_irq(IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY);
172
173 /* SIOF */
174 make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY);
175 197
176 /* SIU */
177 make_ipr_irq(SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY);
178
179 /* VIO interrupt */
180 make_ipr_irq(CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
181 make_ipr_irq(BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
182 make_ipr_irq(VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
183
184 /*MFI interrupt*/
185
186 make_ipr_irq(MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY);
187
188 /* LCD controller */
189 make_ipr_irq(LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY);
190 ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */ 198 ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */
191} 199}
diff --git a/arch/sh/boards/se/770x/irq.c b/arch/sh/boards/se/770x/irq.c
index cff6700bbafd..fcd7cd7fa05f 100644
--- a/arch/sh/boards/se/770x/irq.c
+++ b/arch/sh/boards/se/770x/irq.c
@@ -13,6 +13,48 @@
13#include <asm/io.h> 13#include <asm/io.h>
14#include <asm/se.h> 14#include <asm/se.h>
15 15
16static struct ipr_data se770x_ipr_map[] = {
17#if defined(CONFIG_CPU_SUBTYPE_SH7705)
18 /* This is default value */
19 { 0xf-0x2, BCR_ILCRA, 2, 0x2 },
20 { 0xf-0xa, BCR_ILCRA, 1, 0xa },
21 { 0xf-0x5, BCR_ILCRB, 0, 0x5 },
22 { 0xf-0x8, BCR_ILCRC, 1, 0x8 },
23 { 0xf-0xc, BCR_ILCRC, 0, 0xc },
24 { 0xf-0xe, BCR_ILCRD, 3, 0xe },
25 { 0xf-0x3, BCR_ILCRD, 1, 0x3 }, /* LAN */
26 { 0xf-0xd, BCR_ILCRE, 2, 0xd },
27 { 0xf-0x9, BCR_ILCRE, 1, 0x9 },
28 { 0xf-0x1, BCR_ILCRE, 0, 0x1 },
29 { 0xf-0xf, BCR_ILCRF, 3, 0xf },
30 { 0xf-0xb, BCR_ILCRF, 1, 0xb },
31 { 0xf-0x7, BCR_ILCRG, 3, 0x7 },
32 { 0xf-0x6, BCR_ILCRG, 2, 0x6 },
33 { 0xf-0x4, BCR_ILCRG, 1, 0x4 },
34#else
35 { 14, BCR_ILCRA, 2, 0x0f-14 },
36 { 12, BCR_ILCRA, 1, 0x0f-12 },
37 { 8, BCR_ILCRB, 1, 0x0f- 8 },
38 { 6, BCR_ILCRC, 3, 0x0f- 6 },
39 { 5, BCR_ILCRC, 2, 0x0f- 5 },
40 { 4, BCR_ILCRC, 1, 0x0f- 4 },
41 { 3, BCR_ILCRC, 0, 0x0f- 3 },
42 { 1, BCR_ILCRD, 3, 0x0f- 1 },
43
44 { 10, BCR_ILCRD, 1, 0x0f-10 }, /* LAN */
45
46 { 0, BCR_ILCRE, 3, 0x0f- 0 }, /* PCIRQ3 */
47 { 11, BCR_ILCRE, 2, 0x0f-11 }, /* PCIRQ2 */
48 { 9, BCR_ILCRE, 1, 0x0f- 9 }, /* PCIRQ1 */
49 { 7, BCR_ILCRE, 0, 0x0f- 7 }, /* PCIRQ0 */
50
51 /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
52 /* NOTE: #2 and #13 are not used on PC */
53 { 13, BCR_ILCRG, 1, 0x0f-13 }, /* SLOTIRQ2 */
54 { 2, BCR_ILCRG, 0, 0x0f- 2 }, /* SLOTIRQ1 */
55#endif
56};
57
16/* 58/*
17 * Initialize IRQ setting 59 * Initialize IRQ setting
18 */ 60 */
@@ -38,42 +80,6 @@ void __init init_se_IRQ(void)
38 ctrl_outw(0, BCR_ILCRE); 80 ctrl_outw(0, BCR_ILCRE);
39 ctrl_outw(0, BCR_ILCRF); 81 ctrl_outw(0, BCR_ILCRF);
40 ctrl_outw(0, BCR_ILCRG); 82 ctrl_outw(0, BCR_ILCRG);
41 /* This is default value */
42 make_ipr_irq(0xf-0x2, BCR_ILCRA, 2, 0x2);
43 make_ipr_irq(0xf-0xa, BCR_ILCRA, 1, 0xa);
44 make_ipr_irq(0xf-0x5, BCR_ILCRB, 0, 0x5);
45 make_ipr_irq(0xf-0x8, BCR_ILCRC, 1, 0x8);
46 make_ipr_irq(0xf-0xc, BCR_ILCRC, 0, 0xc);
47 make_ipr_irq(0xf-0xe, BCR_ILCRD, 3, 0xe);
48 make_ipr_irq(0xf-0x3, BCR_ILCRD, 1, 0x3); /* LAN */
49 make_ipr_irq(0xf-0xd, BCR_ILCRE, 2, 0xd);
50 make_ipr_irq(0xf-0x9, BCR_ILCRE, 1, 0x9);
51 make_ipr_irq(0xf-0x1, BCR_ILCRE, 0, 0x1);
52 make_ipr_irq(0xf-0xf, BCR_ILCRF, 3, 0xf);
53 make_ipr_irq(0xf-0xb, BCR_ILCRF, 1, 0xb);
54 make_ipr_irq(0xf-0x7, BCR_ILCRG, 3, 0x7);
55 make_ipr_irq(0xf-0x6, BCR_ILCRG, 2, 0x6);
56 make_ipr_irq(0xf-0x4, BCR_ILCRG, 1, 0x4);
57#else
58 make_ipr_irq(14, BCR_ILCRA, 2, 0x0f-14);
59 make_ipr_irq(12, BCR_ILCRA, 1, 0x0f-12);
60 make_ipr_irq( 8, BCR_ILCRB, 1, 0x0f- 8);
61 make_ipr_irq( 6, BCR_ILCRC, 3, 0x0f- 6);
62 make_ipr_irq( 5, BCR_ILCRC, 2, 0x0f- 5);
63 make_ipr_irq( 4, BCR_ILCRC, 1, 0x0f- 4);
64 make_ipr_irq( 3, BCR_ILCRC, 0, 0x0f- 3);
65 make_ipr_irq( 1, BCR_ILCRD, 3, 0x0f- 1);
66
67 make_ipr_irq(10, BCR_ILCRD, 1, 0x0f-10); /* LAN */
68
69 make_ipr_irq( 0, BCR_ILCRE, 3, 0x0f- 0); /* PCIRQ3 */
70 make_ipr_irq(11, BCR_ILCRE, 2, 0x0f-11); /* PCIRQ2 */
71 make_ipr_irq( 9, BCR_ILCRE, 1, 0x0f- 9); /* PCIRQ1 */
72 make_ipr_irq( 7, BCR_ILCRE, 0, 0x0f- 7); /* PCIRQ0 */
73
74 /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
75 /* NOTE: #2 and #13 are not used on PC */
76 make_ipr_irq(13, BCR_ILCRG, 1, 0x0f-13); /* SLOTIRQ2 */
77 make_ipr_irq( 2, BCR_ILCRG, 0, 0x0f- 2); /* SLOTIRQ1 */
78#endif 83#endif
84 make_ipr_irq(se770x_ipr_map, ARRAY_SIZE(se770x_ipr_map));
79} 85}
diff --git a/arch/sh/boards/se/7751/irq.c b/arch/sh/boards/se/7751/irq.c
index c607b0a48479..e4c63a48296c 100644
--- a/arch/sh/boards/se/7751/irq.c
+++ b/arch/sh/boards/se/7751/irq.c
@@ -14,53 +14,50 @@
14#include <asm/irq.h> 14#include <asm/irq.h>
15#include <asm/se7751.h> 15#include <asm/se7751.h>
16 16
17/* 17static struct ipr_data se7751_ipr_map[] = {
18 * Initialize IRQ setting
19 */
20void __init init_7751se_IRQ(void)
21{
22
23 /* Leave old Solution Engine code in for reference. */ 18 /* Leave old Solution Engine code in for reference. */
24#if defined(CONFIG_SH_SOLUTION_ENGINE) 19#if defined(CONFIG_SH_SOLUTION_ENGINE)
25 /* 20 /*
26 * Super I/O (Just mimic PC): 21 * Super I/O (Just mimic PC):
27 * 1: keyboard 22 * 1: keyboard
28 * 3: serial 0 23 * 3: serial 0
29 * 4: serial 1 24 * 4: serial 1
30 * 5: printer 25 * 5: printer
31 * 6: floppy 26 * 6: floppy
32 * 8: rtc 27 * 8: rtc
33 * 12: mouse 28 * 12: mouse
34 * 14: ide0 29 * 14: ide0
35 */ 30 */
36 make_ipr_irq(14, BCR_ILCRA, 2, 0x0f-14); 31 { 14, BCR_ILCRA, 2, 0x0f-14 },
37 make_ipr_irq(12, BCR_ILCRA, 1, 0x0f-12); 32 { 12, BCR_ILCRA, 1, 0x0f-12 },
38 make_ipr_irq( 8, BCR_ILCRB, 1, 0x0f- 8); 33 { 8, BCR_ILCRB, 1, 0x0f- 8 },
39 make_ipr_irq( 6, BCR_ILCRC, 3, 0x0f- 6); 34 { 6, BCR_ILCRC, 3, 0x0f- 6 },
40 make_ipr_irq( 5, BCR_ILCRC, 2, 0x0f- 5); 35 { 5, BCR_ILCRC, 2, 0x0f- 5 },
41 make_ipr_irq( 4, BCR_ILCRC, 1, 0x0f- 4); 36 { 4, BCR_ILCRC, 1, 0x0f- 4 },
42 make_ipr_irq( 3, BCR_ILCRC, 0, 0x0f- 3); 37 { 3, BCR_ILCRC, 0, 0x0f- 3 },
43 make_ipr_irq( 1, BCR_ILCRD, 3, 0x0f- 1); 38 { 1, BCR_ILCRD, 3, 0x0f- 1 },
44 39
45 make_ipr_irq(10, BCR_ILCRD, 1, 0x0f-10); /* LAN */ 40 { 10, BCR_ILCRD, 1, 0x0f-10 }, /* LAN */
46 41
47 make_ipr_irq( 0, BCR_ILCRE, 3, 0x0f- 0); /* PCIRQ3 */ 42 { 0, BCR_ILCRE, 3, 0x0f- 0 }, /* PCIRQ3 */
48 make_ipr_irq(11, BCR_ILCRE, 2, 0x0f-11); /* PCIRQ2 */ 43 { 11, BCR_ILCRE, 2, 0x0f-11 }, /* PCIRQ2 */
49 make_ipr_irq( 9, BCR_ILCRE, 1, 0x0f- 9); /* PCIRQ1 */ 44 { 9, BCR_ILCRE, 1, 0x0f- 9 }, /* PCIRQ1 */
50 make_ipr_irq( 7, BCR_ILCRE, 0, 0x0f- 7); /* PCIRQ0 */ 45 { 7, BCR_ILCRE, 0, 0x0f- 7 }, /* PCIRQ0 */
51 46
52 /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */ 47 /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
53 /* NOTE: #2 and #13 are not used on PC */ 48 /* NOTE: #2 and #13 are not used on PC */
54 make_ipr_irq(13, BCR_ILCRG, 1, 0x0f-13); /* SLOTIRQ2 */ 49 { 13, BCR_ILCRG, 1, 0x0f-13 }, /* SLOTIRQ2 */
55 make_ipr_irq( 2, BCR_ILCRG, 0, 0x0f- 2); /* SLOTIRQ1 */ 50 { 2, BCR_ILCRG, 0, 0x0f- 2 }, /* SLOTIRQ1 */
56
57#elif defined(CONFIG_SH_7751_SOLUTION_ENGINE) 51#elif defined(CONFIG_SH_7751_SOLUTION_ENGINE)
58 52 { 13, BCR_ILCRD, 3, 2 },
59 make_ipr_irq(13, BCR_ILCRD, 3, 2); 53 /* Add additional entries here as drivers are added and tested. */
60
61 /* Add additional calls to make_ipr_irq() as drivers are added
62 * and tested.
63 */
64#endif 54#endif
55};
65 56
57/*
58 * Initialize IRQ setting
59 */
60void __init init_7751se_IRQ(void)
61{
62 make_ipr_irq(se7751_ipr_map, ARRAY_SIZE(se7751_ipr_map));
66} 63}