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authorMagnus Damm <damm@igel.co.jp>2007-07-31 04:13:39 -0400
committerPaul Mundt <lethal@linux-sh.org>2007-09-20 22:57:47 -0400
commitc9d03d9a80c4bcc571efd93fe80ed40973030422 (patch)
tree36cf0a0dd2024fca11257b3f101a6b9f4d83282c /arch/sh/boards/se
parente29bfbc44332ee2233d87d5adfd1824fd8a1c73b (diff)
sh: simplify se7780 IRQ code
The new intc code handles IRQ3 and IRQ7 in the cpu specific code already, so there is no reason to duplicate that here. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/boards/se')
-rw-r--r--arch/sh/boards/se/7780/irq.c28
1 files changed, 1 insertions, 27 deletions
diff --git a/arch/sh/boards/se/7780/irq.c b/arch/sh/boards/se/7780/irq.c
index 874914746009..6bd70da6bb47 100644
--- a/arch/sh/boards/se/7780/irq.c
+++ b/arch/sh/boards/se/7780/irq.c
@@ -16,32 +16,6 @@
16#include <asm/io.h> 16#include <asm/io.h>
17#include <asm/se7780.h> 17#include <asm/se7780.h>
18 18
19static struct intc2_data intc2_irq_table[] = {
20 { 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT1 */
21 { 4, 0, 30, 0, 30, 3 }, /* daughter board EXTINT2 */
22 { 6, 0, 29, 0, 29, 3 }, /* daughter board EXTINT3 */
23 { 8, 0, 28, 0, 28, 3 }, /* SMC 91C111 (LAN) */
24 { 10, 0, 27, 0, 27, 3 }, /* daughter board EXTINT4 */
25 { 4, 0, 30, 0, 30, 3 }, /* daughter board EXTINT5 */
26 { 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT6 */
27 { 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT7 */
28 { 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT8 */
29 { 0 , 0, 24, 0, 24, 3 }, /* SM501 */
30};
31
32static struct intc2_desc intc2_irq_desc __read_mostly = {
33 .prio_base = 0, /* N/A */
34 .msk_base = 0xffd00044,
35 .mskclr_base = 0xffd00064,
36
37 .intc2_data = intc2_irq_table,
38 .nr_irqs = ARRAY_SIZE(intc2_irq_table),
39
40 .chip = {
41 .name = "INTC2-se7780",
42 },
43};
44
45/* 19/*
46 * Initialize IRQ setting 20 * Initialize IRQ setting
47 */ 21 */
@@ -68,5 +42,5 @@ void __init init_se7780_IRQ(void)
68 /* FPGA + 0x0A */ 42 /* FPGA + 0x0A */
69 ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3); 43 ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
70 44
71 register_intc2_controller(&intc2_irq_desc); 45 plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */
72} 46}