diff options
author | Paul Mundt <lethal@linux-sh.org> | 2008-10-19 21:40:32 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2008-10-19 21:40:32 -0400 |
commit | 79ed2a9216dd3cc35c4f2c5dbaddadb195af83ac (patch) | |
tree | b1567c167b4eeb60cd0a4f316012a637045b0168 /arch/sh/boards/board-ap325rxa.c | |
parent | 25627c7fd71269e2658b6872eef65719ee80b9aa (diff) | |
parent | 843284d0e41b2a7f88504d051d91b5e9dc9c78c7 (diff) |
Merge branch 'sh/gpiolib'
Diffstat (limited to 'arch/sh/boards/board-ap325rxa.c')
-rw-r--r-- | arch/sh/boards/board-ap325rxa.c | 100 |
1 files changed, 74 insertions, 26 deletions
diff --git a/arch/sh/boards/board-ap325rxa.c b/arch/sh/boards/board-ap325rxa.c index 6abaf46a9835..84fa8a04eac4 100644 --- a/arch/sh/boards/board-ap325rxa.c +++ b/arch/sh/boards/board-ap325rxa.c | |||
@@ -18,11 +18,13 @@ | |||
18 | #include <linux/delay.h> | 18 | #include <linux/delay.h> |
19 | #include <linux/i2c.h> | 19 | #include <linux/i2c.h> |
20 | #include <linux/smc911x.h> | 20 | #include <linux/smc911x.h> |
21 | #include <linux/gpio.h> | ||
21 | #include <media/soc_camera_platform.h> | 22 | #include <media/soc_camera_platform.h> |
22 | #include <media/sh_mobile_ceu.h> | 23 | #include <media/sh_mobile_ceu.h> |
23 | #include <video/sh_mobile_lcdc.h> | 24 | #include <video/sh_mobile_lcdc.h> |
24 | #include <asm/io.h> | 25 | #include <asm/io.h> |
25 | #include <asm/clock.h> | 26 | #include <asm/clock.h> |
27 | #include <asm/sh7723.h> | ||
26 | 28 | ||
27 | static struct smc911x_platdata smc911x_info = { | 29 | static struct smc911x_platdata smc911x_info = { |
28 | .flags = SMC911X_USE_32BIT, | 30 | .flags = SMC911X_USE_32BIT, |
@@ -109,17 +111,7 @@ static struct platform_device ap325rxa_nor_flash_device = { | |||
109 | #define FPGA_LCDREG 0xB4100180 | 111 | #define FPGA_LCDREG 0xB4100180 |
110 | #define FPGA_BKLREG 0xB4100212 | 112 | #define FPGA_BKLREG 0xB4100212 |
111 | #define FPGA_LCDREG_VAL 0x0018 | 113 | #define FPGA_LCDREG_VAL 0x0018 |
112 | #define PORT_PHCR 0xA405010E | ||
113 | #define PORT_PLCR 0xA4050114 | ||
114 | #define PORT_PMCR 0xA4050116 | ||
115 | #define PORT_PRCR 0xA405011C | ||
116 | #define PORT_PSCR 0xA405011E | ||
117 | #define PORT_PZCR 0xA405014C | ||
118 | #define PORT_HIZCRA 0xA4050158 | ||
119 | #define PORT_MSELCRB 0xA4050182 | 114 | #define PORT_MSELCRB 0xA4050182 |
120 | #define PORT_PSDR 0xA405013E | ||
121 | #define PORT_PZDR 0xA405016C | ||
122 | #define PORT_PSELD 0xA4050154 | ||
123 | 115 | ||
124 | static void ap320_wvga_power_on(void *board_data) | 116 | static void ap320_wvga_power_on(void *board_data) |
125 | { | 117 | { |
@@ -129,8 +121,7 @@ static void ap320_wvga_power_on(void *board_data) | |||
129 | ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG); | 121 | ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG); |
130 | 122 | ||
131 | /* backlight */ | 123 | /* backlight */ |
132 | ctrl_outw((ctrl_inw(PORT_PSCR) & ~0x00C0) | 0x40, PORT_PSCR); | 124 | gpio_set_value(GPIO_PTS3, 0); |
133 | ctrl_outb(ctrl_inb(PORT_PSDR) & ~0x08, PORT_PSDR); | ||
134 | ctrl_outw(0x100, FPGA_BKLREG); | 125 | ctrl_outw(0x100, FPGA_BKLREG); |
135 | } | 126 | } |
136 | 127 | ||
@@ -301,8 +292,77 @@ static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = { | |||
301 | 292 | ||
302 | static int __init ap325rxa_devices_setup(void) | 293 | static int __init ap325rxa_devices_setup(void) |
303 | { | 294 | { |
304 | clk_always_enable("mstp200"); /* LCDC */ | 295 | /* LD3 and LD4 LEDs */ |
305 | clk_always_enable("mstp203"); /* CEU */ | 296 | gpio_request(GPIO_PTX5, NULL); /* RUN */ |
297 | gpio_direction_output(GPIO_PTX5, 1); | ||
298 | gpio_export(GPIO_PTX5, 0); | ||
299 | |||
300 | gpio_request(GPIO_PTX4, NULL); /* INDICATOR */ | ||
301 | gpio_direction_output(GPIO_PTX4, 0); | ||
302 | gpio_export(GPIO_PTX4, 0); | ||
303 | |||
304 | /* SW1 input */ | ||
305 | gpio_request(GPIO_PTF7, NULL); /* MODE */ | ||
306 | gpio_direction_input(GPIO_PTF7); | ||
307 | gpio_export(GPIO_PTF7, 0); | ||
308 | |||
309 | /* LCDC */ | ||
310 | clk_always_enable("mstp200"); | ||
311 | gpio_request(GPIO_FN_LCDD15, NULL); | ||
312 | gpio_request(GPIO_FN_LCDD14, NULL); | ||
313 | gpio_request(GPIO_FN_LCDD13, NULL); | ||
314 | gpio_request(GPIO_FN_LCDD12, NULL); | ||
315 | gpio_request(GPIO_FN_LCDD11, NULL); | ||
316 | gpio_request(GPIO_FN_LCDD10, NULL); | ||
317 | gpio_request(GPIO_FN_LCDD9, NULL); | ||
318 | gpio_request(GPIO_FN_LCDD8, NULL); | ||
319 | gpio_request(GPIO_FN_LCDD7, NULL); | ||
320 | gpio_request(GPIO_FN_LCDD6, NULL); | ||
321 | gpio_request(GPIO_FN_LCDD5, NULL); | ||
322 | gpio_request(GPIO_FN_LCDD4, NULL); | ||
323 | gpio_request(GPIO_FN_LCDD3, NULL); | ||
324 | gpio_request(GPIO_FN_LCDD2, NULL); | ||
325 | gpio_request(GPIO_FN_LCDD1, NULL); | ||
326 | gpio_request(GPIO_FN_LCDD0, NULL); | ||
327 | gpio_request(GPIO_FN_LCDLCLK_PTR, NULL); | ||
328 | gpio_request(GPIO_FN_LCDDCK, NULL); | ||
329 | gpio_request(GPIO_FN_LCDVEPWC, NULL); | ||
330 | gpio_request(GPIO_FN_LCDVCPWC, NULL); | ||
331 | gpio_request(GPIO_FN_LCDVSYN, NULL); | ||
332 | gpio_request(GPIO_FN_LCDHSYN, NULL); | ||
333 | gpio_request(GPIO_FN_LCDDISP, NULL); | ||
334 | gpio_request(GPIO_FN_LCDDON, NULL); | ||
335 | |||
336 | /* LCD backlight */ | ||
337 | gpio_request(GPIO_PTS3, NULL); | ||
338 | gpio_direction_output(GPIO_PTS3, 1); | ||
339 | |||
340 | /* CEU */ | ||
341 | clk_always_enable("mstp203"); | ||
342 | gpio_request(GPIO_FN_VIO_CLK2, NULL); | ||
343 | gpio_request(GPIO_FN_VIO_VD2, NULL); | ||
344 | gpio_request(GPIO_FN_VIO_HD2, NULL); | ||
345 | gpio_request(GPIO_FN_VIO_FLD, NULL); | ||
346 | gpio_request(GPIO_FN_VIO_CKO, NULL); | ||
347 | gpio_request(GPIO_FN_VIO_D15, NULL); | ||
348 | gpio_request(GPIO_FN_VIO_D14, NULL); | ||
349 | gpio_request(GPIO_FN_VIO_D13, NULL); | ||
350 | gpio_request(GPIO_FN_VIO_D12, NULL); | ||
351 | gpio_request(GPIO_FN_VIO_D11, NULL); | ||
352 | gpio_request(GPIO_FN_VIO_D10, NULL); | ||
353 | gpio_request(GPIO_FN_VIO_D9, NULL); | ||
354 | gpio_request(GPIO_FN_VIO_D8, NULL); | ||
355 | |||
356 | gpio_request(GPIO_PTZ7, NULL); | ||
357 | gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */ | ||
358 | gpio_request(GPIO_PTZ6, NULL); | ||
359 | gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */ | ||
360 | gpio_request(GPIO_PTZ5, NULL); | ||
361 | gpio_direction_output(GPIO_PTZ5, 1); /* RST_CAM */ | ||
362 | gpio_request(GPIO_PTZ4, NULL); | ||
363 | gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */ | ||
364 | |||
365 | ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB); | ||
306 | 366 | ||
307 | platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20); | 367 | platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20); |
308 | 368 | ||
@@ -316,18 +376,6 @@ device_initcall(ap325rxa_devices_setup); | |||
316 | 376 | ||
317 | static void __init ap325rxa_setup(char **cmdline_p) | 377 | static void __init ap325rxa_setup(char **cmdline_p) |
318 | { | 378 | { |
319 | /* LCDC configuration */ | ||
320 | ctrl_outw(ctrl_inw(PORT_PHCR) & ~0xffff, PORT_PHCR); | ||
321 | ctrl_outw(ctrl_inw(PORT_PLCR) & ~0xffff, PORT_PLCR); | ||
322 | ctrl_outw(ctrl_inw(PORT_PMCR) & ~0xffff, PORT_PMCR); | ||
323 | ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x03ff, PORT_PRCR); | ||
324 | ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01C0, PORT_HIZCRA); | ||
325 | |||
326 | /* CEU */ | ||
327 | ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB); | ||
328 | ctrl_outw(ctrl_inw(PORT_PSELD) & ~0x0003, PORT_PSELD); | ||
329 | ctrl_outw((ctrl_inw(PORT_PZCR) & ~0xff00) | 0x5500, PORT_PZCR); | ||
330 | ctrl_outb((ctrl_inb(PORT_PZDR) & ~0xf0) | 0x20, PORT_PZDR); | ||
331 | } | 379 | } |
332 | 380 | ||
333 | static struct sh_machine_vector mv_ap325rxa __initmv = { | 381 | static struct sh_machine_vector mv_ap325rxa __initmv = { |