[S390] Inline assembly cleanup.

Major cleanup of all s390 inline assemblies. They now have a common
coding style. Quite a few have been shortened, mainly by using register
asm variables. Use of the EX_TABLE macro helps  as well. The atomic ops,
bit ops and locking inlines new use the Q-constraint if a newer gcc
is used.  That results in slightly better code.

Thanks to Christian Borntraeger for proof reading the changes.

Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>

1 files changed, 62 insertions, 64 deletions

diff --git a/arch/s390/math-emu/math.c b/arch/s390/math-emu/math.c
index b4957c84e4d6..6b9aec5a2c18 100644
--- a/arch/s390/math-emu/math.c
+++ b/arch/s390/math-emu/math.c
@@ -1564,52 +1564,52 @@ static int emu_tceb (struct pt_regs *regs, int rx, long val) {
 }
 
 static inline void emu_load_regd(int reg) {
-        if ((reg&9) != 0)         /* test if reg in {0,2,4,6} */
+        if ((reg&9) != 0)       /* test if reg in {0,2,4,6} */
                 return;
-        asm volatile (            /* load reg from fp_regs.fprs[reg] */
-                "     bras  1,0f\n"
-                "     ld    0,0(%1)\n"
-                "0:   ex    %0,0(1)"
-                : /* no output */
-                : "a" (reg<<4),"a" (&current->thread.fp_regs.fprs[reg].d)
-                : "1" );
+        asm volatile(           /* load reg from fp_regs.fprs[reg] */
+                "       bras    1,0f\n"
+                "       ld      0,0(%1)\n"
+                "0:     ex      %0,0(1)"
+                : /* no output */
+                : "a" (reg<<4),"a" (&current->thread.fp_regs.fprs[reg].d)
+                : "1");
 }
 
 static inline void emu_load_rege(int reg) {
-        if ((reg&9) != 0)         /* test if reg in {0,2,4,6} */
+        if ((reg&9) != 0)       /* test if reg in {0,2,4,6} */
                 return;
-        asm volatile (            /* load reg from fp_regs.fprs[reg] */
-                "     bras  1,0f\n"
-                "     le    0,0(%1)\n"
-                "0:   ex    %0,0(1)"
-                : /* no output */
-                : "a" (reg<<4), "a" (&current->thread.fp_regs.fprs[reg].f)
-                : "1" );
+        asm volatile(           /* load reg from fp_regs.fprs[reg] */
+                "       bras    1,0f\n"
+                "       le      0,0(%1)\n"
+                "0:     ex      %0,0(1)"
+                : /* no output */
+                : "a" (reg<<4), "a" (&current->thread.fp_regs.fprs[reg].f)
+                : "1");
 }
 
 static inline void emu_store_regd(int reg) {
-        if ((reg&9) != 0)         /* test if reg in {0,2,4,6} */
+        if ((reg&9) != 0)       /* test if reg in {0,2,4,6} */
                 return;
-        asm volatile (            /* store reg to fp_regs.fprs[reg] */
-                "     bras  1,0f\n"
-                "     std   0,0(%1)\n"
-                "0:   ex    %0,0(1)"
-                : /* no output */
-                : "a" (reg<<4), "a" (&current->thread.fp_regs.fprs[reg].d)
-                : "1" );
+        asm volatile(           /* store reg to fp_regs.fprs[reg] */
+                "       bras    1,0f\n"
+                "       std     0,0(%1)\n"
+                "0:     ex      %0,0(1)"
+                : /* no output */
+                : "a" (reg<<4), "a" (&current->thread.fp_regs.fprs[reg].d)
+                : "1");
 }
 
 
 static inline void emu_store_rege(int reg) {
-        if ((reg&9) != 0)         /* test if reg in {0,2,4,6} */
+        if ((reg&9) != 0)       /* test if reg in {0,2,4,6} */
                 return;
-        asm volatile (            /* store reg to fp_regs.fprs[reg] */
-                "     bras  1,0f\n"
-                "     ste   0,0(%1)\n"
-                "0:   ex    %0,0(1)"
-                : /* no output */
-                : "a" (reg<<4), "a" (&current->thread.fp_regs.fprs[reg].f)
-                : "1" );
+        asm volatile(           /* store reg to fp_regs.fprs[reg] */
+                "       bras    1,0f\n"
+                "       ste     0,0(%1)\n"
+                "0:     ex      %0,0(1)"
+                : /* no output */
+                : "a" (reg<<4), "a" (&current->thread.fp_regs.fprs[reg].f)
+                : "1");
 }
 
 int math_emu_b3(__u8 *opcode, struct pt_regs * regs) {
@@ -2089,23 +2089,22 @@ int math_emu_ldr(__u8 *opcode) {
 
         if ((opc & 0x90) == 0) {           /* test if rx in {0,2,4,6} */
                 /* we got an exception therfore ry can't be in {0,2,4,6} */
-                __asm__ __volatile (       /* load rx from fp_regs.fprs[ry] */
-                        "     bras  1,0f\n"
-                        "     ld    0,0(%1)\n"
-                        "0:   ex    %0,0(1)"
-                        : /* no output */
-                        : "a" (opc & 0xf0),
-                          "a" (&fp_regs->fprs[opc & 0xf].d)
-                        : "1" );
+                asm volatile(           /* load rx from fp_regs.fprs[ry] */
+                        "       bras    1,0f\n"
+                        "       ld      0,0(%1)\n"
+                        "0:     ex      %0,0(1)"
+                        : /* no output */
+                        : "a" (opc & 0xf0), "a" (&fp_regs->fprs[opc & 0xf].d)
+                        : "1");
         } else if ((opc & 0x9) == 0) {     /* test if ry in {0,2,4,6} */
-                __asm__ __volatile (       /* store ry to fp_regs.fprs[rx] */
-                        "     bras  1,0f\n"
-                        "     std   0,0(%1)\n"
-                        "0:   ex    %0,0(1)"
-                        : /* no output */
-                        : "a" ((opc & 0xf) << 4),
-                          "a" (&fp_regs->fprs[(opc & 0xf0)>>4].d)
-                        : "1" );
+                asm volatile (          /* store ry to fp_regs.fprs[rx] */
+                        "       bras    1,0f\n"
+                        "       std     0,0(%1)\n"
+                        "0:     ex      %0,0(1)"
+                        : /* no output */
+                        : "a" ((opc & 0xf) << 4),
+                          "a" (&fp_regs->fprs[(opc & 0xf0)>>4].d)
+                        : "1");
         } else  /* move fp_regs.fprs[ry] to fp_regs.fprs[rx] */
                 fp_regs->fprs[(opc & 0xf0) >> 4] = fp_regs->fprs[opc & 0xf];
         return 0;
@@ -2120,23 +2119,22 @@ int math_emu_ler(__u8 *opcode) {
 
         if ((opc & 0x90) == 0) {           /* test if rx in {0,2,4,6} */
                 /* we got an exception therfore ry can't be in {0,2,4,6} */
-                __asm__ __volatile (       /* load rx from fp_regs.fprs[ry] */
-                        "     bras  1,0f\n"
-                        "     le    0,0(%1)\n"
-                        "0:   ex    %0,0(1)"
-                        : /* no output */
-                        : "a" (opc & 0xf0),
-                          "a" (&fp_regs->fprs[opc & 0xf].f)
-                        : "1" );
+                asm volatile(           /* load rx from fp_regs.fprs[ry] */
+                        "       bras    1,0f\n"
+                        "       le      0,0(%1)\n"
+                        "0:     ex      %0,0(1)"
+                        : /* no output */
+                        : "a" (opc & 0xf0), "a" (&fp_regs->fprs[opc & 0xf].f)
+                        : "1");
         } else if ((opc & 0x9) == 0) {     /* test if ry in {0,2,4,6} */
-                __asm__ __volatile (       /* store ry to fp_regs.fprs[rx] */
-                        "     bras  1,0f\n"
-                        "     ste   0,0(%1)\n"
-                        "0:   ex    %0,0(1)"
-                        : /* no output */
-                        : "a" ((opc & 0xf) << 4),
-                          "a" (&fp_regs->fprs[(opc & 0xf0) >> 4].f)
-                        : "1" );
+                asm volatile(           /* store ry to fp_regs.fprs[rx] */
+                        "       bras    1,0f\n"
+                        "       ste     0,0(%1)\n"
+                        "0:     ex      %0,0(1)"
+                        : /* no output */
+                        : "a" ((opc & 0xf) << 4),
+                          "a" (&fp_regs->fprs[(opc & 0xf0) >> 4].f)
+                        : "1");
         } else  /* move fp_regs.fprs[ry] to fp_regs.fprs[rx] */
                 fp_regs->fprs[(opc & 0xf0) >> 4] = fp_regs->fprs[opc & 0xf];
         return 0;